KR20050055913A - Shift register circuit - Google Patents

Abstract

The present invention relates to a shift register circuit for restoring bias stress applied during operation of a shift register to prevent a change in device characteristics to improve circuit stability. The present invention relates to a shift register circuit which is connected in a cascade and input through an input terminal. A shift register circuit comprising a plurality of stages for shifting and sequentially outputting a shift pulse, the shift register circuit comprising: an output buffer unit for selecting and outputting one of a clock signal and a first supply voltage according to voltages of a first node and a second node; Applying a first control unit controlling the first node according to a start pulse, a second control unit controlling the second node according to the start pulse and a clock signal, and a clock signal having a negative phase to the first node And a third control unit for controlling.

Description

Shift register circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display device, and more particularly to a shift register circuit suitable for recovering a characteristic change of an applied voltage when driving a driving circuit to improve the reliability of the circuit.

As the information society develops, the demand for display devices is increasing in various forms.In recent years, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and vacuum fluorescent display (VFD) have been developed. Various flat panel display devices have been studied, and some are already used as display devices in various devices.

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness and low power consumption, and mobile type such as notebook computer monitor. In addition, it is being developed in various ways such as a television for receiving and displaying a broadcast signal, a monitor of a computer.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display as a general screen display device in various parts, development of high quality images such as high definition, high brightness, and large area is required while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel has a predetermined space and is bonded to the first and second glass substrates. And a liquid crystal layer injected between the first and second glass substrates.

The first glass substrate (TFT array substrate) may include a plurality of gate lines arranged in one direction at a predetermined interval, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin films which are switched by signals of the gate line to transfer the signal of the data line to each pixel electrode Transistors are formed.

The second glass substrate (color filter substrate) includes a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common electrode for implementing an image. Is formed.

The first and second glass substrates are bonded to each other by a seal material having a predetermined space by a spacer and having a liquid crystal injection hole, so that the liquid crystal is injected between the two substrates.

Hereinafter, a driving circuit of a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a driving circuit of a general liquid crystal display device.

As shown in FIG. 1, a plurality of gate lines G and a data line D are arranged in a direction perpendicular to each other to have a matrix-type pixel region, and the liquid crystal display panel 21. ) Is divided into a driving circuit unit 22 for supplying a driving signal and a data signal, and a backlight 28 for providing a constant light source to the liquid crystal display panel 21.

Here, the driving circuit unit 22 drives a gate to the data driver 21b for inputting a data signal to each data line of the liquid crystal display panel 21 and the gate lines G of the liquid crystal display panel 21. A gate driver 21a for applying a pulse, display data R, G, and B input from a driving system 27 of a liquid crystal display panel, vertical and horizontal synchronization signals Vsync, Hsync, a clock signal DCLK, and the like. A timing controller that receives a control signal and formats and outputs each display data, a clock, and a control signal at a timing suitable for each data driver 21b and the gate driver 21a of the liquid crystal display panel 21 to reproduce a screen. 23, a power supply unit 24 for supplying a voltage required for the liquid crystal display panel 21 and each part, and a digital input from the data driver 21b by receiving power from the power supply unit 24; A gamma reference voltage unit 25 for supplying a reference voltage necessary for converting data into analog data, a constant voltage VDD used in the liquid crystal display panel 21 using the voltage output from the power supply unit 24, DC / DC converter 26 for outputting a gate high voltage VGH, a gate low voltage VGL, a reference voltage Vref, a common voltage Vcom, and an inverter 29 for driving the backlight 28. It is configured to include.

The operation of the driving circuit of the general liquid crystal display device configured as described above is as follows.

That is, the timing controller 23 controls the display data R, G, and B, and the control signals such as the vertical and horizontal synchronization signals Vsync and Hsync and the clock signal DCLK, which are input from the driving system 27 of the liquid crystal display panel. Since the data driver 21b and the gate driver 21a of the liquid crystal display panel 21 provide the display data, the clock, and the control signal at a timing suitable for reproducing the screen, the gate driver 21a A gate driving pulse is applied to each gate line G of the liquid crystal display panel 21 and the data driver 21b inputs a data signal to each data line D of the liquid crystal display panel 21 in synchronization with the gate driving pulse. Display the input video signal.

At this time, the backlight 28 provides a backlight having a constant brightness regardless of the brightness of the input video signal.

2 is a block diagram schematically illustrating a conventional shift register circuit, FIG. 3 is a detailed circuit diagram illustrating each stage illustrated in FIG. 2, and FIG. 4 is a waveform diagram illustrating input / output signals of the stage of FIG. 3. .

First, as shown in FIG. 2, the conventional shift register circuit is composed of n stages ST1 to STn connected to each other and connected to respective output terminals Vout 1 to Vout n, respectively. It is driven by using the pulses SP, VDD, VSS and four cyclic clocks CLK1 to CLK4.

The start pulse SP is input to the first stage ST1, and the second to nth stages ST2 to STn are output signals G1 to Gn-1 of the previous stage and four cyclic clock signals CLK1. 2 to CLK4 select row lines connected to the pixel column by two clock signals.

As illustrated in FIG. 3, each of the stages ST1 to STn includes a first control unit 51 for controlling a Q node according to a start pulse SP and a fourth clock signal CLK4, and a third clock signal ( A second control section 52 for controlling the QB node in accordance with CLK3 and the start pulse SP and a buffer section 53 composed of a buffer transistor for generating an output.

Here, the first control unit 51 controls the sixth NMOS transistor T6 of the buffer unit 53 through the Q node so that the first clock signal CLK1 is supplied to the output signal Vout1 through the output line. .

To this end, the first control unit 51 inputs a first NMOS transistor T1, diode-connected to a start pulse input line, the first NMOS transistor T1, and a fourth clock signal CLK4. A second NMOS transistor T2 is connected between the line and the Q node.

The second control unit 52 controls the seventh NMOS transistor T7 of the buffer unit 53 and the third NMOS transistor T3 for discharging the Q node after the output is generated through the QB node. The voltage VSS is used to keep the Q node and the output stage off for one frame until the next output.

To this end, the second controller 52 may include a fourth NMOS transistor T4 and a fourth NMOS transistor connected between the second supply voltage VDD input line, the third clock signal CLK3 input line, and the QB node. And a fifth NMOS transistor T5 connected between the T4 and the start pulse SP input line and the first supply voltage VSS input line.

The buffer unit 53 generates a sixth NMOS transistor T6 that generates an output when the first clock signal CLK1 is applied according to the voltage of the Q node, and the first supply voltage VSS according to the charging of the QB node. And a seventh NMOS transistor T7 for keeping the output line off.

In addition, the first control unit 51 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventh NMOS transistor T7 ( T3) is further provided.

As shown in FIG. 4, the conventional shift register circuit configured as described above is driven by a start signal and four clock signals that are cyclically delayed by one clock, and the four clock signals have a voltage width of 10V or more. Supplied in bipolar type. It is assumed here that the potential of 20V is high and the potential of 0V is low. The operation of the shift register with reference to these driving waveforms is as follows.

First, when the start pulse SP and the fourth clock signal CLK4 become high simultaneously in the T1 period, the first and second NMOS transistors T1 and T2 are turned on and the Q node is constant. Charged to voltage (about VDD-Vth). As a result, the sixth NMOS transistor T6 to which the gate terminal is connected by the Q node charging is turned on.

At the same time, the fifth NMOS transistor T5 is turned on by the start signal, and the QB node is turned off by the first supply voltage VSS. As a result, the third and seventh NMOS transistors T3 and T7 having the gate terminal connected to the QB node are turned off.

Subsequently, when one clock signal CLK1 is applied in the T2 period, since the Q node is in a floating state, the voltage increases due to the bootstrapping phenomenon by applying the clock signal, and thus the Q node has a very high voltage. (>> VDD), and thus an output is generated at the output line through the sixth NMOS transistor T6 in an on state without a voltage decrease.

Accordingly, a very high positive bias voltage is applied to the gate of the sixth NMOS transistor T6 constituting the buffer unit 53 by the bootstrapping phenomenon, and the gate driving circuit is applied due to the application of the high voltage due to driving. The device characteristic change (threshold voltage shift) of the transistor constituting the transistor occurs to reduce the stability of the circuit.

When the first clock signal CLK1 becomes low in the T3 period, the output line that was in the high state is discharged through the buffer transistor in the on state. At this time, the voltage of the Q node increased by bootstrapping by the application of the first clock signal CLK1 returns to the high voltage of the principle and keeps the buffer transistor on.

When the third clock signal CLK3 becomes high in the T4 period, the fourth NMOS transistor T4 is turned on so that the QB node is charged with 20 V, which is the second supply voltage VDD. The NMOS transistors T3 and T7 are turned on. Through the turned-on third NMOS transistor T3, the Q node is discharged and turned off, and remains off for one frame until the next output occurs. In addition, the output line is kept off by the seventh NMOS transistor. After the output is generated, the QB node remains on for one frame until the next output is generated by the third clock signal and the second supply voltage VDD.

When the fourth clock signal CLK4 becomes high in the T5 period, the second NMOS transistor T2 is turned on. However, since the first and fifth NMOS transistors T1 and T5 maintain the turn-off state, the QB node remains on. Therefore, since the third and seventh NMOS transistors T3 and T7 continue to be turned on, the output line of the first stage ST1 maintains an off (VSS) state.

When the shift register circuit described above is configured as an NMOS transistor, in order to apply a swing voltage of 20V to 25V to the liquid crystal display gate line, the voltage of the clock pulse input to the shift register composed of the NMOS transistor should be input from 0V to 20V.

Similarly, in order to apply a swing voltage of 20V to a gate line of a liquid crystal display driven by a shift register composed of a PMOS transistor, an input clock voltage having a swing voltage of -8V to 12V is required to the shift register composed of a PMOS transistor. The voltage can be changed depending on the model.

However, the driving circuit of the conventional liquid crystal display device as described above has the following problems.

That is, when an output is generated from the gate driving circuit to the output line through the buffer transistor, a very high bias stress is applied to the buffer transistor due to the sudden increase in the voltage applied to the Q node due to the bootstrapping phenomenon, and thus the element of the buffer transistor The characteristics (shift of threshold voltage) change, and the stability of the circuit is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. The present invention provides a shift register circuit which improves the stability of a circuit by restoring the characteristic change caused by the positive bias stress applied during the operation of the shift register. The purpose is to provide.

In the shift register circuit according to the present invention for achieving the above object is a shift register circuit consisting of a plurality of stages are sequentially connected and outputs the shift pulse sequentially by shifting the start pulse input through the input terminal, An output buffer unit for selecting and outputting one of a plurality of clock signals and a first supply voltage according to voltages of the first and second nodes, a first control unit controlling the first node according to the start pulse, and the start pulse And a second control unit controlling the second node according to a clock signal, and a third control unit applying and controlling a clock signal having a negative phase to the first node.

Hereinafter, the shift register circuit according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a detailed circuit diagram illustrating a shift register circuit according to a first embodiment of the present invention, and FIG. 6 is a waveform diagram illustrating input / output signals of the shift register circuit according to the first embodiment of the present invention.

First, the shift register circuit is composed of a plurality of stages that are cascade-connected and shift the start pulse input through the input terminal to sequentially output the shift pulse. One stage will be described with an example.

As shown in FIG. 5, the first control unit 101 controls the Q node according to the start pulse SP and the fourth clock signal CLK4, and according to the third clock signal CLK3 and the start pulse SP. A second control unit 102 for controlling the QB node, a buffer unit 103 including a buffer transistor for selectively generating an output in an output line according to the charge / discharge state of the Q node, and the first control unit 101 And a third controller 104 for applying a negative bias voltage to the Q node, which is an output terminal.

Here, the first control unit 101 controls the sixth NMOS transistor T6 of the buffer unit 103 through the Q node, and when the Q node is charged and turned on, by the applied clock signal CLK1. The output signal Vout1 is supplied to the output line.

To this end, the first control unit 101 inputs the first NMOS transistor T1, the first NMOS transistor T1, and the fourth clock signal CLK4, which are diode-connected to the start pulse SP input line. A second NMOS transistor T2 is connected between the line and the Q node. At this time, the start signal is synchronized with the fourth clock signal CLK4.

The second control unit 102 controls the seventh NMOS transistor T7 of the buffer unit 103 through a QB node, and the first supply voltage VSS is supplied to the output signal Vout1 through an output line. Keep the output line off.

To this end, the second controller 102 includes a fourth NMOS transistor T4 and a fourth NMOS transistor connected between the second supply voltage VDD input line, the third clock signal CLK3 input line, and the QB node. And a fifth NMOS transistor T5 connected between the T4 and the start pulse SP input line and the first supply voltage VSS input line.

The buffer unit 103 selects the first clock signal CLK1 according to the charge / discharge state of the Q node and supplies the sixth NMOS transistor T6 to the output line and the charge / discharge state of the QB node. A seventh NMOS transistor T7 selects and supplies a first supply voltage VSS to an output line.

In addition, the first control unit 103 is connected between the Q node and the QB node and the first supply voltage VSS input line to control the Q node in dual operation with the seventh NMOS transistor T7 ( T3) is further provided.

In addition, the third controller 104 includes an eighth and ninth NMOS transistors T8 and T9 connected in series between the Q node and a clock signal Vneg having a negative phase applied externally. The gates of the ninth NMOS transistors T8 and T9 are commonly connected to the next stage and are driven.

As shown in FIG. 6, the shift register circuit according to the present invention configured as described above is supplied with the first to fourth clock signals CLK1 to CLK4 having a phase delayed by one clock in sequence.

Here, the fourth clock signal CLK4 has a phase synchronized with the start pulse SP. The first to fourth clock signals CLK1 to CLK4 including the start pulse SP are supplied in a bipolar type having a swing voltage of 10V or more.

It is assumed here that the potential of 20V is high and the potential of 0V is low. In addition, the clock signal Vneg having the negative phase applied to each stage has the same period as the third clock signal CLK3 that charges the QB node and uses a clock signal having the opposite phase. The swing voltage of the clock signal Vneg having a negative phase makes the first supply VSS a high supply, and the low voltage is any lower than the first supply Vss. Use voltage.

The operation of the shift register with reference to these driving waveforms is as follows. First, when the start pulse SP and the fourth clock signal CLK4 become high simultaneously in the T1 period, the first and second NMOS transistors T1 and T2 are turned on and the Q node is constant. Charged to voltage (about VDD-Vth).

As a result, the sixth NMOS buffer transistor T6 to which the gate terminal is connected by the Q node charging is turned on. At the same time, the fifth NMOS transistor T5 is turned on by the start pulse, and the QB node is turned off by the first supply power source VSS. As a result, the third and seventh NMOS transistors T3 and T7 having the gate terminal connected to the QB node are turned off.

Subsequently, when one clock signal CLK1 is applied in the T2 period, since the Q node is in a floating state, the voltage increases due to the bootstrapping phenomenon by applying the clock signal, and thus the Q node has a very high voltage. (>> VDD), and thus an output is generated in the output line through the sixth NMOS transistor T6 in an on state without a voltage decrease.

Accordingly, a very high positive bias voltage is applied to the gate of the sixth NMOS transistor T6 constituting the buffer unit due to the bootstrapping phenomenon, and due to the application of the high voltage due to driving, Device characteristic changes (threshold voltage shifts) occur to reduce the stability of the circuit.

When the first clock signal CLK1 becomes low in the T3 period, the output line which was in the high state is discharged through the sixth NMOS transistor T6 in the on state. At this time, the voltage of the Q node increased by bootstrapping by the application of the first clock signal CLK1 returns to the high voltage of the principle and keeps the sixth NMOS transistor T6 on.

When the third clock signal CLK3 becomes high in the T4 period, the fourth NMOS transistor T4 is turned on so that the QB node is charged with 20 V, which is the second supply voltage VDD. The NMOS transistors T3 and T7 are turned on. Through the turned-on third NMOS transistor T3, the Q node is discharged to be in an off state, and remains off for one frame until the next output occurs. When the third clock signal CLK3 becomes high in the T4 period, the output of the next stage n + 2 is output. At this time, the output from the next stage (n + 2) stage turns on the eighth and ninth NMOS transistors (T8, T9) of the nth stage stage, and applies a clock signal Vneg having a negative phase to the Q node.

In this case, when a clock signal Vneg having a negative phase having the same period as that of the third clock signal CLK3 is applied, a negative voltage is applied to the Q-node (part B of FIG. 6).

Therefore, when the first clock signal CLK1 is applied and the output occurs, the characteristic change caused by the very high positive bias stress caused by the applied bootstrapping phenomenon is Q using a clock signal Vneg having a negative phase. A clock signal having a negative phase having an opposite polarity is applied to the node to recover the characteristic change of the sixth NMOS transistor T6 due to the positive bias during operation, thereby improving the reliability of the circuit.

When the fourth clock signal CLK4 becomes high in the T5 period, the second NMOS transistor T2 is turned on. However, since the first and fifth NMOS transistors T1 and T5 maintain the turn-off state, the QB node remains on.

Therefore, since the third and seventh NMOS transistors T3 and T7 continue to be turned on, the output line of the first stage ST1 maintains an off (VSS) state. At this time, the clock signal Vneg having the negative phase applied to the Q node becomes the high state VSS, and the voltage of the Q node becomes Vss as time passes through the third NMOS transistor T3.

Accordingly, in the shift register circuit of the present invention, a clock signal having a negative phase is applied to the Q node to compensate for the stress effect caused by the positive bias voltage, thereby canceling the characteristic change caused by the positive bias stress.

7 is a circuit diagram showing a shift register circuit according to a second embodiment of the present invention, and FIG. 8 is a timing diagram showing an input / output signal of the shift register circuit according to the second embodiment of the present invention.

As shown in Figs. 7 and 8, the shift register circuit according to the second embodiment has the same configuration and operation as the shift register circuit according to the first embodiment, except that it is connected to the gate of the third control unit 104. The part to be connected is connected to the third clock signal CLK3 rather than the next stage.

9 is a timing diagram showing a simulation result of a shift register circuit according to the present invention.

As shown in FIG. 9, it can be seen that a clock signal having a negative phase corresponding to a positive bias voltage is applied to a Q node.

FIG. 10 is a circuit diagram illustrating a shift register circuit according to a third embodiment of the present invention, and FIG. 11 is a panel timing diagram illustrating input / output signals of the shift register circuit according to a third embodiment of the present invention.

10 and 11, the shift register circuit according to the third embodiment has the same configuration and operation as the shift register circuit according to the first embodiment. However, as in the first and second embodiments, the source electrode of the third NMOS transistor T3 is disconnected from the existing Vss and connected to the clock signal Vneg having a negative phase so as to be negative to the Q node without passing through the third controller. It is characterized by applying the power.

In this case, all the third NMOS transistors T3 of each stage constituting the shift register are connected to the clock signal Vneg having the same negative phase, and after one frame driving, a blank time area is used. Is applied to the Q node with negative phase. In the case of the third embodiment, the third transistor in each stage serves as a third control unit for applying a clock signal having a negative phase to the Q node.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those of ordinary skill in Esau.

As described above, the shift register circuit according to the present invention has the following effects.

That is, by applying a clock signal having a negative phase corresponding to the positive bias voltage to compensate for the stress effect caused by the positive bias, the characteristics of the output buffer circuit due to the positive bias stress can be canceled to improve the reliability of the circuit.

1 is a block diagram showing a driving circuit of a general liquid crystal display device

2 is a block diagram schematically illustrating a conventional shift register circuit.

3 is a detailed circuit diagram showing each stage shown in FIG.

4 is a waveform diagram illustrating input / output signals of the stage of FIG.

5 is a detailed circuit diagram showing a shift register circuit according to a first embodiment of the present invention.

6 is a waveform diagram showing an input / output signal of a shift register according to a first embodiment of the present invention;

7 is a detailed circuit diagram showing a shift register circuit according to a second embodiment of the present invention.

8 is a waveform diagram showing an input / output signal of a shift register circuit according to a second embodiment of the present invention;

9 is a timing diagram showing a simulation result of a shift register circuit according to the present invention.

10 is a detailed circuit diagram showing a shift register circuit according to a third embodiment of the present invention.

Fig. 11 is a waveform diagram showing input / output signals of the shift register circuit according to the third embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

101: first control unit 102: second control unit

103: output buffer section 104: third control section

Claims (14)

A shift register circuit comprising a plurality of stages that are connected in a cascade and sequentially output a shift pulse by shifting a start pulse input through an input terminal. An output buffer unit for selecting and outputting one of a plurality of clock signals and a first supply voltage according to voltages of the first and second nodes; A first controller for controlling the first node according to the start pulse; A second controller for controlling the second node according to the start pulse and a clock signal; And a third controller configured to apply and control a clock signal having a negative phase to the first node. 2. The shift register circuit according to claim 1, wherein each stage is composed of only thin film transistors having channels of the same type. 2. The shift register circuit according to claim 1, wherein each stage is composed only of an amorphous silicon thin film transistor.  The shift register circuit of claim 1, wherein the third controller is driven by a next stage of the plurality of stages. The shift register circuit of claim 1, wherein the third controller is driven by one clock signal among a plurality of clock signals applied from the outside. 2. The shift register circuit of claim 1, wherein the third control unit is driven by a third transistor whose source is separated from the first supply voltage and connected to a clock signal having a negative phase. The NMOS transistor of claim 1, wherein the first control unit comprises: a first NMOS transistor diode-connected to a start pulse input line; and a second NMOS connected between the first NMOS transistor, a plurality of clock signal input lines, and a first node. A shift register comprising a transistor. The second NMOS transistor of claim 1, wherein the second controller comprises: a fourth NMOS transistor connected between the second supply voltage input line, the third clock signal input line, and the second node; A shift register circuit comprising a fifth NMOS transistor connected between a supply voltage input line. The sixth NMOS transistor of claim 1, wherein the output buffer unit selects one clock signal among a plurality of clock signals according to a voltage of a first node and supplies the same to a output line, and a first supply according to a voltage of a second node. And a seventh NMOS transistor for selecting a voltage and supplying the voltage to an output line. 6. The third NMOS of claim 1 or 5, wherein the first controller is connected between the first node and the second node and the first supply voltage input line to control the first node in dual operation with the seventh NMOS transistor. The shift register circuit further comprises a transistor. The eighth and ninth NMOS transistors of claim 1, wherein the third controller is configured in series between the first node and a clock signal having a negative phase applied from the outside, and has a next stage connected to each gate. And a shift register circuit. The shift register circuit of claim 1, wherein the third controller is configured by connecting sources of all third transistors of each stage to a clock signal having a separate negative phase. The shift register circuit according to claim 1 or 11, wherein a voltage lower than a first supply voltage is applied to the first node through a clock signal having a negative phase applied to the third controller. 7. The shift register circuit according to claim 1 or 6, wherein a voltage lower than a first supply voltage is applied to the first node through a clock signal having a negative phase applied to the third controller.