KR102460921B1 - Shift resister and display device having the same - Google Patents

Abstract

The shift register according to the present invention is composed of first to n-th stages and sequentially outputs gate pulses, and the output order of the gate pulses is set to be selectable in either direction. The n-th stage is a pull-up transistor that charges the output terminal in response to the voltage of the Q node, the first transistor that applies a turn-on voltage to the Q node in response to the previous stage gate pulse in the forward scan mode, and the start pulse in the reverse scan mode a second transistor for applying a turn-on voltage to the Q node in response to, and a forward direction for applying a turn-off voltage to the Q node in response to a dummy gate pulse applied after outputting an n-th gate pulse in the forward scan mode Includes a reset transistor.

Description

Shift register and display device including same

The present invention relates to a shift register and a display device including the same.

In the display device, data lines and gate lines are arranged to be perpendicular to each other, and pixels are arranged in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. A video data voltage is supplied to pixels of a display line to which a gate pulse is supplied, and video data is displayed while all display lines are sequentially scanned by the gate pulse.

The field of application of the display device is gradually diversifying, and as the spread of portable terminals becomes common, the types of display devices are also increasing. The position of the driving circuit part for driving the display device is also diversified according to the design and characteristics of the device to which the display device is applied. The output direction of the shift register for driving the gate line of the display panel according to each display device is also not limited to any one direction. The gate driver may be implemented in the form of a gate in panel (GIP) in the display panel. In order not to fix the output direction of the gate pulse in one direction, a circuit configuration different from the conventional one is required.

An object of the present invention is to provide a shift register capable of increasing compatibility according to types of display panels and a display device including the same.

The shift register according to the present invention is composed of first to n-th stages and sequentially outputs gate pulses, and the output order of the gate pulses is set to be selectable in either direction. The n-th stage is a pull-up transistor that charges the output terminal in response to the voltage of the Q node, the first transistor that applies a turn-on voltage to the Q node in response to the previous stage gate pulse in the forward scan mode, and the start pulse in the reverse scan mode a second transistor for applying a turn-on voltage to the Q node in response to, and a forward direction for applying a turn-off voltage to the Q node in response to a dummy gate pulse applied after outputting an n-th gate pulse in the forward scan mode Includes a reset transistor.

The shift register of the present invention can be applied to both a forward scan mode and a reverse scan mode by using transistors capable of setting and resetting a Q node in each of the stages.

In particular, since the present invention uses a forward reset transistor for the Q node of the last stage, even if the gate electrode of the second transistor is connected to the start pulse input terminal for the reverse scan mode, the reset operation of the Q node in the forward scan mode is smoothly performed. can do.

1 is a view showing a display device according to the present invention.
2 is a view showing a shift register according to the first embodiment.
3 is a diagram showing the timing of a gate pulse output from the shift register according to the first embodiment.
4 to 6 are views showing stages of the shift register according to the first embodiment.
7 is a diagram illustrating clock signals applied to the shift register and voltage changes of main nodes according to the first embodiment.
8 is a diagram illustrating a shift register according to the second embodiment.
9 is a diagram showing the timing of the gate pulse output from the shift register according to the second embodiment.
10 and 11 are diagrams illustrating stages of a shift register according to the second embodiment.
12 is a diagram illustrating clock signals applied to a shift register according to the second embodiment, and voltage changes of main nodes according to the clock signals.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the gate driving circuit of the present specification, the switch elements may be implemented as transistors of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although the n-type transistor is illustrated in the following embodiments, the present specification is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. The source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage. The invention is not limited by the source and drain of the transistor in the following embodiments.

1 is a diagram schematically showing a display device according to an embodiment of the present invention.

Referring to FIG. 1 , the display device of the present invention includes a display panel PNL and a drive IC DIC for driving the display panel PNL.

The display portion AA of the display panel PNL is formed by data lines DL, gate lines GL orthogonal to the data lines DL, and data lines DL and gate lines GL. It includes pixels P in a defined matrix form. The first pixel line HL1 refers to pixels P that are scanned by a gate pulse applied through the first gate line GL1 , and the n-th pixel line HLn is connected through the n-th gate line GLn. Refers to pixels P that are scanned by the applied gate pulse.

The display portion AA of the display panel PNL may be divided into a TFT array and a color filter array. A TFT array may be formed on an upper plate or a lower plate of the display panel PNL. The TFT array includes TFTs (Thin Film Transistor, T) formed at intersections of the data lines DL and the gate lines GL, the pixel electrode of the liquid crystal cell Clc charging the voltage of the data signal, and the common voltage ( Vcom) is supplied to the common electrode of the liquid crystal cell Clc, and a storage capacitor (Cst) (not shown) connected to the pixel electrode to maintain a data voltage, and the like, to display an input image. The storage capacitor is omitted from the figure.

A color filter array may be formed on an upper or lower plate of the display panel PNL. The color filter array includes a black matrix, a color filter, and the like. In the case of a COT (Color Filter on TFT) ? or TOC (TFT on Color Filter) ? model, a color filter and a black matrix together with a TFT array may be disposed on one substrate.

The gate driver 120 may be formed in the display panel PNL. The gate driver 120 includes a shift register that outputs a gate pulse synchronized with a data signal in response to a gate timing control signal input through the drive IC (DIC). The gate timing control signal includes a start pulse and a shift clock. The shift register sequentially supplies the gate pulses to the gate lines GL by shifting the gate pulses according to the shift clock timing.

The TFTs T of the display panel PNL are turned on according to a gate pulse to select a line of the display panel PNL in which data of an input image is written. The shift register may be directly formed on the substrate of the display panel PNL in the same process as the TFT array of the pixel array.

The drive IC DIC supplies the data signal of the input image to the data lines DL and supplies the gate timing control signal including the clock signals CLK to the gate driver 120 . The drive IC (DIC) includes a timing signal generator and a data driver.

The timing signal generator 100 transmits pixel data of an input image received from a host system (not shown) to the data driver 110 . The timing signal generator 100 receives a timing signal received in synchronization with pixel data, a data timing control signal for controlling the operation timing of the data driver 110 , and a data timing control signal for controlling the operation timing of the gate driver 120 . A gate timing control signal is generated. A demultiplexer (MUX) may be disposed between the drive IC (DIC) and the data lines (DL). In this case, the timing signal generator 100 generates a MUX control signal for controlling a demultiplexer (MUX).

The data driver 110 receives the pixel data (digital data) of the input image from the timing signal generator 100 during the display period, latches it, and then performs a digital-to-analog converter (hereinafter referred to as "DAC"). ) is supplied. The DAC converts the pixel data into a gamma compensation voltage to generate a voltage of the data signal.

In addition, the drive IC may further include a power supply unit (not shown). The power supply unit generates DC power required for driving the display panel PNL by using a DC-DC converter. The DC-DC converter includes a charge pump, a regulator, a buck converter, a boost converter, and the like.

The gate driver 120 outputs a gate pulse in response to the clock signals CLK and the start pulse VST. The gate driver 120 may be implemented as a shift register including stages connected to each other.

FIG. 2 is a diagram illustrating a shift register according to the first embodiment, and FIG. 3 is a diagram illustrating timing of gate pulses output from the shift register. In FIG. 3 , the forward reset signal DG2 and the reverse reset signal DG1 may be output using a dummy stage (not shown) or may be separately applied signals.

4 to 6 are views showing a stage according to the first embodiment. In particular, FIG. 4 is a diagram illustrating a configuration of a first stage, FIG. 5 is a diagram illustrating a configuration of a k-th stage, and FIG. 6 is a diagram illustrating a configuration of an n-th stage for driving the last pixel line.

The forward driving voltage FWD and the reverse driving voltage REV shown in FIGS. 4 to 6 vary according to the scan mode. The following [Table 1] is a table showing the voltage levels of the forward driving voltage and the reverse driving voltage according to the scan mode.

Forward scan mode Reverse scan mode FWD VGH VGL REV VGL VGH

Referring to [Table 1], the forward driving voltage FWD maintains the high potential voltage of the turn-on voltage level in the forward scan mode and the low potential voltage of the turn-off voltage level in the reverse scan mode. The reverse driving voltage REV maintains the high potential voltage of the turn-on voltage level in the reverse scan mode and the low potential voltage of the turn-off voltage level in the forward scan mode.

2 to 6 , the shift register according to the present invention includes first to n-th stages STG1 to STG[n] (n is a natural number) that are dependently connected to each other. The first stage STG generates a first gate pulse G1 and applies it to the first gate line GL1 . The n-th stage STG[n] generates an n-th gate pulse G[n] and applies it to the n-th gate line GL[n].

Each of the first stages STG1 to n-th stages STGN includes a first transistor T1 , a second transistor T2 , a node controller NCON, a pull-up transistor Tpu, and a pull-down transistor Tpd. .

The first transistor T1 has a gate electrode receiving a start pulse VST or a (k-1)th gate pulse Gout[k-1], a drain electrode connected to an input terminal of the forward driving voltage FWD, and a Q node a source electrode connected to The second transistor T2 includes a gate electrode to which a subsequent gate pulse is input, a drain electrode connected to the Q node, and a source electrode connected to an input terminal of the reverse driving voltage REV. The node controller NCON controls voltages of the Q node and the QB node. In particular, the node control unit NCON maintains the QB node at the turn-off voltage in the section where the Q node is the turn-on voltage, and maintains the Q node at the turn-off voltage in the section where the QB node is the turn-on voltage. may include The pull-up transistor Tpu includes a gate electrode connected to the Q node, a drain electrode connected to an input terminal of the clock signal CLK, and a source electrode connected to an output terminal Nout. The pull-down transistor Tpd includes a gate electrode connected to the QB node, a drain electrode connected to an output terminal Nout, and a source electrode connected to an input terminal of the low potential voltage VGL. The first capacitor CQ stably maintains the voltage of the Q node, and the second capacitor CQB stably maintains the voltage of the QB node.

The first stage STG1 further includes a reverse reset transistor Tre1 (hereinafter, referred to as a first reset transistor). The first reset transistor Tre1 of the first stage STG1 is turned on in response to a reverse reset signal DG1 (hereinafter, referred to as a first dummy gate pulse).

The n-th stage STGn further includes a forward reset transistor (Tre2 or less, a second reset transistor). The second reset transistor Tre2 of the n-th stage STGn is turned on in response to a forward reset signal DG2 (hereinafter, referred to as a second dummy gate pulse).

With this configuration, the shift register according to the present invention can have a forward scan mode and a reverse scan mode.

In the forward scan mode, the first stage STG1 starts driving by the start pulse VST, and outputs the first gate pulse G1. Subsequently, the second stage STG2 outputs the second gate pulse G2. As such, the (k-1)th (k is a natural number greater than 1 and less than n) stage STG[k-1]) outputs the (k-1)th gate pulse G[k-1], Subsequently, the kth stage STGk outputs the kth gate pulse Gk.

In the reverse scan mode, the n-th stage STGn outputs the n-th gate pulse Gn in response to the start pulse VST. Then, the (n-1)th stage is driven to output the (n-1)th gate pulse G[n-1]. As such, the k-th stage STGk outputs the k-th gate pulse Gk, and then the (k-1)-th stage STG[k-1]) generates the (k-1)-th gate pulse G[k]. -1]) is printed.

The driving of the shift registers in the forward scan mode is as follows.

In the forward scan mode, the first transistor T1 of each stage sets the Q node in response to the previous stage gate pulse. The first transistor T1 of the first stage STG1 sets the Q node in response to the start pulse VST. The first transistor T1 of the second stage STG2 sets the Q node in response to the first gate pulse G1 . Similarly, the first transistor T1 of the kth stage STG[k] sets the Q node in response to the (k-1)th gate pulse G[k-1], and the nth stage STG The first transistor T1 of [n]) sets the Q node in response to the (n-1)th gate pulse G[n-1]. Setting the Q node means precharging the Q node to a turn-on voltage.

In the forward scan mode, the second transistor T2 of the first to (n-1)th stages STG1 to STG[n-1] resets the Q node in response to the subsequent gate pulse. For example, the second transistor T2 of the first stage STG1 resets the Q node in response to the second gate pulse G2 , and the second transistor T2 of the second stage STG2 has the third gate pulse Reset the Q node in response to (G3). Similarly, the second transistor T2 of the kth stage STG[k] resets the Q node in response to the (k+1)th gate pulse G[k+1].

In the forward scan mode, the n-th stage STG[n] resets the Q node using the second reset transistor Tre2. The second reset transistor Tre2 is turned on in response to the second dummy gate pulse DG2. The second transistor T2 of the n-th stage STGn sets the Q node in response to the start signal VST in the reverse scan mode.

In the reverse scan mode, the second transistor T2 of each stage sets the Q node in response to the previous stage gate pulse. In the reverse scan mode, the gate pulse preceding the kth gate pulse Gk becomes the (k+1)th gate pulse G[k+1]. That is, the second transistor T2 of the n-th stage STG[n] sets the Q node in response to the start pulse VST. The second transistor T2 of the kth stage STGk sets the Q node in response to the (k+1)th gate pulse G[k+1]. Similarly, the second transistor T2 of the first stage STG1 sets the Q node in response to the second gate pulse G2.

In the reverse scan mode, the first transistor T1 of the second to n-th stages STG2 to STG[n] resets the Q node in response to the subsequent gate pulse. In the reverse scan mode, the gate pulse after the kth gate pulse Gk becomes the (k-1)th gate pulse G[k-1]. That is, the first transistor T1 of the nth stage STGn resets the Q node in response to the (n-1)th gate pulse G[n-1], and the first transistor T1 of the kth stage STGk The transistor T1 resets the Q node in response to the (k-1)th gate pulse G[k-1]. The first transistor T1 of the second stage STG1 resets the Q node in response to the first gate pulse G1 .

In the reverse scan mode, the first stage STG1 resets the Q node using the first reset transistor Tre1. The first reset transistor Tre1 is turned on in response to the first dummy gate pulse DG1.

7 is a diagram illustrating timings of clock signals applied to a shift register. In FIG. 7 , the voltage change of the Q node shows the change in the voltage of the Q node of the stage outputting the gate pulse during the output period of the first clock signal.

4 and 7, the operation of the first stage in the forward scan mode is as follows.

Until the first timing t1, the QB node is in a high potential voltage state, and the second capacitor CQB stably maintains the QB node is a turn-on voltage.

At a first timing t1 , the first transistor T1 precharges the Q node in response to the start signal VST.

At the second timing t2 , when the first clock signal CLK1 is input to the drain electrode of the pull-up transistor Tpu, the Q node is bootstrapped according to a voltage increase of the drain electrode of the pull-up transistor Tpu. . As the Q node is bootstrapped, the potential difference between the gate and the source of the pull-up transistor Tpu increases, and the pull-up transistor Tpu is turned on. As a result, the pull-up transistor Tpu charges the output terminal Nout using the first clock signal CLK1.

At the third timing t3 , the first clock signal CLK1 becomes a low potential voltage, and the output terminal Nout becomes a turn-off voltage. In addition, the second transistor T2 discharges the Q node to the low potential voltage VSS in response to the second gate pulse G2.

8 is a diagram illustrating a shift register according to a second embodiment of the present invention. 9 is a diagram illustrating output timing of gate pulses in a forward scan mode of FIG. 8 . In the second embodiment, the same reference numerals are used for the same components as those of the first embodiment, and detailed descriptions thereof will be omitted.

Referring to FIG. 8 , the shift register according to the second embodiment includes a first shift register SR1 and a second shift register SR2. The first shift register SR1 drives odd-numbered pixel lines, and the second shift register SR2 drives even-numbered pixel lines.

The first shift register SR1 includes the first to mth (m is a natural number satisfying the condition m<(n/4)) left stage LSTG driven using the left clock signals CLK1_L to CLK4_L. do. The m-th left stage LSTGm outputs a (4m-3)-th gate pulse and a (4m-1)-th gate pulse. 8 shows an embodiment in which "4m-3=n-1". Accordingly, the first left stage LSTG1 outputs the first gate pulse G1 and the third gate pulse G3, and the second left stage LSTG1 outputs the fifth gate pulse G5 and the seventh gate pulse G5 and the seventh gate pulse G3. G7) is output.

The second shift register SR2 includes first to m-th right stages RSTG1 to RSTGm driven using the right clock signals CLK1_R to CLK4_R. The m-th right stage LSTGm outputs a (4m-2)-th gate pulse and a 4m-th gate pulse. Accordingly, the first right stage RSTG1 outputs the second gate pulse G2 and the fourth gate pulse G4, and the second right stage RSTG2 outputs the sixth gate pulse G6 and the eighth gate pulse G6. G8) is output.

The shift register according to the second embodiment is capable of a forward scan mode and a reverse scan mode.

In the forward scan mode, the first left stage LSTG1 starts driving by the start pulse LVST, and sequentially outputs the first gate pulse G1 and the third gate pulse G3. Subsequently, the second left stage LSTG2 sequentially outputs the fifth gate pulse G5 and the seventh gate pulse G7. As such, the first shift register SR1 sequentially outputs odd-numbered gate pulses.

In the forward scan mode, the first right stage RSTG1 starts driving by the start pulse RVST, and sequentially outputs the second gate pulse G2 and the fourth gate pulse G4. Subsequently, the second right stage RSTG2 sequentially outputs the sixth gate pulse G6 and the eighth gate pulse G8. As described above, the second shift register SR2 sequentially outputs even-th gate pulses.

In the reverse scan mode, the mth left stage LSTGm starts driving by the start pulse LVST, and the (n-1)th gate pulse G[n-1] and the (n-3)th gate pulse It outputs (G[n-3]). Subsequently, the (m-1)th left stage (LSTG[m-1]) is performed with the (n-5)th gate pulse (G[n-5]) and the (n-7)th gate pulse (G[n-7] ) is output. As such, the first shift register SR1 outputs the odd-numbered gate pulses in the reverse order to drive the odd-numbered gate lines.

In the reverse scan mode, the m-th right stage RSTGm starts driving by the start pulse RVST, and generates the n-th gate pulse Gn and the (n-2)-th gate pulse G[n-2]. print out Subsequently, the second right stage RSTG2 outputs an (n-4)th gate pulse G[n-4] and an (n-6)th gate pulse G[n-6]. As described above, the second shift register SR2 outputs even-th gate pulses in the reverse order to drive even-th gate lines.

10 is a diagram illustrating a first left stage of the first shift register, and FIG. 11 is a diagram illustrating an m-th left stage of the first shift register. Although the left stages shown in FIGS. 10 and 11 are shown, the right stages also have substantially the same circuit configuration. Therefore, in FIGS. 10 and 11 , first to fourth clock signals CLK1 to CLK4 are denoted.

Referring to FIG. 10 , the first left stage LSTG1 of the first shift register SR1 includes the first transistor T1 and the second transistor T2 , the node controllers T3 to T12 , and the first pull-up transistor Tpu1 . ), a second pull-up transistor Tpu2 , a first pull-down transistor Tpd1 , a second pull-down transistor Tpd2 , and a first reset transistor Tre1 .

The first transistor T1 includes a gate electrode receiving the start pulse RVST, a drain electrode connected to an input terminal of the forward driving voltage FWD, and a source electrode connected to the Q node.

The second transistor T2 includes a gate electrode to which a subsequent gate pulse is input, a drain electrode connected to the Q node, and a source electrode connected to an input terminal of the reverse driving voltage REV.

The node controllers T3 to T12 control voltages of the Q node and the QB node. The node controllers T3 to T12 include QB node controllers T3, T4, and T5, inverters T6 and T12, and seventh to eleventh transistors T7 to T11. The QB node controllers T3, T4, and T5 include a forward X node charging unit T3 (hereinafter, referred to as the third transistor), a reverse X node charging unit T4 (hereinafter referred to as a fourth transistor), and a QB node charging unit T5 (hereinafter, referred to as a fourth transistor). fifth transistor). The inverters T6 and T12 include a QB node discharge unit T6 (hereinafter referred to as a sixth transistor) and a Q node discharge unit T12 (hereinafter referred to as a twelfth transistor).

The third transistor T3 includes a gate electrode connected to the input terminal of the forward driving voltage FWD, a drain electrode connected to the input terminal of the third clock signal CLK3, and a source electrode connected to the X node. The fourth transistor T4 includes a gate electrode connected to the input terminal of the reverse driving voltage REV, a drain electrode connected to the input terminal of the fourth clock signal CLK4, and a source electrode connected to the X node.

The third transistor T3 turns on the fifth transistor t5 during the output period of the third clock signal CLK3 in the forward scan mode, and the fourth transistor T4 turns on the fourth clock signal ( The fifth transistor T5 is turned on during the output period of CLK4).

The fifth transistor T5 includes a gate electrode connected to the X node, a drain electrode connected to the input terminal of the high potential voltage VGH, and a source electrode connected to the QB node. The fifth transistor T5 applies a turn-on voltage to the QB node in a period in which the X node is the turn-on voltage.

The sixth transistor T6 includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the input terminal of the low potential voltage VGL. The sixth transistor T6 applies a turn-off voltage to the QB node during a period in which the Q node is a turn-on voltage.

The seventh transistor T7 includes a gate electrode and a drain electrode receiving the APO signal APO, and a source electrode connected to the first output terminal Nout1 . The eighth transistor T8 includes a gate electrode receiving the APO signal APO, a drain electrode connected to the QB node, and a source electrode connected to an input terminal of the low potential voltage VGL. The ninth transistor T9 includes a gate electrode and a drain electrode receiving the APO signal APO, and a source electrode connected to the second output terminal Nout2. The seventh transistor T7 and the ninth transistor T9 apply a turn-on voltage to the first output terminal Nout1 and the second output terminal Nout2 in response to the APO signal APO. The eighth transistor T8 applies a turn-off voltage to the QB node in response to the APO signal APO.

The tenth transistor T10 includes a gate electrode connected to the input terminal of the high potential voltage VGH, a drain electrode connected to the Q node, and a source electrode connected to the BST1 node. The eleventh transistor T11 includes a gate electrode connected to the input terminal of the high potential voltage VGH, a drain electrode connected to the Q node, and a source electrode connected to the BST2 node. The tenth transistor T10 and the eleventh transistor T11 prevent the voltage of the Q node from being bootstrapped while the first and second pull-up transistors Tpu1 and Tpu2 are bootstrapped, thereby preventing the transistor connected to the Q node. Prevents instantaneous overloading of fields.

The first pull-up transistor Tpu1 includes a gate electrode connected to the node BST1 , a drain electrode connected to the input terminal of the first clock signal CLK1 , and a source electrode connected to the first output terminal Nout. The second pull-up transistor Tpu2 includes a gate electrode connected to the node BST2 , a drain electrode connected to the input terminal of the second clock signal CLK2 , and a source electrode connected to the second output terminal Nout.

The first pull-down transistor Tpd1 includes a gate electrode connected to the QB node, a drain electrode connected to the first output terminal Nout, and a source electrode connected to the input terminal of the low potential voltage VGL. The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a drain electrode connected to the second output terminal Nout, and a source electrode connected to an input terminal of the low potential voltage VGL.

The first reset transistor Tre1 includes a gate electrode receiving the first dummy gate pulse DG1 , a drain electrode receiving the forward driving voltage FWD, and a source electrode connected to the Q node. The first reset transistor Tre1 applies a turn-off voltage to the Q node in response to the first dummy gate pulse DG1 in the reverse scan mode.

The first capacitor CQ stably maintains the voltage of the Q node, and the second capacitor CQB stably maintains the voltage of the QB node.

Referring to FIG. 11 , the m-th left stage LSTGm of the first shift register SR1 includes the first transistor T1 and the second transistor T2 , the node controllers T3 to T12 , and the first pull-up transistor Tpu1 . ), a second pull-up transistor Tpu2 , a first pull-down transistor Tpd1 , a second pull-down transistor Tpd2 , and a second reset transistor Tre2 .

The first transistor T1 and the second transistor T2, the node controller, the first pull-up transistor Tpu1, the second pull-up transistor Tpu2, the first pull-down transistor Tpd1, and the second transistor T2 of the m-th left stage LSTGm The configuration of the 2 pull-down transistor Tpd2 is the same as that of the first stage STG1.

The second reset transistor Tre2 of the m-th left stage LSTGm connects the gate electrode connected to the second dummy gate pulse DG2, the drain electrode connected to the Q node, and the source electrode connected to the input terminal of the reverse driving voltage REV. include The second reset transistor Tre2 of the mth left stage LSTGm applies a turn-off voltage to the Q node in response to the second dummy gate pulse DG2 in the forward scan mode.

12 is a diagram illustrating a timing of a clock signal and a voltage change of a main node according thereto. In particular, Fig. 12 shows the first left stage node change.

Referring to FIGS. 10 and 12 , driving of the first left stage is as follows.

Until the start pulse LVST is applied, the QB node is in a high potential voltage state, and the second capacitor CQB stably maintains that the QB node is a turn-on voltage.

In a period in which the start pulse LVST is applied, the first transistor T1 precharges the Q node in response to the start signal LVST. When the Q node becomes the turn-on voltage, the tenth transistor T10 is diode-connected to apply the turn-on voltage to the BST1 node.

In a period in which the first clock signal CLK1 is applied, the BST1 node is bootstrapped according to a voltage increase of the drain electrode of the first pull-up transistor Tpu1. As the BST1 node is bootstrapped, the potential difference between the gate and the source of the first pull-up transistor Tpu1 increases, and the first pull-up transistor Tpu1 is turned on. As a result, the first output terminal Nout1 outputs the first gate pulse.

When the first clock signal CLK1 becomes the low potential voltage, the BST1 node is lowered to a certain level from the bootstrapped voltage, but also maintains the turn-on voltage at this time.

During the period in which the second clock signal CLK2 is applied, the BST2 node is bootstrapped according to a voltage increase of the drain electrode of the second pull-up transistor Tpu2 . As the BST2 node is bootstrapped, the potential difference between the gate and the source of the second pull-up transistor Tpu2 increases, and the second pull-up transistor Tpu2 is turned on. As a result, the second output terminal Nout2 outputs the third gate pulse.

In a period in which the third clock signal CLK3 is applied, the third transistor T3 applies a turn-on voltage to the X node. As a result, the fifth transistor T5 applies a turn-on voltage to the QB node. The twelfth transistor T12 discharges the Q node to the low potential voltage VGL in response to the QB node voltage. A period in which the third clock signal CLK3 is applied is a period in which the second left stage LSTG2 outputs the fifth gate pulse G5 . That is, in a period in which the third clock signal CLK3 is applied, the second transistor T2 applies a turn-off voltage to the Q node in response to the fifth gate pulse G5 .

In this way, in the forward scan mode, the first to (m-1)th left stages LSTG1 to LSTG[m-1) sequentially output odd-numbered gate pulses.

Subsequently, the mth left stage LSTGm shown in FIG. 11 outputs a (n−1)th gate pulse using the nth clock signal CLKn through the same process. The nth clock signal CLKn may be the second clock signal CLK2 or the fourth clock signal CLK4 .

Unlike the first to (m-1)th left stages LSTG[m-1], in the m-th left stage LSTGm, the gate electrode of the second transistor T2 receives the gate pulse of the subsequent stage. Instead, the start pulse LVST is input to perform a starting operation in the reverse scan mode. Accordingly, the second transistor T2 of the m-th left stage LSTGm does not perform an operation for resetting the Q node.

The twelfth transistor T12 of the mth left stage LSTGm resets the Q node in response to the QB node voltage. In order for the twelfth transistor T12 to be turned on, the X node for turning on the fifth transistor T5 must be a turn-on voltage. The X node becomes a turn-on voltage at the output timing of the (n+1)th clock signal CLK[n+1].

If the second reset transistor Tre2 is not present, the sixth transistor T6 is also turned on because the Q node cannot be discharged to the turn-off voltage at the timing when the twelfth transistor T12 is to be turned on. . The sixth transistor T6 operates to discharge the QB node voltage to a turn-off voltage. Accordingly, the QB node is simultaneously charged with the turn-on voltage by the fifth transistor T5 and discharged to the turn-off voltage by the twelfth transistor T12.

As a result, since the voltage of the QB node is not reliably inverted to the turn-on voltage and the Q node voltage is also unstable, an unwanted gate pulse may be output.

In contrast, the m-th left stage LSTGm of the present invention resets the Q node to a turn-off voltage using the second reset transistor Tre2. Therefore, even when the second transistor T2 is connected to the input terminal to which the start pulse is applied for the reverse scan mode, the Q node can be stably reset at the time when the gate pulse is terminated. As a result, it is possible to prevent an unwanted gate pulse from being output in the last stage.

In the present invention, the shift register discharges the QB node and the output terminals in an abnormal power-off situation. Abnormal power-off is a situation in which power is turned off without going through a normal power-off sequence, and may be, for example, when a battery is removed.

In order to prepare for an abnormal power-off situation, the drive IC (DIC) senses one or more voltage levels among the input power sources. The drive IC (DIC) generates an APO signal (APO) when the input power is below a preset threshold.

The seventh transistor T7 of the stages resets the QB node to a turn-off voltage in response to the APO signal APO. The tenth transistor T10 and the eleventh transistor T11 apply a turn-on voltage to the first and second output terminals Nout2 to discharge the voltage charged in the pixels P.

The data driver 110 discharges the data lines DL in response to the APO signal.

As a result, when it is determined that the input power Vin is abnormally cut off, the display device according to the second exemplary embodiment discharges all wires connected to the pixels to prevent afterimages and stains. If voltage remains in the gate driver 120 and the pixels P, when the display device resumes normal driving, the pixels P emit light at an undesired moment, which may cause a flicker phenomenon. In contrast, according to the present invention, the voltage of the gate driver 120 and the display panel PNL is discharged using the abnormal power-off detection unit 30 to prevent a flicker phenomenon that may occur when the display device is re-driven.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: Display panel DIC: Drive IC
100: timing signal generator 110: data driver
120: gate driver

Claims (9)

In the shift register comprising the first to n-th stages and sequentially outputting gate pulses, the output order of the gate pulses is selectable in any one of two directions,
The nth stage is
a pull-up transistor that charges the output stage in response to the voltage at the Q node;
a first transistor for applying a turn-on voltage to the Q node in response to a previous gate pulse in a forward scan mode;
a second transistor for applying a turn-on voltage to the Q node in response to a start pulse in a reverse scan mode; and
a forward reset transistor for applying a turn-off voltage to the Q node in response to a dummy gate pulse applied after outputting an n-th gate pulse in the forward scan mode;
The nth stage is
a pull-down transistor for applying a turn-off voltage to the output terminal in response to the voltage of the QB node;
an inverter for maintaining voltages of the Q node and the QB node at opposite voltage levels; and
Further comprising a QB node control unit for applying a turn-on voltage to the QB node at the output timing of the dummy gate pulse,
The QB node control unit
a forward X node charging unit including a gate electrode to which a high potential voltage is applied in the forward scan mode, a drain electrode receiving a clock signal synchronized with the dummy gate pulse, and a source electrode connected to the X node; and
and a QB node charging unit comprising a gate electrode connected to the X node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the QB node. The method of claim 1,
The nth stage is
In the forward scan mode, the n-th gate pulse is output last in one frame,
A shift register of a display device that outputs the n-th gate pulse first in one frame in the reverse scan mode. 3. The method of claim 2,
The first to nth stages output first to nth gate pulses, respectively,
A shift register of a display device in which an (n-1)th gate pulse, the nth gate pulse, and the dummy gate pulse are output at the same time interval. delete delete The method of claim 1,
The inverter is
a QB node discharge unit configured to apply a turn-off voltage to the QB node in response to the Q node voltage; and
and a Q node discharge unit configured to apply a turn-off voltage to the Q node in response to the QB node voltage. The method of claim 1,
The first transistor is a shift register of the display device for applying a turn-off voltage to the Q node in response to a gate pulse at a later stage in a reverse scan mode. 8. The method of claim 7,
The second transistor is
A shift register of a display device for applying a turn-on voltage to the Q node in response to a second gate pulse in the reverse scan mode. a display panel on which gate lines and data lines connected to pixels are disposed; and
The first to n-th stages are configured to sequentially output gate pulses applied to the gate lines, and the output order of the gate pulses includes a shift register selected from one of two directions;
The n-th stage outputting the n-th gate pulse is
a pull-up transistor that charges the output stage in response to the voltage at the Q node;
a first transistor for applying a turn-on voltage to the Q node in response to a previous gate pulse in a forward scan mode;
a second transistor for applying a turn-on voltage to the Q node in response to a start pulse in a reverse scan mode;
a forward reset transistor for applying a turn-off voltage to the Q node in response to a dummy gate pulse applied after outputting the n-th gate pulse in the forward scan mode;
a pull-down transistor for applying a turn-off voltage to the output terminal in response to the voltage of the QB node;
an inverter for maintaining voltages of the Q node and the QB node at opposite voltage levels; and
Further comprising a QB node control unit for applying a turn-on voltage to the QB node at the output timing of the dummy gate pulse,
The QB node control unit
a forward X node charging unit including a gate electrode to which a high potential voltage is applied in the forward scan mode, a drain electrode receiving a clock signal synchronized with the dummy gate pulse, and a source electrode connected to the X node; and
and a QB node charging unit including a gate electrode connected to the X node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the QB node.

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