KR20200069825A - Emitting Signal Generator and Light Emitting Display Device including the Emitting Signal Generator - Google Patents

Abstract

The present invention provides a light emitting signal generation circuit unit. The light emitting signal generation circuit unit comprises: a first signal output circuit unit outputting a light emitting signal of a first voltage in correspondence to a potential of a QB node; a second signal output circuit unit outputting a light emitting signal of a second voltage in correspondence to a potential of a Q node; a node control circuit unit operated based on a start signal, a first clock signal, and a second clock signal and having a Q′ node for controlling the QB node and a Q2 node for controlling the Q node; and a node compensation circuit unit controlling a potential between the Q node and the Q2 node and controlling a potential of the Q′ node based on a third voltage different from at least one of a first voltage and a second voltage. Therefore, the driving reliability may be improved.

Description

Light emitting signal generation circuit unit and light emitting display device including the same {Emitting Signal Generator and Light Emitting Display Device including the Emitting Signal Generator}

The present invention relates to a light emitting signal generating circuit unit and a light emitting display device including the same.

2. Description of the Related Art With the development of information technology, the market for a display device that is a connection medium between a user and information is growing. Accordingly, the use of display devices such as a light emitting display (LED), a quantum dot display (Quantum Dot Display; QDD), a liquid crystal display (Liquid Crystal Display: LCD) is increasing.

The above-described display devices include a display panel including sub-pixels, a driving unit outputting a driving signal driving the display panel, and a power supply unit generating power to be supplied to the display panel or driving unit.

In the above display devices, when a driving signal such as a scan signal and a data signal is supplied to sub-pixels formed on the display panel, the selected sub-pixel transmits light or emits light directly to display an image. .

On the other hand, among the display devices described above, the light emitting display device has many advantages such as fast response speed, high luminance, wide electrical and optical characteristics with a wide viewing angle, and mechanical characteristics that can be implemented in a flexible form. However, the improvement of the light emitting display device in terms of the configuration and driving method of the display panel remains, and thus continuous research is needed.

The present invention for solving the above-described problems of the background art reduces the bias stress applied to a specific transistor during operation of the signal generating device, improves the life of the shift register, increases driving reliability, and prevents abnormal operation of the shift register. It is to prevent and improve the phenomenon of flashing on the display panel.

As the above-mentioned problem solving means, the present invention provides a first signal output circuit unit for outputting a first voltage emission signal in response to the potential of the QB node, and a second signal for outputting a second voltage emission signal in response to the potential of the Q node. A node control circuit having an output circuit, a Q'node that operates based on a start signal, a first clock signal, and a second clock signal and controls a QB node and a Q2 node that controls a Q node, and a first voltage and a second voltage It provides a light-emitting signal generation circuit unit including a node compensation circuit for controlling the potential between the Q node and the Q2 node based on at least one of the third voltage and the Q'node.

The node compensation circuit unit may maintain a turn-on state based on the third voltage.

The third voltage may maintain a low voltage at the same time that the power of the device is turned on.

When the power of the device is turned on, the second voltage may temporarily have the same level as the first voltage and then drop to the low voltage level equal to the third voltage.

The node control circuit unit includes a first transistor having a gate electrode connected to a second clock signal line transmitting a second clock signal, a first electrode connected to a start signal line transmitting a start signal, and a second electrode connected to a Q2 node, A gate electrode is connected to a first clock signal line transmitting a first clock signal, a second transistor connected to a second electrode of the first transistor and a first electrode to a Q2 node, and a first electrode to a second electrode of the second transistor. The first transistor is connected to the third voltage line to which the second electrode is connected to the first voltage line that transmits the first voltage, and the second electrode to which the gate electrode is connected to the second clock signal line and which transmits the second voltage. A fourth transistor connected to the gate electrode of the third transistor, a fifth transistor connected to the Q2 node, a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the first voltage line. , A gate electrode connected to the Q'node and a first electrode connected to the first clock signal line, a gate electrode connected to the first clock signal line, and a first electrode connected to the second electrode of the eighth transistor The first transistor may include a ninth transistor having a second electrode connected to the QB node and a first electrode of the fifth transistor, and a tenth transistor having a gate electrode connected to the Q2 node and a first electrode connected to the second clock signal line.

The first signal output circuit part includes a seventh transistor having a gate electrode connected to a QB node, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to a first voltage line transmitting a first voltage. The second signal output circuit part includes a sixth transistor having a gate electrode connected to the Q node, a first electrode connected to a second voltage line transmitting a second voltage, and a second electrode connected to an output terminal outputting a light emission signal. can do.

The node control circuit part has a first capacitor connected to the Q node and the other end connected to the first clock signal line, a second capacitor connected to the QB node and the other end connected to the first voltage line, and a Q'node. A third capacitor connected to the other end may be included between the second electrode of the eighth transistor and the first electrode of the ninth transistor.

The node compensation circuit unit includes a first compensation transistor having a gate electrode connected to a third voltage line transmitting a third voltage, a first electrode connected to a Q2 node, and a second electrode connected to a Q node, and a gate electrode connected to a third voltage line This may include a second compensation transistor in which the first electrode is connected to the second electrode of the fourth transistor and the second electrode of the fourth transistor, and the second electrode is connected to the Q'node.

In another aspect, the present invention provides a light emitting display device including a display panel for displaying an image, a scan signal generation circuit unit for supplying a scan signal to the display panel, and a light emission signal generation circuit unit for supplying a light emission signal to the display panel. The light emission signal generation circuit unit is a first signal output circuit unit for outputting a light emission signal of a first voltage corresponding to the potential of the QB node, a second signal output circuit unit for outputting a light emission signal of a second voltage corresponding to the potential of the Q node, start A node control circuit unit having a Q'node that controls the QB node and a Q2 node that controls the QB node and operates based on the signal, the first clock signal, and the second clock signal, and at least one of the first voltage and the second voltage. A node compensation circuit unit may control a potential between the Q node and the Q2 node based on the other third voltage and control the potential of the Q'node.

The node compensation circuit unit may maintain a turn-on state based on the third voltage.

The third voltage may maintain a low voltage at the same time that the power of the device is turned on.

When the power of the device is turned on, the second voltage may temporarily have the same level as the first voltage and then drop to the low voltage level equal to the third voltage.

The second voltage may have a low voltage level after a start signal for starting an operation of the scan signal generation circuit unit and the light emission signal generation circuit unit is generated.

The third voltage can maintain a low voltage even after the screen of the display panel is turned on.

The node control circuit unit includes a first transistor having a gate electrode connected to a second clock signal line transmitting a second clock signal, a first electrode connected to a start signal line transmitting a start signal, and a second electrode connected to a Q2 node, A gate electrode is connected to a first clock signal line transmitting a first clock signal, a second transistor connected to a second electrode of the first transistor and a first electrode to a Q2 node, and a first electrode to a second electrode of the second transistor. The first transistor is connected to the third voltage line to which the second electrode is connected to the first voltage line that transmits the first voltage, and the second electrode to which the gate electrode is connected to the second clock signal line and which transmits the second voltage. A fourth transistor connected to the gate electrode of the third transistor, a fifth transistor connected to the Q2 node, a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the first voltage line. , A gate electrode connected to the Q'node and a first electrode connected to the first clock signal line, a gate electrode connected to the first clock signal line, and a first electrode connected to the second electrode of the eighth transistor The first transistor may include a ninth transistor having a second electrode connected to the QB node and a first electrode of the fifth transistor, and a tenth transistor having a gate electrode connected to the Q2 node and a first electrode connected to the second clock signal line.

The first signal output circuit part includes a seventh transistor having a gate electrode connected to a QB node, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to a first voltage line transmitting a first voltage. The second signal output circuit part includes a sixth transistor having a gate electrode connected to the Q node, a first electrode connected to a second voltage line transmitting a second voltage, and a second electrode connected to an output terminal outputting a light emission signal. can do.

The node compensation circuit unit includes a first compensation transistor having a gate electrode connected to a third voltage line transmitting a third voltage, a first electrode connected to a Q2 node, and a second electrode connected to a Q node, and a gate electrode connected to a third voltage line This may include a second compensation transistor in which the first electrode is connected to the second electrode of the fourth transistor and the second electrode of the fourth transistor, and the second electrode is connected to the Q'node.

The light emitting signal generation circuit unit may include a reset transistor having a gate electrode connected to a reset signal line, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to a first voltage line.

The present invention has an effect of reducing the bias stress applied to a specific transistor during operation of the signal generating device and improving the life of the shift register and driving reliability. In addition, the present invention has an effect of preventing an abnormal operation of the shift register by controlling not to electrically float a specific node during the initial operation of the signal generating device. In addition, the present invention has an effect that can prevent and improve the phenomenon of the appearance of flashing on the display panel by preventing abnormal operation of the shift register during the initial operation of the signal generator.

1 is a block diagram schematically showing an organic light emitting display device according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a sub-pixel shown in FIG. 1.
3 is an equivalent circuit diagram showing a sub-pixel including a compensation circuit according to an embodiment of the present invention.
4 and 5 are exemplary diagrams of pixels that may be implemented based on the sub-pixel of FIG. 3.
6 is a view showing an arrangement example of a gate-in-panel scan driver according to an embodiment of the present invention.
7 is a first configuration example of a device associated with a gate-in-panel scan driver.
8 is a second configuration example of a device associated with a gate-in-panel scan driver.
9 is a first configuration example of a shift register.
10 is a second configuration example of a shift register.
11 is a detailed block diagram of light emitting signal generation circuit units according to an embodiment of the present invention.
12 is a first exemplary view showing a detailed circuit configuration of a light emitting signal generation circuit unit of the first stage shown in FIG. 11.
13 is a second exemplary view showing a detailed circuit configuration of the light emitting signal generation circuit unit of the first stage shown in FIG. 11.
14 and 15 are example waveforms for explaining the operation of the light emitting signal generation circuit unit of the first stage shown in FIGS. 12 and 13.
16 is an exemplary view showing a detailed circuit configuration of a light emitting signal generation circuit portion of a first stage according to an experimental example.
FIG. 17 is a diagram showing input/output waveforms and internal voltages of the experimental example shown in FIG. 16.
18 is a view for comparing and explaining the output waveform of the light emitting signal generation circuit unit of the first stage according to the experimental example and the embodiment.

Hereinafter, with reference to the accompanying drawings, specific details for the practice of the present invention will be described.

The display device according to the present invention may be implemented as a television, a video player, a personal computer (PC), a home theater, an automobile electric device, a smart phone, and the like, but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (Quantum Dot Display Apparatus; QDD), a liquid crystal display device (Liquid Crystal Display Apparatus: LCD), or the like. Hereinafter, for convenience of description, a light emitting display device that expresses an image by directly emitting light will be taken as an example. The light emitting display device may be implemented based on an inorganic light emitting diode or may be implemented based on an organic light emitting diode. Hereinafter, for convenience of description, an example based on an organic light emitting diode will be described.

In addition, although the sub-pixel described below includes an n-type thin film transistor as an example, it may be implemented in a form in which a p-type thin film transistor or an n-type and p-type are present together. The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the thin film transistor, carriers begin to flow from the source. The drain is an electrode through which the carrier is exposed in the thin film transistor. That is, the carrier flow in the thin film transistor flows from the source to the drain.

In the case of the n-type thin film transistor, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain because the carrier is an electron. In the n-type thin film transistor, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In contrast, in the case of a p-type thin film transistor, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain because the carrier is a hole. In the p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. However, the source and drain of the thin film transistor can be changed according to the applied voltage. Reflecting this, in the following description, one of the source and the drain is described as the first electrode, and the other of the source and the drain is described as the second electrode.

1 is a block diagram schematically showing an organic light emitting display device according to an exemplary embodiment of the present invention, and FIG. 2 is a schematic diagram showing a sub-pixel shown in FIG. 1.

1 and 2, the organic light emitting display device according to an exemplary embodiment of the present invention includes an image supply unit 110, a timing control unit 120, a scan driving unit 130, a data driving unit 140, and a display panel. 150 and the power supply unit 180 are included.

The image supply unit 110 (or the host system) outputs various driving signals in addition to the image data signals supplied from the outside or the image data signals stored in the internal memory. The image supply unit 110 may supply a data signal and various driving signals to the timing control unit 120.

The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130, a data timing control signal DDC for controlling the operation timing of the data driver 140, and various synchronization signals ( It outputs the vertical sync signal Vsync and the horizontal sync signal Hsync).

The timing controller 120 supplies the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 is formed in the form of an integrated circuit (IC) and may be mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 outputs a scan signal (or scan voltage) in response to a gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 supplies scan signals to sub-pixels included in the display panel 150 through scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be directly formed on the display panel 150 by a gate in panel method, but is not limited thereto.

The data driving unit 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing control unit 120 and the digital data signal based on the gamma reference voltage. Convert to voltage and output.

The data driver 140 supplies data voltages to sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in an IC form and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates and outputs a high-potential first panel power EVDD and a low-potential second panel power EVSS based on an external input voltage supplied from the outside. The power supply unit 180 may include the first panel power and the second panel power (EVDD, EVSS), as well as voltages required for driving the scan driver 130 (eg, scan high voltage, scan low voltage) or data driver 140. It is possible to generate and output voltages required for driving (drain voltage, half drain voltage).

The display panel 150 includes a scan signal output from a driver including a scan driver 130 and a data driver 140, a drive signal including a data voltage, and first and second panel power output from the power supply unit 180. Displays images in response to the panel power sources (EVDD, EVSS). The sub-pixels of the display panel 150 directly emit light.

The display panel 150 may be manufactured based on a substrate having rigidity or ductility such as glass, silicon, and polyimide. In addition, sub-pixels emitting light may be formed of pixels including red, green, and blue, or pixels including red, green, blue, and white.

For example, one sub-pixel SP includes a switching transistor SW and a pixel circuit PC including a driving transistor, a storage capacitor, and an organic light emitting diode. The sub-pixel SP used in the organic light emitting display device emits light directly, so the circuit configuration is complicated. In addition, there are various organic light emitting diodes that emit light, as well as compensation circuits that compensate for deterioration of driving transistors that supply driving current to the organic light emitting diode. Therefore, it is referred to that the pixel circuit PC included in the sub-pixel SP is shown in block form.

Meanwhile, in the above description, the timing control unit 120, the scan driving unit 130, and the data driving unit 140 are described as if they were individual components. However, one or more of the timing control unit 120, the scan driving unit 130, and the data driving unit 140 may be integrated in one IC according to the implementation method of the light emitting display device.

3 is an equivalent circuit diagram illustrating a sub-pixel including a compensation circuit according to an embodiment of the present invention, and FIGS. 4 and 5 are exemplary diagrams of a pixel that can be implemented based on the sub-pixel of FIG. 3.

As illustrated in FIG. 3, a sub-pixel including a compensation circuit according to an embodiment of the present invention includes a switching transistor SW, a sensing transistor ST, a driving transistor DT, a capacitor CST, and an organic light emitting diode. (OLED).

In the switching transistor SW, a gate electrode is connected to the 1A scan line GL1a, a first electrode is connected to the first data line DL1, and a second electrode is connected to the gate electrode of the driving transistor DT. In the driving transistor DT, a gate electrode is connected to the capacitor CST, a first electrode is connected to the first power line EVDD, and a second electrode is connected to the anode electrode of the organic light emitting diode OLED.

The capacitor CST has a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light emitting diode OLED. In the organic light emitting diode OLED, the anode electrode is connected to the second electrode of the driving transistor DT, and the cathode electrode is connected to the second power line EVSS. In the sensing transistor ST, a gate electrode is connected to the first B scan line GL1b, a first electrode is connected to the sensing line VREF, and a second electrode is connected to the anode electrode of the organic light emitting diode (OLED), which is a sensing node. .

The sensing transistor ST is a compensation circuit added to compensate for deterioration or threshold voltage of the driving transistor DT and the organic light emitting diode OLED. The sensing transistor ST acquires a sensing value through a sensing node defined between the driving transistor DT and the organic light emitting diode OLED. The sensing value obtained from the sensing transistor ST is transmitted to an external compensation circuit provided outside the sub-pixel through the sensing line VREF.

The first A scan line GL1a connected to the gate electrode of the switching transistor SW and the first B scan line GL1b connected to the gate electrode of the sensing transistor ST take a separate structure as shown or have a common connection structure. Can take The gate electrode common connection structure can reduce the number of scan lines, and as a result, it is possible to prevent the reduction of the aperture ratio due to the addition of the compensation circuit.

4 and 5, first to fourth sub-pixels SP1 to SP4 including a compensation circuit according to an embodiment of the present invention may be defined to constitute one pixel. In this case, the first to fourth sub-pixels SP1 to SP4 may be arranged in order of emitting red, green, blue, and white, respectively, but are not limited thereto.

As in the first example of FIG. 4, the first to fourth sub pixels SP1 to SP4 including the compensation circuit are connected to share one sensing line VREF, and the first to fourth data lines DL1 ~ DL4) may have a structure connected to each.

As in the second example of FIG. 5, the first to fourth sub-pixels SP1 to SP4 including the compensation circuit are connected to share one sensing line VREF, and two sub-pixels are connected to one data line. It may have a shared connected structure. For example, the first and second sub-pixels SP1 and SP2 may share the first data line DL1 and the third and fourth sub-pixels SP3 and SP4 may share the second data line DL2. .

However, FIGS. 4 and 5 show only two examples, and the present invention is also applicable to a display panel having sub-pixels of other structures not illustrated and described above. In addition, the present invention is also applicable to a structure having a compensation circuit in a sub-pixel or a structure without a compensation circuit in a sub-pixel.

6 is a view showing an arrangement example of a gate-in-panel type scan driver according to an embodiment of the present invention, FIG. 7 is an exemplary view of a first configuration of a device associated with a gate-in-panel type scan driver, and FIG. 8 is a gate-in panel A second configuration example of the apparatus associated with the method scan driver, FIG. 9 is a first configuration example of the shift register, and FIG. 10 is a second configuration example of the shift register.

As shown in FIG. 6, the gate-in-panel scan drivers 130a and 130b are disposed in the non-display area NA of the display panel 150. The scan driving units 130a and 130b may be disposed on the left and right non-display areas NA of the display panel 150 as shown in FIG. 6(a). Also, the scan driving units 130a and 130b may be arranged in the upper and lower non-display areas NA of the display panel 150, as shown in FIG. 6(b).

Although the scan driving units 130a and 130b are illustrated and described as an example of being arranged in pairs in the non-display area NA located on the left and right or top and bottom sides of the display area AA, only one is disposed on the left, right, top, or bottom sides. It may be, but is not limited thereto.

As shown in FIG. 7, the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter unit 135 generates and outputs a plurality of clock signals Gclk and Eclk and start signals Gvst and Evst based on the signals output from the timing controller 120. A plurality of clock signals (Gclk, Eclk) may be generated and output in the form of K phases (K is an integer of 2 or more) having different phases, such as 2 phase, 4 phase, and 8 phase.

The shift register 131 operates based on signals Gclk, Eclk, Gvst, Evst, etc. output from the level shifter unit 135, and scan signals (Scan) capable of turning on or off the transistor formed on the display panel [1] to Scan[m]) and emission signals (Em[1] to Em[m]) are output. The shift register 131 is formed in a thin film form on the display panel by a gate-in-panel method. Accordingly, the portion formed on the display panel in the scan driver 130 may be the shift register 131 (ie, 130a and 130b correspond to 131 in FIG. 6 ).

Unlike the shift register 131, the level shifter 135 is formed in the form of an IC. The level shifter 135 may be configured in a separate IC form as shown in FIG. 7, or may be included inside the power supply 180 or other devices as shown in FIG. 8.

9 and 10, the shift register 131 is composed of a plurality of stages (STG1 ~ STGm). The plurality of stages STG1 to STGm have a structure in which they are connected to each other and receive at least one front end or rear end output signal as an input signal.

9, the stages STG1 to STGm of the shift register 131 include scan signal generation circuits SCAN[1] to SCAN[m] and light emission signal generation circuits EM[ 1] to EM[m]), respectively. For example, the first stage STG1 generates a first scan signal generation circuit unit SCAN[1] for outputting a first scan signal Scan[1] and a light emission signal for outputting a light emission signal Em[1]. It has a circuit part EM[1].

The scan signal generation circuits SCAN[1] to SCAN[m] output scan signals Scan[1] to Scan[m] through scan lines of the display panel. The light emission signal generation circuit units EM[1] to EM[m] output light emission signals Em[1] to Em[m] through the light emission signal lines of the display panel.

As shown in the second example shown in FIG. 10, the stages STG1 to STGm of the shift register 131 include first scan signal generation circuits SCAN1[1] to SCAN1[m], and second scan signal generation circuitry. SCAN2[1] to SCAN2[m], and light emission signal generation circuits EM[1] to EM[m], respectively. In one example, the first stage STG1 is a first scan signal generating circuit unit SCAN1[1] for outputting the first scan signal Scan1[1], and a second for outputting the second scan signal Scan2[1]. It has a two-scan signal generation circuit section SCAN2[1] and an emission signal generation circuit section EM[1] for outputting the emission signal Em[1].

The first scan signal generation circuit units SCAN1[1] to SCAN1[m] output first scan signals Scan1[1] to Scan1[m] through the first scan lines of the display panel. The second scan signal generation circuit units SCAN2[1] to SCAN2[m] output second scan signals Scan2[1] to Scan2[m] through the second scan lines of the display panel. The light emission signal generation circuit units EM[1] to EM[m] output light emission signals Em[1] to Em[m] through the light emission signal lines of the display panel.

The first scan signals Scan1[1] to Scan1[m] may be used as a signal for driving the A-th transistor (eg, switching transistor, etc.) included in the sub-pixels. The second scan signals Scan2[1] to Scan2[m] may be used as a signal for driving the B-transistor (eg, sensing transistor, etc.) included in the sub-pixels.

The light emission signals Em[1] to Em[m] may be used as signals for driving the C-th transistor (eg, light emission control transistor, etc.) included in the sub-pixels. For example, when the light emission control transistors of the sub-pixels are controlled using the light emission signals Em[1] to Em[m], the light emission time of the organic light emitting diode is varied.

However, the examples of FIGS. 9 and 10 are examples to help understanding the shift register 131, and the present invention is not limited thereto, and may be implemented in a form of outputting more various and more signals.

FIG. 11 is a detailed block diagram of light emitting signal generating circuit parts according to an embodiment of the present invention, and FIG. 12 is a first exemplary view showing a detailed circuit configuration of the light emitting signal generating circuit part of the first stage shown in FIG. 11. 13 is a second exemplary view showing a detailed circuit configuration of the light emitting signal generating circuit part of the first stage shown in FIG. 11, and FIGS. 14 and 15 are light emitting signal generating circuit parts of the first stage shown in FIGS. These are waveform examples for explaining the operation.

As illustrated in FIG. 11, the first stage light emission signal generation circuit units EM[1] to EM[m] according to an embodiment of the present invention include a first clock signal line ECLK1 and a second clock signal line. (ECLK2), the start signal line (EVST), the first voltage line (VEH), the second voltage line (VEL), and the third voltage line (VBV). Therefore, the light emitting signal generation circuit units EM[1] to EM[m] of the first stage are applied through the first clock signal applied through the first clock signal line ECLK1 and the second clock signal line ECLK2. Second clock signal, start signal applied through the start signal line (EVST), first voltage applied through the first voltage line (VEH), second voltage applied through the second voltage line (VEL), second The light emitting signals are output based on the third voltage applied through the three voltage line VBV.

On the other hand, the light emission signal generation circuit unit EM[1] of the first stage is connected to the start signal line EVST, but the light emission of the first stage located at the front end from the light emission signal generation circuit unit EM[2] of the second stage The output signal of the signal generating circuit section EM[1] is used as a start signal. For this reason, the light emitting signal generating circuit part EM[2] of the second stage is connected to the output terminal EMO[1] of the light emitting signal generating circuit part EM[1] of the first stage instead of the start signal line EVST. Will be.

As shown in the first example shown in FIG. 12, the light emitting signal generation circuit unit EM[1] of the first stage includes a first transistor T1 to a tenth transistor T10, and a first to third capacitors CQ and CQB. , CQ'), a first compensation transistor Tb1 and a second compensation transistor Tb2. The sixth and seventh transistors T6 and T7 may be included in the signal output circuit unit. In addition, the first to fifth transistors T1 to T5 and the eighth to tenth transistors T8 to T10 may be included in the node control circuit. In addition, the first and second compensation transistors Tb1 and Tb2 may be included in the node compensation circuit.

For example, the first transistor T1 to the tenth transistor T10, the first compensation transistor Tb1, and the second compensation transistor Tb2 are implemented as p-type thin film transistors. The first transistor T1 to the tenth transistor T10, the first compensation transistor Tb1, and the second compensation transistor Tb2 implemented as a p-type thin film transistor are turned on under a condition that a low voltage is applied and a high voltage is applied. Turn off at the condition.

The first transistor T1 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the start signal line EVST, and a first electrode and a Q2 node (Q2N) of the second transistor T2. Is connected to the second electrode. The first transistor T1 is turned on or off in response to the second clock signal applied through the second clock signal line ECLK2.

The second transistor T2 has a gate electrode connected to the first clock signal line ECLK1, a second electrode of the first transistor T1, and a first electrode connected to the Q2 node Q2N and a third transistor T3. The second electrode is connected to the first electrode. The second transistor T2 is turned on or off in response to the first clock signal applied through the first clock signal line ECLK1.

In the third transistor T3, a gate electrode is connected to the second electrode of the fourth transistor T4 and the first electrode of the second compensation transistor Tb2, and the first electrode is connected to the second electrode of the second transistor T2. The second electrode is connected to the first voltage line VEH. When the fourth transistor T4 is turned on, the third transistor T3 is turned on in response to the second voltage through the second voltage line VEL.

In the fourth transistor T4, a gate electrode is connected to the second clock signal line ECLK2, a first electrode is connected to the second voltage line VEL, and a first electrode and a third transistor of the second compensation transistor Tb2. The second electrode is connected to the gate electrode of (T3). The fourth transistor T4 is turned on or off in response to the second clock signal applied through the second clock signal line ECLK2. The fourth transistor T4 is turned on or off simultaneously with the first transistor T1.

In the fifth transistor T5, a gate electrode is connected to the Q2 node Q2N, and a first electrode is connected to the second electrode of the QB node QBN and the ninth transistor T9, and the first electrode is connected to the first voltage line VEH. Two electrodes are connected. The fifth transistor T5 is turned on or off in response to the potential of the Q2 node Q2N.

In the sixth transistor T6, a gate electrode is connected to one end of the Q node Q and the first capacitor CQ, the first electrode is connected to the second voltage line VEL, and the light emitting signal generation circuit unit of the first stage ( The second electrode is connected to the output terminal EMO[1] of EM[1]). The sixth transistor T6 is turned on or off in response to the potential of the Q node Q. The sixth transistor T6 may be defined as a second signal output circuit unit.

In the seventh transistor T7, the gate electrode is connected to the QB node QBN, and the first electrode is connected to the output terminal EMO[1] of the light emitting signal generation circuit unit EM[1] of the first stage and the first electrode The second electrode is connected to the voltage line VEH. The seventh transistor T7 is turned on or off in response to the potential of the QB node QBN. The seventh transistor T7 may be defined as a first signal output circuit unit.

In the eighth transistor T8, a gate electrode is connected to the second electrode and the Q'node Q'N of the second compensation transistor Tb2, the first electrode is connected to the first clock signal line ECLK1, and the ninth The second electrode is connected to the first electrode of the transistor T9. The eighth transistor T8 is turned on or off in response to the potential of the Q'node Q'N.

In the ninth transistor T9, the gate electrode is connected to the first clock signal line ECLK1, the first electrode is connected to the second electrode of the eighth transistor T8, and the first electrode and QB of the fifth transistor T5 are connected. The second electrode is connected to the node QBN. The ninth transistor T9 is turned on or off in response to the first clock signal applied through the first clock signal line ECLK1. The ninth transistor T9 is turned on or off simultaneously with the second transistor T2.

In the tenth transistor T10, the gate electrode is connected to the Q2 node Q2N, the first electrode is connected to the second clock signal line ECLK2, and the second electrode is connected to the first electrode of the second compensation transistor Tb2. do. The tenth transistor T10 is turned on or off in response to the potential of the Q2 node Q2N. The tenth transistor T10 is turned on or off simultaneously with the fifth transistor T5. On the other hand, the tenth transistor (T10), as can be seen from the figure shown separately, the form of the 10a transistor (T10a) and the 10b transistor (T10b) in which two gate electrodes are commonly connected to the second clock signal line (ECLK2). It may be implemented as.

The first capacitor CQ has one end connected to the Q node QN and the other end connected to the first clock signal line ECLK1. The second capacitor CQB has one end connected to the QB node QBN and the other end connected to the first voltage line VEH. One end of the third capacitor CQ' is connected to the Q'node Q'N, and the other end is connected between the second electrode of the eighth transistor T8 and the first electrode of the ninth transistor T9.

The first compensation transistor Tb1 has a gate electrode connected to a third voltage line VBV, a second electrode of the first transistor T1, a first electrode of the second transistor T2, and a tenth transistor T10. The first electrode is connected to the gate electrode and the Q2 node Q2N, and the second electrode is connected to the Q node QN. The first compensation transistor Tb1 may be defined as a first node compensation circuit unit.

In the second compensation transistor Tb2, the gate electrode is connected to the third voltage line VBV, the second electrode of the fourth transistor T4 and the first electrode of the second electrode of the tenth transistor T10 are connected and Q The second electrode is connected to the'node (Q'N) and the gate electrode of the eighth transistor (T8). The second compensation transistor Tb2 is simultaneously turned on or off by the third voltage applied through the third voltage line VBV together with the first compensation transistor Tb1. The second compensation transistor Tb2 may be defined as a second node compensation circuit unit.

As shown in the second example illustrated in FIG. 13, the light emitting signal generation circuit unit EM[1] of the first stage includes first transistors T1 to 10 transistors T10, and first to third capacitors CQ and CQB. , CQ'), a first compensation transistor Tb1, a second compensation transistor Tb2, and a reset transistor TR.

In the reset transistor TR, a gate electrode is connected to the reset signal line EQRST, a first electrode is connected to the output terminal EMO[1] of the light emitting signal generation circuit unit EM[1] of the first stage, and the first electrode is connected to the reset signal line EQRST. The second electrode is connected to the voltage line VEH. The reset transistor TR is turned on or off in response to the reset signal applied through the reset signal line EQRST. When the reset transistor TR is turned on, the output terminal EMO[1] of the light emission signal generation circuit unit EM[1] of the first stage is based on the first voltage applied through the first voltage line VEH. A high voltage light emission signal is output.

12 to 15, the start signal Evst applied through the start signal line EVST may have a form of generating a high voltage for 3 horizontal hours 3H. The second clock signal Eclk2 applied through the second clock signal line ECLK2 may have a form in which the low voltage and the high voltage alternately occur at a period of 1 horizontal time (1H) in synchronization with the high voltage timing of the start signal. have.

The first clock signal Eclk1 applied through the first clock signal line ECLK1 may have a form in which the high voltage and the low voltage alternately occur at a period of 1 horizontal time (1H) in synchronization with the high voltage timing of the start signal. have. That is, the second clock signal Eclk2 and the first clock signal Eclk1 may generate high voltage and low voltage in reverse phase.

The elements included in the light emission signal generation circuit unit EM[1] of the first stage include a start signal Evst, a first clock signal Eclk1, a second clock signal Eclk2, a first voltage Veh, and a second voltage. It operates in response to the voltage Vel and the third voltage Vbv.

By operation of the elements included in the light emission signal generation circuit unit EM[1] of the first stage, the Q node Q has a period of being charged with a high voltage, and the Q'node Q'and QB node QB ) Has a period of discharge with a low voltage. At this time, the QB node QB can maintain the low voltage of the reversed phase delayed by 1 horizontal time (1H) compared to the start signal Evst for 3 horizontal times (3H).

The sixth transistor T7 is turned on or off in response to the potential of the Q node Q, and the seventh transistor T7 is turned on or off in response to the potential of the QB node QB. When the potential of the Q node Q maintains a high voltage, the potential of the QB node QB can maintain a low voltage.

Since the seventh transistor T7 is turned on corresponding to the low voltage of the QB node QB, the first voltage Veh applied through the first voltage line VEH is the light emission signal generating circuit part EM[ of the first stage. 1]) through the output terminal (EMO[1]). As a result, the output terminal EMO[1] of the light emission signal generation circuit unit EM[1] of the first stage is at least three horizontal based on the first voltage Veh applied through the first voltage line VEH. During the time 3H, the high voltage light emission signal Em[1] is output, and then it is converted to the low voltage light emission signal Em[1].

Elements included in the light emitting signal generation circuit unit EM[1] of the first stage may receive bias stress as they operate as described above. For example, the second transistor (T2), the third transistor (T3), the fourth transistor (T4) and the seventh transistor (T7) are HJTS (High Junction Temperature) due to the high voltage transfer operation through the source-drain electrode. Stress). In addition, the first transistor T1 may be included in a device subjected to PBTS (Positive Bias Temperature Stress) due to application of a high voltage through the gate electrode. In addition, the third transistor (T3), the fifth transistor (T5), the eighth transistor (T8), and the ninth transistor (T9) are applied to a device that receives NBTS (Negative Bias Temperature Stress) due to the application of a low voltage through the gate electrode. Can be included.

The first compensation transistor Tb1 and the second compensation transistor Tb2 are devices added between nodes to reduce bias stress of devices included in the light emitting signal generation circuit unit EM[1] of the first stage. The first compensation transistor Tb1 and the second compensation transistor Tb2 may reduce bias stress received by the aforementioned devices through node control at both ends (voltage control at both ends).

The first compensation transistor Tb1 and the second compensation transistor Tb2 may control a floating node during operation of the light emitting signal generation circuit unit EM[1] of the first stage. Nodes electrically floating in the light emission signal generation circuit unit EM[1] of the first stage may include, for example, Q node QN, Q'node Q'N, and QB node QBN. The first compensation transistor Tb1 and the second compensation transistor Tb2 may control the potential of the Q'node Q'N while simultaneously controlling between the Q node QN and the Q2 node Q2N. When the potential of the Q'node Q'N is controlled, the potential of the QB node QBN is also controlled.

The first compensation transistor Tb1 and the second compensation transistor Tb2 reduce bias stress of elements included in the light emission signal generation circuit unit EM[1] of the first stage and prevent abnormal operation due to an electrically floating node. In order to do so, it is connected to a separate third voltage line VBV that applies the third voltage Vbv. Descriptions related to the operation of the first compensation transistor Tb1 and the second compensation transistor Tb2 are described below.

12, 13 and 15, when the power of the device is turned on, the first voltage Veh applied through the first voltage line VEH is applied through the scan high voltage line. The scan high voltage (Vgh) increases. After the scan high voltage Vgh rises, the scan low voltage Vgl applied through the scan low voltage line drops. The scan high voltage Vgh and scan low voltage Vgl are voltages applied to the scan signal generation circuits (see descriptions of SCAN[1] to SCAN[m] in FIGS. 9 and 10).

After the reset signal Qrst occurs, the first panel power Evdd rises, and then the start signal Vst occurs. When the start signal Vst is generated, the scan driver 130 starts an operation for generating a scan signal and a light emission signal.

After the start signal Vst occurs, the second voltage Vel applied through the second voltage line VEL does not immediately drop to the same level as the third voltage Vbv applied through the third voltage line VBV. Falls. The second voltage Vel falls to the low voltage level later than the scan low voltage Vgl. That is, when the power of the device is turned on (Power On), the second voltage (Vel) temporarily has the same level as the first voltage (Veh) and then falls to the low voltage level such as the third voltage (Vbv).

The third voltage Vbv applied through the third voltage line VBV has the same level as the second voltage Vel applied through the second voltage line VEL. However, the third voltage Vbv applied through the third voltage line VBV is maintained at a low voltage while the power of the device is turned on. The third voltage Vbv applied through the third voltage line VBV continues to maintain a low voltage even after the display panel is turned on.

The first compensation transistor Tb1 and the second compensation transistor Tb2 maintain a continuous turn-on state based on the third voltage Vbv maintained at a low voltage at the same time that the power of the device is turned on.

16 is an exemplary view showing a detailed circuit configuration of a light emitting signal generation circuit part of a first stage according to an experimental example, FIG. 17 is a diagram showing an input/output waveform and an internal voltage of the experimental example shown in FIG. 16, and FIG. 18 is an experimental example A diagram for comparing and explaining the output waveform of the light emitting signal generation circuit portion of the first stage according to the embodiment.

As shown in FIG. 16, the light emitting signal generation circuit unit EM[1] of the first stage according to the experimental example has the same circuit configuration as the embodiment described in FIG. 12 of the present invention. However, the gate electrode is connected to the first compensation transistor Tb1 and the second compensation transistor Tb2 of the experimental example to the second voltage line VEL.

As described with reference to FIG. 15, the second voltage Vel applied through the second voltage line VEL falls to the low voltage level later than the time when the scan driver 130 starts operation. Experimental Example Also, by adding the first compensation transistor Tb1 and the second compensation transistor Tb2, bias stress of elements included in the light emission signal generation circuit unit EM[1] of the first stage can be reduced.

However, since the first compensation transistor Tb1 and the second compensation transistor Tb2 are controlled based on the second voltage Vel, a specific node is electrically floating during an initial operation period after the device is powered on. You cannot control the status. For example, during an initial operation period in which the device is powered on, at least one of the Q node QN, the Q'node Q'N and the QB node QBN is placed in an electrically floating state. That is, the light emitting signal generation circuit unit EM[1] of the first stage drives the voltage of the node in an unknown state (Un-known).

For this reason, as in the experimental example of FIG. 17, when controlling the first compensation transistor Tb1 and the second compensation transistor Tb2 based on the second voltage Vel, the internal voltage Q'during the initial operation period Is shaken in an abnormal state. As can be seen through "Initial Low Fluctuation" and "Waveform NG" in FIG. 17, when the circuit is configured as in the experimental example, it can be seen how the output waveform can be distorted.

The light emitting signal generation circuit unit EM[1] of the first stage according to the experimental example shown in FIG. 16 is displayed because the light emission signal Emo is abnormally output during the initial operation period, as shown in FIG. 18(a). Screen flickering on the panel Pnl may occur.

On the other hand, the light emitting signal generation circuit unit EM[1] of the first stage according to the embodiment shown in FIGS. 12 and 13 shows that the light emission signal Emo is generated during the initial operation period as shown in FIG. 18(b). As it is output normally, screen flicker on the display panel (Pnl) does not occur. The reason is that the third voltage Vbv applied through the third voltage line VBV is maintained at a low voltage at the same time that the power of the device is turned on and the first compensation transistor Tb1 and the second compensation transistor are maintained. This is because the turn-on state of (Tb2) is stably maintained.

As described above, the present invention has an effect of reducing bias stress applied to a specific transistor during operation of the signal generating device, improving the life of the shift register and increasing driving reliability. In addition, the present invention has an effect of preventing an abnormal operation of the shift register by controlling not to electrically float a specific node during the initial operation of the signal generating device. In addition, the present invention has an effect that can prevent and improve the phenomenon of the appearance of flashing on the display panel by preventing abnormal operation of the shift register during the initial operation of the signal generator.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the technical configuration of the present invention described above is in other specific forms without changing the technical spirit or essential features of the present invention by those skilled in the art to which the present invention pertains. It will be understood that it can be practiced. Therefore, the above-described embodiments are to be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

130: scan driver 150: display panel
131: shift register 135: level shifter
T1: 1st transistor T10: 10th transistor
Tb1: first compensation transistor Tb2: second compensation transistor
SCAN[1] ~ SCAN[m]: scan signal generation circuits
EM[1] ~ EM[m]: Light emitting signal generation circuit parts

Claims (18)

A first signal output circuit unit for outputting a light emission signal of a first voltage corresponding to the potential of the QB node;
A second signal output circuit unit for outputting a light emission signal of a second voltage corresponding to the potential of the Q node;
A node control circuit unit having a Q'node that controls the QB node and a Q2 node that controls the Q node and operates based on a start signal, a first clock signal, and a second clock signal; And
A light emitting signal including a node compensation circuit for controlling a potential between the Q node and the Q2 node and controlling the potential of the Q'node based on a third voltage different from at least one of the first voltage and the second voltage Generation circuit. According to claim 1,
The node compensation circuit unit
A light emitting signal generation circuit unit that maintains a turn-on state based on the third voltage. According to claim 1,
The third voltage
A light emitting signal generation circuit unit that maintains a low voltage at the same time that the power of the device is turned on. According to claim 1,
The second voltage
When the power of the device is turned on, the light emitting signal generation circuit unit temporarily has a level equal to the first voltage and then falls to a low voltage level equal to the third voltage. According to claim 1,
The node control circuit part
A first transistor having a gate electrode connected to a second clock signal line transmitting the second clock signal, a first electrode connected to a start signal line transferring the start signal, and a second electrode connected to the Q2 node;
A second transistor having a gate electrode connected to a first clock signal line transmitting the first clock signal and a second electrode of the first transistor and a first electrode connected to the Q2 node;
A third transistor having a first electrode connected to a second electrode of the second transistor and a second electrode connected to a first voltage line transmitting the first voltage;
A fourth transistor having a gate electrode connected to the second clock signal line, a first electrode connected to a second voltage line transmitting the second voltage, and a second electrode connected to a gate electrode of the third transistor;
A fifth transistor having a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the first voltage line;
An eighth transistor having a gate electrode connected to the Q'node and a first electrode connected to the first clock signal line;
A ninth transistor having a gate electrode connected to the first clock signal line, a first electrode connected to a second electrode of the eighth transistor, a first electrode of the fifth transistor, and a second electrode connected to the QB node;
A light emitting signal generation circuit unit including a tenth transistor having a gate electrode connected to the Q2 node and a first electrode connected to the second clock signal line. The method of claim 5,
The first signal output circuit unit
A seventh transistor having a gate electrode connected to the QB node, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to a first voltage line transmitting the first voltage,
The second signal output circuit unit
A light emission signal including a sixth transistor having a gate electrode connected to the Q node and a first electrode connected to a second voltage line transmitting the second voltage and a second electrode connected to an output terminal outputting the light emission signal is generated. Circuit part. The method of claim 5,
The node control circuit part
A first capacitor having one end connected to the Q node and the other end connected to the first clock signal line;
A second capacitor having one end connected to the QB node and the other end connected to the first voltage line,
And a third capacitor having one end connected to the Q'node and a second terminal connected between the second electrode of the eighth transistor and the first electrode of the ninth transistor. The method of claim 5,
The node compensation circuit unit
A first compensation transistor having a gate electrode connected to a third voltage line transferring the third voltage, a first electrode connected to the Q2 node, and a second electrode connected to the Q node;
A second compensation transistor having a gate electrode connected to the third voltage line, a first electrode connected to a second electrode of the fourth transistor and a second electrode of the ten transistor, and a second electrode connected to the Q'node. Light emitting signal generation circuit portion comprising. A display panel for displaying an image;
A scan signal generation circuit unit supplying a scan signal to the display panel; And
It includes a light emitting signal generating circuit for supplying a light emitting signal to the display panel,
The light emission signal generation circuit unit
A first signal output circuit section for outputting a first voltage emission signal corresponding to the potential of the QB node, and a second signal output circuit section for outputting a second voltage emission signal corresponding to the potential of the Q node, start signal, and first clock A node control circuit unit having a Q'node that controls the QB node and a Q2 node that controls the Q node, which is operated based on the signal and the second clock signal, and is different from at least one of the first voltage and the second voltage. And a node compensation circuit unit controlling a potential between the Q node and the Q2 node and controlling the potential of the Q'node based on 3 voltages. The method of claim 9,
The node compensation circuit unit
A light emitting display device that maintains a turn-on state based on the third voltage. The method of claim 9,
The third voltage
A light emitting display device that maintains a low voltage at the same time that the power of the device is turned on. The method of claim 9,
The second voltage
When the power of the device is turned on, the light emitting display device having a level equal to the first voltage and then falling to a low voltage level equal to the third voltage. The method of claim 12,
The second voltage
A light emitting display device having the low voltage level after a start signal for starting operation of the scan signal generation circuit unit and the light emission signal generation circuit unit is generated. The method of claim 9,
The third voltage
A light emitting display device that maintains a low voltage even after the screen of the display panel is turned on. The method of claim 9,
The node control circuit part
A first transistor having a gate electrode connected to a second clock signal line transmitting the second clock signal, a first electrode connected to a start signal line transferring the start signal, and a second electrode connected to the Q2 node;
A second transistor having a gate electrode connected to a first clock signal line transmitting the first clock signal and a second electrode of the first transistor and a first electrode connected to the Q2 node;
A third transistor having a first electrode connected to a second electrode of the second transistor and a second electrode connected to a first voltage line transmitting the first voltage;
A fourth transistor having a gate electrode connected to the second clock signal line, a first electrode connected to a second voltage line transmitting the second voltage, and a second electrode connected to a gate electrode of the third transistor;
A fifth transistor having a gate electrode connected to the Q2 node, a first electrode connected to the QB node, and a second electrode connected to the first voltage line;
An eighth transistor having a gate electrode connected to the Q'node and a first electrode connected to the first clock signal line;
A ninth transistor having a gate electrode connected to the first clock signal line, a first electrode connected to a second electrode of the eighth transistor, a first electrode of the fifth transistor, and a second electrode connected to the QB node;
And a tenth transistor having a gate electrode connected to the Q2 node and a first electrode connected to the second clock signal line. The method of claim 15,
The first signal output circuit unit
A seventh transistor having a gate electrode connected to the QB node, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to a first voltage line transmitting the first voltage,
The second signal output circuit unit
A light emitting display device comprising a sixth transistor having a gate electrode connected to the Q node, a first electrode connected to a second voltage line transmitting the second voltage, and a second electrode connected to an output terminal outputting the light emission signal. . The method of claim 15,
The node compensation circuit unit
A first compensation transistor having a gate electrode connected to a third voltage line transferring the third voltage, a first electrode connected to the Q2 node, and a second electrode connected to the Q node;
A second compensation transistor having a gate electrode connected to the third voltage line, a first electrode connected to a second electrode of the fourth transistor and a second electrode of the ten transistor, and a second electrode connected to the Q'node. A light emitting display device comprising. The method of claim 15,
The light emission signal generation circuit unit
A light emitting display device comprising a reset transistor having a gate electrode connected to a reset signal line, a first electrode connected to an output terminal outputting a light emission signal, and a second electrode connected to the first voltage line.

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