KR20040077160A - Method of fabricating driving and switching device for liquid crystal display device with driving circuit - Google Patents

Abstract

PURPOSE: A fabrication method of a driving element and a switching element for a driving circuit integrated LCD device is provided to fabricate a TFT in a top gate-staggered type, to form source electrodes and drain electrodes under gate electrodes, thereby omitting a semiconductor layer contact hole process. CONSTITUTION: An inorganic insulating layer and a metal layer are formed by continuously depositing an inorganic insulating material and a metal material on a front side of a substrate(100) where semiconductor layers(122,125) are formed. A PR(Photo Resist) is coated on the metal layer, and PR patterns(127) are formed in parts where gate electrodes(147,150) are to be formed through the third mask process. Gate insulating films(135,140) and the gate electrodes(147,150) are formed by etching the metal layer and the inorganic insulating layer. By overetching the two layers, the gate electrodes(147,150) and the gate insulating films(135,140) are formed smaller than the PR patterns(127).

Description

Method of fabricating driving and switching device for liquid crystal display device with integrated driving circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing a top gate type staggered structure thin film transistor which is a driving element for a liquid crystal display device with a driving circuit unit and a switching element.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because the low-temperature process is possible, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has disordered atomic arrangements, weak Si-Si bonds and dangling bonds exist, which are converted into a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

Therefore, in general, a driving device manufactured separately is connected to the liquid crystal panel, and as a representative example, the driving device is manufactured in TCP (Tape Carrier Package) and attached to the liquid crystal panel. Accordingly, in the TCP, a plurality of circuit parts are attached between a PCB (Printed Circuit Board) substrate and a liquid crystal panel to receive a signal input from the PCB substrate and transfer the signal to the liquid crystal panel. However, such a configuration occupies a large part of the cost of the actual equipment of the driver IC, and as the resolution of the liquid crystal panel increases, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP is short. TCP bonding itself is becoming difficult.

On the other hand, since polysilicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. When the polysilicon is used to make a driving circuit directly on a substrate, driving IC costs can be reduced and mounting is simplified.

1 is a schematic diagram of a general liquid crystal display device integrated with a driving circuit unit.

As shown, the driving circuit section 5 and the display section 3 are formed on the insulating substrate 1 together. The display unit 3 is positioned at the center of the substrate 1, and gate and data driving circuit units 5a and 5b are positioned at one side of the display unit 3 and the other side not parallel thereto. In the display unit 3, a plurality of gate lines 7 connected to the gate driving circuit unit 5a and a plurality of data lines 9 connected to the data driving circuit unit 5b cross each other. The pixel electrode 10 is formed in the defined pixel region P, and the thin film transistor T connected to the pixel electrode 10 is positioned at the intersection of the two wires.

In addition, the gate and data driving circuit unit are connected to an external signal input terminal 12.

The gate and data driver circuits 5a and 5b internally adjust an external signal input through the external signal input terminal 12 to display the display control signal to the display unit 3 through the gate and data lines 7 and 9, respectively. And an apparatus for supplying a data signal.

Accordingly, the gate and data driver circuits 5a and 5b are formed with a complementary metal-oxide semiconductor (CMOS) structure thin film transistor (not shown), which is an inverter, to properly output an input signal. It is.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. One conductor is formed and driven in a complementary manner to form a current gate by effective electrical control of the two types of semiconductors.

2A and 2B are cross-sectional views respectively showing cross-sections of thin film transistors that are display element switching elements and drive circuit portion CMOS structure drive elements.

As shown in FIG. 2A, a buffer layer 25 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) is formed on an entire surface of the substrate 20 on the insulating substrate 20, and is disposed on the buffer layer 25. The semiconductor layer 30 is formed, and the gate insulating layer 45 is formed on the entire surface of the semiconductor layer 30. In addition, a gate electrode 50 is formed on the gate insulating film 45, and an interlayer 70 is formed on the gate electrode 50. Semiconductor layer contact holes 73a and 73b for contacting the semiconductor layer 30 are formed in the gate insulating layer 45 and the interlayer insulating layer 70, and the semiconductor layer contact hole 73a is disposed on the interlayer insulating layer 70. , 73b), and the source and drain electrodes 80a and 80b are formed to be spaced apart from the gate electrode 50 by a predetermined distance. A protective layer 90 including a drain electrode contact hole 95 is formed on the drain electrode 80b, and the drain electrode 80 is formed on the protective layer 90 through the drain electrode contact hole 95. ) Is connected to the pixel electrode 97.

In the semiconductor layer 30, a portion of the lower region of the gate insulating layer 45 corresponding to the gate electrode 50 forms an active layer 30a, and a portion of the semiconductor layer 30 contacting the source and drain electrodes 80a and 80b is n ^+. A doped n-type ohmic contact layer 30c is formed, and an n ⁻ doped Lightly Doped Drain (LDD) layer 30b is formed between the active layer 30a and the n-type ohmic contact layer 30c. The LDD layer 30b is doped at a low concentration to disperse hot carriers, thereby preventing an increase in leakage current I _off and preventing a loss of current in an on state. do.

Next, referring to FIG. 2B, which is a cross-sectional view of the CMOS structure thin film transistor of the driving circuit portion. In this case, the CMOS structure thin film transistor of the driving circuit unit includes a thin film transistor unit II including a semiconductor layer 35 doped with n + and a thin film transistor unit III including a semiconductor layer 40 doped with p +. For the sake of convenience, the same elements are denoted by the numerals in the order of II and III.

As illustrated, the n-type semiconductor layer 35 and the p-type semiconductor layer 40 are formed on the transparent insulating substrate 20 having the buffer layer 25 spaced apart from each other by a predetermined distance, and the n-type and p-type semiconductor layers The gate insulating layer 45 is formed on the entire surface of the upper portion 35 and 40, and the gate electrodes 55 and 60 are formed on the gate insulating layer 45. An interlayer insulating layer 70 including semiconductor layer contact holes 75a, 75b, 77a, and 77b is formed on the entire surface of the substrate 20 on the gate electrodes 55 and 60, and the interlayer insulating layer 70 is formed. Source and drain electrodes (83a, 87a, 83b, 87b) contacting the n-type and p-type semiconductor layers 35, 40, respectively, through the semiconductor layer contact holes 75a, 75b, 77a, and 77b, respectively. Is formed, and a protective layer 90 is formed over the entire surface of the source and drain electrodes 83a, 87a, 83b, 87b.

A region of the n-type semiconductor layer 35 corresponding to the gate electrode 55 and formed under the gate insulating layer 45 forms an active layer 35a and contacts the source and drain electrodes 83a and 83b. The semiconductor layer including the region forms an n ⁺ doped n-type ohmic contact layer 35c, and forms an n ⁻ doped LDD layer 35b between the active layer 35a and the n-type ohmic contact layer 35c. have. In addition, since the p-type semiconductor layer 40 uses holes as carriers, since the deterioration of the carrier and the leakage current are less affected than the n-type thin film transistors, the pD semiconductor layer 40 does not form an LDD layer, The semiconductor layer region under the corresponding gate insulating layer 45 forms the active layer 40a, and the outer region of the active layer 40a forms the p-type ohmic contact layer 40c.

As described above, the display unit of the driving circuit-integrated liquid crystal display and the manufacturing method of the driving circuit unit thin film transistor will be described with reference to the drawings.

3A to 3F and 4A to 4F are cross-sectional views illustrating manufacturing processes of the thin film transistors in the display portion thin film transistor portion I and the driving circuit portions n-type and p-type thin film transistor portions II and III, respectively, in manufacturing steps.

As shown in FIGS. 3A and 4A, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the transparent insulating substrate 20 to form a buffer layer 25. After depositing amorphous silicon (a-Si) on the substrate 20 on which the buffer layer 25 is formed, and performing a dehydrogenation process, a laser crystallization process is performed to crystallize the amorphous silicon layer into a polysilicon layer. . Thereafter, a first mask process is performed to pattern the polysilicon layer to form semiconductor layers 30, 35, and 40.

3B and 4B, a silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 20 on which the semiconductor layers 30, 35, and 40 are formed to form a gate insulating layer 45. Subsequently, a metal material, for example, molybdenum (Mo) is deposited on the gate insulating layer 45 and then subjected to a second mask process to form gate electrodes 50, 55, and 60. The gate electrodes 50, 55, and 60 are used as masks to n-do lightly doped drain (LDD) doping by ion implantation on the entire surface of the substrate 20. In this case, the dose of LDD doping is approximately 1E13 / cm 2 to 5E13 / cm 2. At this time, the semiconductor layers 30a, 35a, and 40a under the gate electrodes 50, 55, and 60 of each of the display unit and the driving circuit unit are not doped, and all of the other semiconductor layers 30b, 35b, and 40b are n-doped. .

Next, as shown in FIGS. 3C and 4C, PR is applied to the entire surface of the n-doped substrate 20 and a third mask process is performed to form a PR pattern 62. The PR pattern 62 is formed to include the gate electrodes 50 and 55 in the I and II regions so as to block the upper portion of the gate insulating layer 45 extending from the gate electrodes 50 and 55 at both sides. In the p-type thin film transistor unit III, the PR pattern 63 is formed to completely cover the gate insulating layer 45 corresponding to the semiconductor layer 40 including the gate electrode 60. Thereafter, n + doping by ion implantation having a high concentration of dose is performed on the entire surface of the substrate 20 on which the PR patterns 62 and 63 are formed. At this time, the semiconductor layer of the portion not blocked by the PR patterns 62 and 63 is n + doped to form n-type ohmic contact layers 30c and 35c. At this time, the dose of the n + doping has a value of approximately 1E15 / ㎠ to 9E15 / ㎠. In addition, the portions of the semiconductor layers 30 and 35 in the I and II regions, in which n − and n + doping are blocked by the gate electrodes 50 and 55, form the active layers 30 a and 35 a, and the active layers 30 a, The n-doped portion between 35a) and n-type ohmic contact layers 30c, 35c forms LDD layers 30b, 35b. Thereafter, the PR patterns 62 and 63 are removed.

Next, referring to FIGS. 3D and 4D, a PR is coated on the entire surface of the substrate 20 on which the n-type ohmic contact layers 30c and 35c are formed, and the fourth mask process is performed to form gate electrodes 50 and 55 in the I and II regions. PR pattern 65 is formed so as to cover the gate insulating film 45 of the portion corresponding to the semiconductor layers 30 and 35, and on the gate insulating film of the portion corresponding to the p-type semiconductor layer 40 in the region III. It exposes without forming a PR pattern. Thereafter, p + doping is performed by ion implantation having a high dose of 1E15 / cm 2 to 9E15 / cm 2. The semiconductor layer 40 in which the ion doping is blocked by the gate electrode 60 in the III region forms an active layer 40a, and p + doped portions other than the active layer 40a are p-type ohmic contact layer 40c. ). Thereafter, the PR pattern 65 is removed.

3E and 4E, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 20 on which the p-type ohmic contact layer 40c is formed. The mask process is performed to form the interlayer insulating film 70. At this time, the gate insulating layer 45 is also etched to form semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, 77b exposing a part of the ohmic contact layers 30c, 35c, 40c to the outside. Thereafter, molybdenum (Mo) and aluminum neodymium (AlNd) are sequentially deposited on the substrate on which the interlayer insulating film 70 is formed, and are collectively etched by a sixth mask process to form the semiconductor layer contact holes 73a and 73b. Source and drain electrodes 80a, 83a, 87a, and 80b, 83b, and 87b connected to the ohmic contact layers 30c, 35c, and 40c through 75a, 75b, 77a, and 77b.

Next, as shown in FIGS. 3F and 4F, silicon nitride (SiNx) is formed on the substrate 20 on which the source and drain electrodes (80a, 83a, 87a, 80b, 83b, and 87b) are formed. After the deposition, the hydrogen nitride heat treatment of the silicon nitride (SiNx) is performed, a seventh mask process is performed to form a protective layer 90 having a drain contact hole 95. Since it belongs to the manufacturing process on the array substrate, but will be briefly described as it is associated with the thin film transistor manufacturing process. After the deposition of indium tin oxide (ITO) on the substrate on which the protective layer 90 is formed in the process corresponding to the display portion thin film transistor portion of the region I, an eighth mask process is performed to form the drain contact hole 95. The pixel electrode 97 connected to the drain electrode 90b is formed through the pixel electrode 97.

In the aforementioned thin film transistor manufacturing process of the conventional liquid crystal display integrated with a driver circuit, a total of eight mask processes are performed. Since the mask process includes a photo resist coating, an exposure, and a development, as the mask process is added, manufacturing cost and processing time increase, and thus, the production yield decreases, and the number of masks As it increases, there is a problem in that the probability of generating a defect in the thin film transistor element increases. In addition, in the manufacture of a thin film transistor having a top gate structure as described above, a defect in which the ohmic contact layer doped with n + may be lost due to overetching when the semiconductor layer contact hole is formed.

In order to solve the above problems, in the present invention, a thin film transistor is manufactured in a top gate type staggered type, and the source and drain electrodes are formed under the gate electrode to form a semiconductor layer contact hole. By eliminating the process, defects in which the n + and p + doped layers are lost can be eliminated. In addition, the LDD layer is formed by using over-etching when forming the gate electrode to secure device reliability, and p + doping is performed using counter doping to drive the driving circuit and the switching element for the liquid crystal display device with the integrated driving circuit in six mask processes. It aims at providing the manufacturing method.

1 is a schematic diagram of a general liquid crystal display device integrated with a driving circuit unit;

2A and 2B are cross-sectional views of a conventional display unit switching element and driving circuit unit CMOS structure driving element.

3A to 3F and FIGS. 4A to 4F are cross-sectional views illustrating manufacturing steps of a switching device of a conventional display unit and a CMOS structure driving device of a driving circuit unit, respectively.

5A and 5B are sectional views of a display unit switching element and a driving circuit portion CMOS structure driving element according to the present invention;

6A to 6G and 7A to 7G are cross-sectional views illustrating manufacturing steps of a switching device of a display unit and a CMOS structure driving device of a driving circuit unit according to an exemplary embodiment of the present invention, respectively.

<Description of Symbols for Main Parts of Drawings>

100: insulating substrate 105: buffer layer

112a and 115a: source electrode 112b and 115b: drain electrode

122, 125: semiconductor layer 127: PR pattern

135, 140: gate insulating film 147, 150: gate electrode

Ⅴ: n-type thin film transistor unit

Ⅵ: P-type thin film transistor unit

In order to achieve the above object, a display unit switching element and a driving circuit unit driving element manufacturing method of a drive circuit-integrated liquid crystal display device according to the present invention comprises a display portion composed of a plurality of pixels including an insulating substrate switching element, and a CMOS element Defining a driving circuit unit; Forming first source and drain electrodes spaced apart from the pixels of the display unit, second source and drain electrodes spaced apart from the driving circuit unit, and third source and drain electrodes; Forming first, second, and third semiconductor layers respectively corresponding to the upper portions of the first to third source and drain electrodes; An inorganic insulating layer, a metal layer, and a PR layer are formed on the entire surface of the substrate on which the first to third semiconductor layers are formed, and a mask process is performed to form first to third PR patterns on the first to third semiconductor layers, respectively. Making a step; Etching the metal layer exposed to the outside of the first to third PR patterns and an inorganic insulating layer below the first and third PR patterns to form first to third gate electrodes and a gate insulating layer having a smaller area under each of the PR patterns Wow; N + doping by implanting a first dose of ions into the surfaces of the first to third semiconductor layers exposed to the outside of the first to third PR patterns; After removing the first to third PR patterns, n-doping by implanting a second dose of ions into the surfaces of the first to third semiconductor layers; After forming the fourth PR pattern and the fifth PR pattern completely covering the n-doped first and second source and drain electrodes and the first and second semiconductor layers, the first and second source and drain electrodes are formed on the exposed surface of the third semiconductor layer. Injecting 3 doses of ions into the p + doping; After removing the fourth and fifth PR patterns, forming a protective layer on an entire surface of the substrate on which the p + doped third semiconductor layer and the n + and n-ion doped first and second semiconductor layers are formed. .

According to an exemplary embodiment of the present invention, a method of manufacturing an array substrate including a display switching element and a driving circuit driving element of a liquid crystal display integrated with a driving circuit includes a display unit including a plurality of pixels including a switching element on an insulating substrate, and a CMOS element. Defining a driving circuit unit; Forming first source and drain electrodes spaced apart from the pixels of the display unit, second source and drain electrodes spaced apart from the driving circuit unit, and third source and drain electrodes; Forming first, second, and third semiconductor layers respectively corresponding to the upper portions of the first to third source and drain electrodes; An inorganic insulating layer, a metal layer, and a PR layer are formed on the entire surface of the substrate on which the first to third semiconductor layers are formed, and a mask process is performed to form first to third PR patterns on the first to third semiconductor layers, respectively. Making a step; Etching the metal layer exposed to the outside of the first to third PR patterns and an inorganic insulating layer below the first and third PR patterns to form first to third gate electrodes and a gate insulating layer having a smaller area under each of the PR patterns Wow; N + doping by implanting a first dose of ions into the surfaces of the first to third semiconductor layers exposed to the outside of the first to third PR patterns; After removing the first to third PR patterns, n-doping by implanting a second dose of ions into the surfaces of the first to third semiconductor layers; After forming the fourth PR pattern and the fifth PR pattern completely covering the n-doped first and second source and drain electrodes and the first and second semiconductor layers, the first and second source and drain electrodes are formed on the exposed surface of the third semiconductor layer. Injecting 3 doses of ions into the p + doping; After removing the fourth and fifth PR patterns, forming a protective layer on an entire surface of the substrate on which the p + doped third semiconductor layer and the n + and n-ion doped first and second semiconductor layers are formed; Etching the passivation layer to expose a first drain electrode; Forming a transparent pixel electrode in contact with the exposed first drain electrode and positioned in the pixel.

In this case, after defining the display unit and the driving circuit unit, the method may further include forming a buffer layer on the entire surface of the substrate.

In addition, the semiconductor layer is characterized in that after the deposition of amorphous silicon, crystallized into polysilicon using a laser or the like.

After the p + doping, the method may further include performing an activation process on the first to third semiconductor layers.

After the protective layer is formed, further comprising the step of hydrogenation heat treatment.

The first to third gate electrodes and the gate insulating layer are formed by performing isotropic overetching, and the first dose to be implanted is 1E15 / cm 2 to 9E15 / cm 2, and the second dose is 1E13 / cm 2 to 5E13 The second dose amount has a value of 2E15 / cm 2 to 1E16 / cm 2, and the third dose amount is always ion-implanted at a value larger than the first dose amount.

Hereinafter, a process of manufacturing a top gate type staggered structure thin film transistor, which is a driving element and a switching element, of a driving circuit-integrated liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to the drawings.

5A and 5B are cross-sectional views illustrating thin film transistors, which are switching elements of a display unit, and n-type and p-type thin film transistors, which are driving elements of a CMOS structure of a driving circuit unit, of a liquid crystal display device with an integrated driving circuit according to the present invention, respectively. For convenience of description, the thin film transistor forming unit of the display unit is defined as an IV region, the n-type thin film transistor forming unit of the driving circuit unit CMOS elements is defined as a V region, and the p-type thin film transistor forming unit is defined as an VI region.

As shown in FIG. 5A, a buffer layer 105 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ), is formed on the entire surface of the substrate 100 on the insulating substrate 100, and the upper portion of the buffer layer 105. The source electrode 110a and the drain electrode 110b are formed to be spaced apart from each other at a predetermined interval, and overlap with a portion of the source and drain electrodes 110a and 110b to cover the spaced area between the two electrodes, and to n-type ohmic contact. The semiconductor layer 120 is formed of three parts, a layer 120c, an LDD layer 120b, and an active layer 120a. The gate insulating layer 130 is formed on the active layer 120a of the semiconductor layer 120. A gate electrode 143 is formed, and a passivation layer 160 including a drain contact hole 165 is formed on the gate electrode 143, and the drain contact hole is formed on the passivation layer 160. The pixel electrode 170 is connected to the drain electrode 110b through 165.

In more detail with respect to the semiconductor layer 120, the lower region of the gate insulating layer 130 corresponding to the gate electrode 143 forms an active layer 120a and is in contact with the source and drain electrodes 110a and 110b. The portion forms n ⁺ doped n-type ohmic contact layer 120c and is doped with low concentration n- between the active layer 120a and n-type ohmic contact layer 120c to increase the dispersion of the hot carrier and increase leakage current. LDD (Lightly Doped Drain) layer 120b is formed to prevent the formation.

Next, the CMOS structure thin film transistor of the driving circuit unit will be described with reference to FIG. 5B. At this time, the CMOS of the driving circuit unit is an n-type thin film transistor unit (V) including a n + doped semiconductor layer 122 and a p-type thin film transistor unit (VI) including a semiconductor layer 125 doped with p +. It is composed. As illustrated, the source and drain electrodes 122a, 125a, 122b, and 125b are spaced apart at regular intervals on the insulating substrate 100 on which the buffer layer 105 is formed. And VI, respectively, and overlap with portions of the source and drain electrodes 122a, 125a, 122b, 125b in the n-type and p-type thin film transistor units V, VI, respectively. N-type semiconductor contact layer 122 including n-type ohmic contact layer 122c, LDD layer 122b, and active layer 122a is formed in n-type thin film transistor unit V. The p-type semiconductor layer 125 including the p-type ohmic contact layer 125d and the active layer 125a is formed in the p-type thin film transistor unit VI. In addition, the gate insulating layers 135 and 140 and the gate electrodes 147 and 150 are formed on the active layers 122a and 125a of the semiconductor layers 122 and 125, respectively. Layer 160 is formed. Further, in the region IV of the display TFT, a pixel electrode 170 is formed on the passivation layer 160 to contact the drain electrode 110b through the drain contact hole 165 on the passivation layer 160. .

At this time, in the region VI, since the p-type semiconductor layer 125 uses holes as carriers, since the deterioration and leakage current of the carrier are less affected than the n-type thin film transistors, the p-type ohmic is not formed. It is formed only of the contact layer 125d and the active layer 125a.

A method of manufacturing the n-type and p-type thin film transistors, which are the display switching element and the driving circuit CMOS element, according to the embodiment of the present invention described above.

6A to 6G and 7A to 7G are cross-sectional views illustrating a display thin film transistor and a driving circuit CMOS thin film transistor according to an exemplary embodiment of the present invention, respectively.

First, as illustrated in FIGS. 6A to 7A, an inorganic insulating material such as silicon oxide (SiO ₂ ) is deposited on the transparent insulating substrate 100 to form a buffer layer 105. When the buffer layer 105 crystallizes amorphous silicon with polysilicon, alkali ions, such as potassium ions (K +), sodium ions (Na +), etc. present in the substrate 100 may be generated by heat. It is formed in order to prevent the film quality characteristic of polysilicon from falling by alkali ion. Subsequently, a metal material such as aluminum neodymium (AlNd) is deposited on the entire surface of the buffer layer 105, and a first mask process including PR coating, exposure, development, and etching is performed. Source and drain electrodes 110a, 112a, 115a, and 110b, 112b, and 115b are formed on the region by spaced intervals. In this case, in the display TFT, the drain electrode 110b is formed to be slightly longer than the drain electrodes 112b and 115b in regions V and VI because the drain electrode 110b must be in contact with the pixel electrode to be formed later.

Next, as shown in FIGS. 6B and 7B, amorphous silicon is deposited on the entire surface of the source and drain electrodes 110a, 112a and 115a and 110b, 112b and 115b, and then, by using a laser or the like. The polysilicon layer is formed by performing the crystallization process of the amorphous silicon. Thereafter, a second mask process is performed on the polysilicon layer formed by the crystallization process, and the polysilicon layer is patterned to form source and drain electrodes (110a, 112a, 115a, 110b, 112b, and 115b). The semiconductor layers 120, 122, and 125 are formed on a portion and a portion spaced apart from the two electrodes.

Next, as shown in FIGS. 6C and 7C, an inorganic insulating material and molybdenum of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) are formed on the entire surface of the substrate 100 on which the semiconductor layers 120, 122, and 125 are formed. Metal materials such as (Mo) are continuously deposited to form an inorganic insulating layer and a metal layer, and a photoresist (PR) is completely coated on the metal layer, and gate electrodes 143 and 147 are formed through a third mask process. The PR patterns 127 are formed on portions where 150 is to be formed. Thereafter, the metal layer and the inorganic insulating layer are continuously etched to form gate insulating layers 130, 135, and 140 and gate electrodes 143, 147, and 150. In this case, the over-etching of the two layers is performed so that the gate electrodes 143, 147, and 150 and the gate insulating layers 130, 135, and 140 under the PR pattern 127 are formed smaller than the PR pattern 127. In other words, the width B of the gate electrodes 143, 147, 150 and the gate insulating layers 130, 135, and 140 is formed to be shorter than the width A of the PR pattern 127. 140 and one end of the gate electrodes 143, 147 and 150 and the other end of the PR pattern 127, the other ends of the gate insulating layers 130, 135 and 140 and the gate electrodes 143, 147 and 150 and the An area of the predetermined interval C exists between the other ends of the PR pattern 127.

In this case, the inorganic insulating layer formed on the semiconductor layer does not necessarily need to be formed to form a gate insulating layer positioned only under the gate electrodes 143, 147, and 150. The inorganic insulating layer may be entirely formed of a gate insulating film without etching the inorganic insulating layer. This is because the inorganic insulating layer can be doped to the lower semiconductor layers 120, 122, and 125 by controlling energy during doping.

Thereafter, n + doping by high concentration ion implantation having a dose of 1E15 / cm 2 to 9E15cm 2 is performed using the PR pattern 127 as a blocking mask. At this time, n + doping is also performed in the semiconductor layer 125c of the p-type thin film transistor unit VI of the driving circuit portion in which the p-type semiconductor layer 125 is to be formed, which is later caused by p + doping having a larger dose. It does not matter because it performs counter doping.

Since the PR pattern 127 is used as a blocking mask during the n + doping, the semiconductor layer 120a of the portion corresponding to the blocking mask is not doped. The n + doped portions of the semiconductor layers 120 and 122 of the display unit and the driving circuit unit n-type thin film transistor units IV and V form n-type ohmic contact layers 120c and 122c.

Next, as shown in FIGS. 6D and 7D, after the n-type ohmic contact layers 120c and 122c are formed by n + doping, the PR patterns 127 used as the blocking masks are removed by an etch and strip process. . In this case, in order to remove the PR pattern, only the etching process is performed. However, since the PR pattern in which ions are implanted by doping on the PR is not completely removed by the etching process, the PR pattern is processed by performing a strip process after the etching process. To remove it completely. Thereafter, n-doping is performed by ion implantation having a dose of approximately 1E13 / cm 2 to 5E13 / cm 2 on the entire surface of the substrate 100. In this case, the n-type ohmic contact layers 120c and 122c in which the n + doping is performed in the display unit and the driving circuit unit n-type thin film transistor units IV and V are not affected by the smaller dose of n-doping. In FIG. 7C, the semiconductor layer corresponding to the region of the predetermined interval c positioned between both ends of the PR pattern 127 and both ends of the gate electrodes 143 and 147 is n-doped to form the LDD layers 120b and 122b. In the semiconductor layer below the gate electrodes 120b and 122b, the gate electrodes 143 and 147 act as a blocking mask to form the active layers 120a and 122a without being doped. In this case, n-doping is also performed in the semiconductor layer 125b of the p-type thin film transistor unit VI, but since n-doping is canceled by p + doping, it is not a problem.

Next, as shown in FIGS. 6E and 7E, after the LDD layers 120b and 122b are formed by the n-doping, the fourth mask process is performed to coat PR on the entire surface of the substrate. The PR pattern 155 is formed to completely block the thin film transistor unit IV and the driving circuit unit n-type thin film transistor unit V. As shown in FIG. Then, p ⁺ doping is performed by ion implantation in which 2E15 / cm 2 to 1E16 cm 2 have a dose. In this case, the n-type semiconductor layers 120 and 122 of the display unit and the driving circuit unit n-type thin film transistor units IV and V do not doping because the PR pattern 155 serves as a blocking mask. P + doping is performed on the exposed semiconductor layers (regions 125b and 125c of FIG. 7D) other than the portions blocked by the gate electrode 150 of the semiconductor layer 125. The p + doped semiconductor layer (125b and 125c region of FIG. 7D) forms the p-type ohmic contact layer 125d, and the semiconductor layer that is doped off by the gate electrode 150 forms the active layer 125a. do. The p + doped semiconductor layer (125b and 125c region of FIG. 7D) was p + doped in the state of n + and n-doping, but was counter-doped by higher p + doping, so the p-type ohmic contact layer ( 125d).

6F and 7F, after the doping process is completed, heat is applied to the substrate 100 on which the n-type and p-type ohmic contact layers 120c, 122c, and 125d are formed in a furnace. Or RTA (Rapid Thermal Annealing) process in the chamber or laser activation process. In the activation process, since the crystal form inside the polysilicon forming the semiconductor layers 120, 122, and 125 is partially modified by doping, recrystallization of the semiconductor layers 120, 122, and 125 and electrically activating doped impurities. For that. Subsequently, a protective layer 160 is formed by depositing an entire surface of the substrate 100 such as silicon nitride (SiNx). Thereafter, a hydrogenation heat treatment process is performed on the substrate 100 on which the protective layer 160 is formed to improve characteristics of the device. The hydrogenation heat treatment process is 60 minutes to 180 minutes in an atmosphere of 380 degrees Celsius to 430 degrees Celsius. Subsequently, the passivation layer 160 is patterned by a fifth mask process to form a drain contact hole 165 exposing the drain electrode 110b of the display TFT.

6G and 7G, Indium-Tin-Oxide (ITO) or Indium-Zink, which is a transparent conductive material on the entire surface of the substrate 100 on which the drain contact hole 165 is formed, is shown. -Oxide (Indium-Zinc-Oxide; IZO) is deposited and the pixel electrode 170 is in contact with the drain electrode 110b through the drain contact hole 165 of the thin film transistor unit IV of the display unit by performing a sixth mask process. ).

As described above, the thin film transistor is formed in the top gate type staggered structure by the method of fabricating the thin film transistor of the driving circuit integrated liquid crystal display according to the present invention, thereby forming the contact hole by connecting the semiconductor layer, the source and the drain electrode without forming the contact hole. The omic contact layer loss defect due to the over-etching can be prevented, and at the same time, the mask process for forming the contact hole can be omitted.

In addition, when the gate electrode is formed, overetching is performed to form a gate electrode smaller than the PR pattern formed for patterning the gate electrode, and the doping process is performed by using the PR pattern as a blocking mask. Can be omitted.

Therefore, by manufacturing the thin film transistor of the driving circuit-integrated liquid crystal display device using only eight masks using only six masks, the production process is simplified and the processing time is shortened, thereby improving production yield and reducing manufacturing costs. To provide.

Claims (14)

Defining an insulating substrate as a display portion composed of a plurality of pixels including a switching element and a driving circuit portion configured with a CMOS element; Forming first source and drain electrodes spaced apart from the pixels of the display unit, second source and drain electrodes spaced apart from the driving circuit unit, and third source and drain electrodes; Forming first, second, and third semiconductor layers respectively corresponding to the upper portions of the first to third source and drain electrodes; An inorganic insulating layer, a metal layer, and a PR layer are formed on the entire surface of the substrate on which the first to third semiconductor layers are formed, and a mask process is performed to form first to third PR patterns on the first to third semiconductor layers, respectively. Making a step; Etching the metal layers exposed to the outside of the first to third PR patterns to form first to third gate electrodes and a gate insulating layer having a smaller area under each of the PR patterns; N + doping by implanting a first dose of ions into the surfaces of the first to third semiconductor layers exposed to the outside of the first to third PR patterns; After removing the first to third PR patterns, n-doping by implanting a second dose of ions into the surfaces of the first to third semiconductor layers; After forming the fourth PR pattern and the fifth PR pattern completely covering the n-doped first and second source and drain electrodes and the first and second semiconductor layers, the first and second source and drain electrodes are formed on the exposed surface of the third semiconductor layer. Injecting 3 doses of ions into the p + doping; After removing the fourth and fifth PR patterns, forming a protective layer on an entire surface of the substrate on which the p + doped third semiconductor layer and the n + and n-ion doped first and second semiconductor layers are formed; Switching device for a driving circuit-integrated liquid crystal display device comprising a; and a method of manufacturing a driving device. The method of claim 1, And defining a buffer layer on a front surface of the substrate after defining the display unit and the driving circuit unit. The method of claim 1, The semiconductor layer is a driving device and a method for manufacturing a switching device for a liquid crystal display device integrated with a driving circuit crystallized in polysilicon using a laser or the like after depositing amorphous silicon. The method of claim 1, After the p + doping further comprising the step of performing an activation process for the first to third semiconductor layer drive circuit-integrated liquid crystal display device switching device and driving method manufacturing method. The method of claim 1, After the protective layer is formed, the driving circuit integrated liquid crystal display device switching element and driving device manufacturing method further comprising the step of hydrogenation heat treatment. The method of claim 1, And the first to third gate electrodes and the gate insulating layer are formed by performing isotropic overetching. The method of claim 1, The first dose to be ion implanted is 1E15 / cm 2 to 9E15 / cm 2, the second dose is 1E13 / cm 2 to 5E13 / cm 2, and the third dose is 2E15 / cm 2 to 1E16 / cm 2, and the third dose A method of manufacturing a drive element and a switching element for a liquid crystal display with a drive circuit, wherein the amount is always ion-implanted to a value greater than the first dose. Defining a display unit including a plurality of pixels including a switching element on an insulating substrate, and a driving circuit unit including a CMOS element; Forming first source and drain electrodes spaced apart from the pixels of the display unit, second source and drain electrodes spaced apart from the driving circuit unit, and third source and drain electrodes; Forming first, second, and third semiconductor layers respectively corresponding to the upper portions of the first to third source and drain electrodes; An inorganic insulating layer, a metal layer, and a PR layer are formed on the entire substrate on which the first to third semiconductor layers are formed, and a mask process is performed to form first to third PR patterns on the first to third semiconductor layers, respectively. Making a step; Etching the metal layers exposed to the outside of the first to third PR patterns to form first to third gate electrodes and a gate insulating layer having a smaller area under each of the PR patterns; N + doping by implanting a first dose of ions into the surfaces of the first to third semiconductor layers exposed to the outside of the first to third PR patterns; After removing the first to third PR patterns, n-doping by implanting a second dose of ions into the surfaces of the first to third semiconductor layers; After forming the fourth PR pattern and the fifth PR pattern completely covering the n-doped first and second source and drain electrodes and the first and second semiconductor layers, the first and second source and drain electrodes are formed on the exposed surface of the third semiconductor layer. Injecting 3 doses of ions into the p + doping; After removing the fourth and fifth PR patterns, forming a protective layer on an entire surface of the substrate on which the p + doped third semiconductor layer and the n + and n-ion doped first and second semiconductor layers are formed; Etching the passivation layer to expose a first drain electrode; Forming a transparent pixel electrode in contact with the exposed first drain electrode and positioned in the pixel Method of manufacturing an array substrate for a drive circuit-integrated liquid crystal display device comprising a. The method of claim 8, And defining a buffer layer on the entire surface of the substrate after defining the display unit and the driving circuit unit. The method of claim 8, The semiconductor layer is a method of manufacturing an array substrate for a liquid crystal display device of a drive circuit-integrated liquid crystal after the deposition of amorphous silicon, crystallized in polysilicon using a laser or the like. The method of claim 8, And performing the activation process of the first to third semiconductor layers after the p + doping. The method of claim 1, And forming a hydrogenation heat treatment after the protective layer is formed. The method of claim 1, And the first to third gate electrodes and the gate insulating film are formed by performing isotropic overetching. The method of claim 1, The first dose to be ion implanted is 1E15 / cm 2 to 9E15 / cm 2, the second dose is 1E13 / cm 2 to 5E13 / cm 2, and the third dose is 2E15 / cm 2 to 1E16 / cm 2, and the third dose A method of manufacturing an array substrate for a drive circuit-integrated liquid crystal display device, wherein the amount is always implanted with a value greater than the first dose.