KR100316269B1 - Thin film transistor, liquid crystal display and method for fabricating the same - Google Patents

Abstract

PURPOSE: A thin film transistor, a liquid crystal display and a method for fabricating the thin film transistor and liquid crystal display are provided to improve reliability of the liquid crystal display and simplify fabricating processes. CONSTITUTION: A thin film transistor includes an insulating substrate(40), source and drain electrodes(41S,41D) formed on the insulating substrate, source and drain regions(42S,42D) formed of heavily doped impurity silicon on the source and drain electrodes, and an active layer connected to the source and drain regions and the source and drain electrodes. The thin film transistor further includes an LDD region(43L) that is formed in the active layer and comes into contact with the source and drain regions and the source and drain electrodes, and a gate electrode(45) formed on the active layer having a gate insulating layer(44) formed between the gate electrode and the active layer.

Description

Thin film transistor, liquid crystal display device and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), a liquid crystal display (LCD), and a method of manufacturing the same. Particularly, in forming a source / drain region and a source / drain electrode, The present invention relates to a thin film transistor liquid crystal display device and a method for manufacturing the same, which can simplify the manufacturing process by using only the photosensitive film pattern.

1 is a cross-sectional view showing a first example of a conventional TFT.

The source electrode 11S and the drain electrode 11D are formed on the insulating substrate 10, and the active layer 13 is formed thereon, and the gate insulating film 14 and the gate electrode 15 are formed on the active layer 13. Formed. The active layer 13 is formed with a source region 13S and a drain region 13D formed by doping impurities at a high concentration. At this time, the impurity concentration of the source / drain regions 13S and 13D should have a high concentration of about 10 ¹⁹ to ²¹ / cm 3 to ^improve contact resistance with the source / drain electrodes 11S and 11D. Then, the passivation layer 16 covers the entire surface of the substrate, and exposes a portion of the source / drain electrodes 11S and 11D, and the source / drain electrodes exposing the transparent conductive wirings 17-1 and 17-2. 11S) is formed on the protective film 16 in connection with 11D.

However, in the conventional TFT as described above, since the source / drain regions are formed of a high concentration of impurities, a large leakage current in the off state occurs, which makes it difficult to apply the switching element of the pixel.

Therefore, as an alternative for reducing the leakage current in the off state, a TFT structure having an LED or offset structure has been proposed. 2 is a cross-sectional view illustrating a TFT having an LED structure for explaining a second example of the prior art.

The source electrode 21S and the drain electrode 21D are formed on the insulating substrate 20, and the active layer 23 is formed thereon, and the gate insulating film 24 and the gate electrode 25 are formed on the active layer 23. Formed. The active layer 23 is formed with a source region 23S and a drain region 23D formed by doping impurities at a high concentration, and an LED region 23L doped with a low concentration. A source / drain electrode having the protective layer 26 covering the entire surface of the substrate and exposing a part of the source / drain electrodes 21S and 21D and exposing the transparent conductive wirings 27-1 and 27-2 ( 21S) and 21D are formed on the protective film 26. As shown in FIG. In this example, the source / drain regions 23S and 23D are heavily doped, so that the contact resistance with the source / drain electrodes 21S and 21D is good, and the LED region 23L is formed therein. As a result, the structure can reduce the leakage current in the off state.

3A to 3E are manufacturing process diagrams of the conventional TFT shown in FIG.

Referring to FIG. 3A, after the first conductive layer is formed on the insulating substrate 20, a photolithography process is performed on the first conductive layer to form source / drain electrodes 21S and 21D. Subsequently, after the polycrystalline silicon layer is formed on the entire surface, a photolithography process is performed to form the active layer 23.

Referring to FIG. 3B, after the first insulating film and the second conductive layer are formed on the entire surface, the gate electrode 25 is formed by performing a photolithography process on the second conductive layer, and then using the gate electrode 25 as a mask. The first insulating film at the bottom thereof is etched to form the gate insulating film 24.

Referring to FIG. 3C, the exposed portion of the active layer is doped at low concentration using n-type or P-type ions on the front surface. At this time, the gate electrode 25 serves as a mask for low concentration ion doping. Unexplained reference numeral 23L denotes a portion of the active layer that is lightly doped.

Referring to FIG. 3D, the photoresist pattern PR may be formed to cover the gate electrode 25 and the portion of the active layer surrounding the gate electrode, that is, the portion defined as the LED region. Thereafter, a high concentration of n-type or P-type ions is formed on the entire surface to form a high concentration impurity region, that is, source / drain regions 23S and 23D, in the exposed active layer. At this time, the low concentration ion region in which the high concentration ion doping is blocked by the photoresist pattern PR becomes the LED region 23L with respect to the source / drain region. In this case, if the low concentration ion doping process as shown in Fig. 3C is omitted, the LED region 23L becomes an offset region.

Referring to FIG. 3E, a second insulating film, which is a protective film 26, is formed on the entire surface, and then a photolithography process is performed to form a contact hole exposing a part of the source / drain electrodes 21S and 21D. Subsequently, after the transparent conductive layer is formed on the entire surface, the photolithography process is performed to form the transparent conductive wirings 27-1 and 27-2.

However, the prior art described as described above has a problem in that a masking process, a photolithography process, and an ion doping process must be additionally performed to form the LED area.

It is an object of the present invention to provide a TFT and an LCD having a structure for forming a source / drain region for improving contact resistance with a source / drain electrode and for simplifying the overall manufacturing process. To this end, the present invention forms a source / drain region and a source / drain electrode using one photoresist pattern.

The present invention relates to an insulating substrate, a source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, and the source / drain region and the source / drain electrode. A thin film transistor comprising an active layer formed to be in contact with the active layer, an LED region formed in the active layer and contacting the source / drain region and the source / drain electrode, and a gate electrode formed on the active layer with a gate insulating layer interposed therebetween. do.

The present invention also provides an insulating substrate, a source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, the source / drain region, and the source / drain region. A first thin film including an active layer formed to contact an electrode, an active region formed on the active layer, the LED region contacting the source / drain electrode, and a gate electrode interposed with a gate insulating layer on the active layer A transistor, a source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, and an active layer formed to contact the source / drain region and the source / drain electrode And formed in the active layer, wherein the source / drain regions and the source / de A second thin film transistor including a high concentration impurity region in contact with a phosphorus electrode, a gate electrode having a gate insulating film interposed therebetween, and the first and second thin film transistors, the first and second thin film transistors of A protective layer having contact holes exposing source / drain regions, respectively, and a connection electrically connecting the source / drain regions exposed by the contact holes to form a CMOS structure between the first thin film transistor and the second thin film transistor; Provided is a thin film transistor including wiring.

In addition, the present invention is a step of sequentially forming a first conductive layer and an impurity silicon layer on the insulating substrate, etching the impurity silicon layer to form a source / drain region, and etching the first conductive layer to Forming a source / drain electrode under the source / drain region, forming an active layer in contact with the source / drain region and the source / drain electrode, and a gate having a gate insulating layer interposed therebetween on the active layer It provides a method of manufacturing a thin film transistor comprising the step of forming an electrode.

In addition, the present invention is to define a first thin film transistor region and a second thin film transistor region on the insulating substrate, sequentially forming a first conductive layer and an impurity silicon layer on the insulating substrate, and the impurity silicon layer Etching to form a source / drain region in each of the regions, etching the first conductive layer to form source / drain electrodes positioned under the source / drain regions of the respective regions, and Forming an active layer in contact with the source / drain region and the source / drain electrode in each region, and forming a gate electrode interposed with a gate insulating film on the active layer of each region; Forming a low concentration impurity region of a first conductivity type in an active layer of a type 1 thin film transistor region, and the second type thin film transistor Forming a high-concentration impurity region of a second conductivity type in the active layer of the stud region, forming a protective film covering each of the regions, the protective film being formed to expose the source / drain regions of each region; It provides a method for manufacturing a thin film transistor comprising the step of forming a connection wiring connecting the exposed source / drain region so that the type thin film transistor and the second type thin film transistor form a CMOS structure.

The present invention also provides a liquid crystal display device comprising a pixel portion thin film transistor and a CMOS circuit portion type 1 and type 2 thin film transistor, comprising: an insulating substrate, a source / drain electrode formed on the insulating substrate; A source / drain region formed of high concentration impurity silicon on the source / drain electrode, an active layer formed on the source / drain region and the source / drain electrode, and formed on the active layer, wherein the source / drain region and the source / drain electrode A pixel portion thin film transistor including an LED region in contact with the substrate, a gate electrode having a gate insulating film interposed on the active layer, and a circuit portion first thin film formed on the insulating substrate to have the same structure as the pixel thin film transistor. A transistor, a source / drain electrode formed on the insulating substrate, and the source / drain A source / drain region formed of high concentration impurity silicon on the electrode, an active layer formed to contact the source / drain region, and the source / drain electrode, and formed in the active layer, wherein the source / drain region and the source / drain electrode A second thin film transistor including a high concentration impurity region in contact with the gate electrode and a gate electrode having a gate insulating layer interposed therebetween, the pixel portion thin film transistor, the circuit portion first and second thin film transistors, and the pixel portion thin film transistor. A protective film having a contact hole formed to expose a drain region of the first thin film transistor and a source / drain region of the circuit part first thin film transistor, and a pixel electrode connected to the exposed drain region of the pixel part thin film transistor; The circuit part first thin film transistor and the circuit part Second thin film transistor is to achieve a CMOS structure including the first thin film transistor circuit, and connected to each electrically connected to the source / drain region of the second thin film transistor wiring circuit provides a liquid crystal display device formed.

In addition, the present invention provides a method for manufacturing a liquid crystal display device comprising a pixel portion thin film transistor and a CMOS portion circuit type first type and second type thin film transistor, wherein the insulating substrate has a first conductive layer and a first conductive impurity silicon layer. And forming source / drain regions respectively by etching the impurity silicon layer, and source / drain electrodes positioned under the respective source / drain regions by etching the first conductive layer. And forming active layers in contact with the source / drain electrodes positioned below the respective source / drain regions, respectively, and forming a gate electrode interposed with a gate insulating film on each active layer. Forming a first layer on the active layer of the thin film transistor of the pixel portion and the active layer of the first type thin film transistor of the circuit portion; Forming a low-concentration impurity region of a conductive type, forming a high-concentration impurity region of a second conductivity type in an active layer of the circuit type second thin film transistor, and covering an entire surface of the exposed substrate, Forming a protective film having a contact hole exposing a drain region, a first type of the circuit portion, and a source / drain region of the second type thin film transistor, and a pixel electrode connected to the drain region of the pixel portion thin film transistor; And forming a connection wiring for electrically connecting the source / drain regions of the circuit part type 1 and the second type thin film transistor so that the circuit part type 1 thin film transistor and the circuit part type 2 thin film transistor have a CMOS structure. It provides a method for manufacturing a liquid crystal display comprising the.

In the present invention, the impurity silicon layer may proceed by isotropic etching, and the first conductive insect may be etched anisotropically. In addition, the impurity silicon layer and the first conductive layer may be simultaneously etched using an etchant having different etching selectivity with respect to the impurity silicon layer and the first conductive layer.

1 is a view showing a first example of a thin film transistor according to the prior art

2 is a view showing a second example of a thin film transistor according to the prior art;

3A to 3E are manufacturing process diagrams of the thin film transistor shown in FIG.

4 is a cross-sectional view of a thin film transistor showing a first embodiment of the present invention.

5A through 5E are manufacturing process diagrams of the thin film transistor shown in FIG.

6A through 6F are manufacturing process diagrams of a thin film transistor having a CMOS structure for explaining a second embodiment of the present invention.

7A to 7B are manufacturing process diagrams of a thin film transistor having a CMOS structure for explaining a third embodiment of the present invention.

8A to 8C are manufacturing process diagrams of the liquid crystal display device to which the present invention is applied.

9 is a view for explaining another liquid crystal display device to which the present invention is applied.

4 is a cross-sectional view of a TFT showing a first embodiment of the present invention.

A source electrode 41S and a drain electrode 41D are formed on the insulating substrate 40, and a source region 42S and a drain region 42D formed of silicon doped with a high concentration of impurities are formed thereon. . The active layer 43 is formed to contact each of them, and a gate insulating film 44 and a gate electrode 45 are formed on the active layer 43. In this case, the LED region 43L formed by doping impurities at low concentration is formed in the active layer 43. Therefore, the present invention has an LED structure. The protective film 46 covers the entire surface of the substrate, and exposes a portion of the source / drain regions 42S and 42D, and the source / drain regions are exposed by the transparent conductive wirings 47-1 and 47-2. It is connected to (42S) (42D), and is formed on the protective film 46.

In the present invention according to this embodiment, since the source / drain electrodes 41S and 41D are connected to the source / drain regions 42S and 42D which are high concentration ion regions, the contact resistance can be reduced.

5A to 5E show manufacturing process drawings of the TFT shown in FIG.

Referring to FIG. 5A, after the first conductive layer 41 L and the impurity silicon layer 41 L, which is a silicon layer doped with a high concentration of impurities, are successively formed on the insulating substrate 40, the photoresist pattern for forming the source / drain electrodes is formed. To form (PR). In this case, the first conductive layer 41L may be formed by depositing a conventional metal conductive material such as molybdenum or aluminum by sputtering. In addition, the impurity silicon layer 42L may be formed by depositing a material containing amorphous silicon and n-type ions by PECVD, or forming an amorphous silicon layer first and then doping the n-type ions over the entire surface of the amorphous silicon layer.

Referring to FIG. 5B, the source silicon layer 42S and the drain region 42D are etched by etching the impurity silicon layer 42L at the bottom thereof using the photoresist pattern PR for forming the source / drain electrodes as a mask. The first conductive layer 41L is etched using the photoresist pattern PR as a mask to form a source electrode 41S and a drain electrode 41D. At this time, the impurity silicon layer is excessively etched so that the source / drain regions 42S and 42D are narrower than the source / drain electrodes 41S and 41D. At this time, it is preferable to form the impurity silicon layer and the first conductive layer as thin as about 200 to 2000 mW (appropriately 600 mW).

To this end, the impurity silicon layer 42 L is isotropically etched and the first conductive layer 41 L is anisotropically etched. The impurity silicon layer and the first conductive layer are etched by dry etching or wet etching. It can proceed sequentially by. In the case of wet etching, the impurity silicon layer may be a mixture of (HNO ₃ + HF + H ₂ O) or a mixture of (CrO ₃ + HF + H ₂ O) as an etching solution, and the first conductive layer may be a molybdenum layer. In the case of an aluminum layer, a mixture of (H ₃ PO ₄ + CH ₃ COOH + HNO ₃ + H ₂ O) may be used as an etching solution. In the case of dry etching, the impurity silicon layer may use a mixed gas of (CF ₄ + O ₂ ) or a mixed gas of (C ₂ ClF ₅ + O ₂ ) as an etching gas, and the first conductive layer is a molybdenum layer or aluminum In the case of a layer, a gas such as Cl ₂ , BCl ₃ , or CCl ₄ may be used as an etching gas.

In addition, the impurity silicon layer 42L and the first conductive layer 41L may be simultaneously etched using the etching selectivity. At this time, the source / drain regions 42S and 42D may be narrower than the source / drain electrodes 41S and 41D only by using a mixed etchant having a higher etching selectivity in the impurity silicon layer than the first conductive layer. .

Referring to FIG. 5C, after the photoresist pattern is removed, a polycrystalline silicon layer is formed on the entire surface, and then photo-etched to form an active layer in contact with the source / drain electrodes 41S and 41D and the source / drain regions 42S and 42D. To form 43. Subsequently, after the first insulating film and the second conductive layer are formed on the entire surface, the gate electrode 45 is formed by performing a photolithography process on the second conductive layer, and then the gate electrode 45 is used as a mask. The first insulating film is etched to form a gate insulating film 44. In this case, the first insulating film may be used as the gate insulating film without being etched.

Referring to FIG. 5D, an LED doping process using low concentration n-type ions is performed on the entire surface to form an LED region 43L which is a low concentration ion region in the exposed active layer. Therefore, the present invention constitutes the TFT of the LED structure. In this case, if the ion doping process using low concentration n-type ions is omitted, the LED region 43L becomes an offset region.

Referring to FIG. 5E, after forming the second insulating layer on the entire surface, a photolithography process is performed to form contact holes exposing the source / drain regions 42S / 42D. Subsequently, after the transparent conductive layer is formed on the entire surface, a photolithography process is performed to form transparent conductive wirings 47-1 and 47-2. In this case, the transparent conductive wirings 47-1 and 47-2 may be used as source / drain wirings or pixel electrodes.

As seen in the first embodiment, the present invention can simplify the manufacturing process since the source / drain electrodes and the source / drain regions are formed using one photosensitive film pattern. In addition, since the impurity silicon layer doped with a high concentration of ions is also used as the ohmic contact layer, the contact resistance can be reduced.

Although the present invention shown in this embodiment is an n-type TFT, by performing an ion doping process using p-type ions, it is possible to form an LED structure TFT which forms an LED region 43L in a low concentration p-type ion region. Can be. At this time, the source / drain regions 42S and 42D may be formed as a high concentration p-type ion region.

The TFT of the present invention can be applied to a CMOS structure, which can be described with reference to FIGS. 6A to 6E. The TFT shown below is formed on the same substrate as the pixel portion of the liquid crystal display, thereby showing a structure for advancing through the same process. In the figure, the left side shows an n-type TFT (n-TFT) and the right side shows a P-type TFT (p-TFT).

Referring to FIG. 6A, after the first conductive layer 61 L and the impurity silicon layer 62 L are successively formed on the insulating substrate 60, the photosensitive film pattern PR for forming the source / drain electrodes is formed, respectively. In this case, the first conductive layer 61L may be formed by depositing a conventional conductive material such as molybdenum or aluminum by sputtering. In addition, the impurity silicon layer 62L may be formed by depositing a material containing amorphous silicon and n-type ions by PECVD, or forming an amorphous silicon layer first and then doping the n-type ions over the entire surface of the amorphous silicon layer.

Referring to FIG. 6B, the impurity silicon layer at the bottom thereof is etched using the photoresist pattern PR for forming the source / drain electrodes as a mask, so that the source regions 62S and 62S 'and the drain regions 62D and 62D' are etched. The first conductive layer is etched using the photoresist pattern PR as a mask to form source electrodes 61S, 61S ', and drain electrodes 61D, 61D', respectively. At this time, the impurity silicon layer is overetched so that the source / drain regions are formed narrower than the source / drain electrodes. Since the etching technique has been described above in the first embodiment, the description thereof is omitted.

Referring to FIG. 6C, after the polycrystalline silicon layer is formed on the entire surface, photolithography is performed to form active layers 63 and 63 ′ contacting the source / drain electrodes and the source / drain regions, respectively. Subsequently, after the first insulating film and the second conductive layer are formed on the entire surface, a photolithography process is performed on the second conductive layer to form gate electrodes 65 and 65 ', respectively, and then these gate electrodes are used as masks. The first insulating film at the bottom thereof is etched to form gate insulating films 64 and 64 ', respectively. In this case, the first insulating film may be used as the gate insulating film without being etched.

Referring to FIG. 6D, an ion doping process using a low concentration of n-type ions is performed on the entire surface, and the exposed active layer is lightly doped with n-type ions. In this case, the low concentration n-type ion region of the n-type TFT becomes the LED region 63L.

Referring to FIG. 6E, after forming the photoresist pattern PR covering the n-type TFT, an ion doping process using a high concentration of p-type ions is performed on the entire surface, that is, an exposed portion of the active layer 63 'of the p-type TFT. In the previous step, the portion doped with a low concentration of n-type ions is converted into a high concentration of p-type ion region 63H. The broken p-type TFT is manufactured.

Referring to FIG. 6F, after forming the second insulating film on the entire surface, a photolithography process is performed to form contact holes exposing the source / drain regions 62S, 62S ', 62D, and 62D'. Subsequently, after the transparent conductive layer is formed on the entire surface, a photolithography process is performed to connect the source and drain electrodes to the n-type and p-type TFTs so as to form CMOS. 2) (67-3) is formed.

7A to 7B show that in the TFT of the present invention applied to a CMOS structure, in the case of a P-type TFT, the source and drain regions, which are high concentration n-type ion regions, are counter-doped in the process of performing a high concentration p-type ion doping process, It is a proposed structure to prevent the contact resistance with the transparent conductive wiring layer from being weakened. Subsequent processes are carried out on the resulting substrate as shown in Figs. 6A to 6E as follows.

Referring to FIG. 7A, after forming the second insulating layer 46 on the entire surface, a photolithography process is performed to form contact holes exposing source / drain regions 62S, 62S ', 62D, and 62D'. do. Subsequently, an exposed portion of the source / drain region is removed using the etched second insulating layer 46 as a mask to expose a portion of the source / drain electrodes 61S, 61S ', 61D, and 61D' at the bottom. Let's do it. The removed portion of the source / drain region was initially a high concentration of n-type ion region, but was a counter-doped portion with a high concentration of ions in the process of doping p-type ions at a high concentration.

Referring to FIG. 7B, after the transparent conductive layer is formed on the front surface, a photolithography process is performed to connect the respective source and drain electrodes to form n-type and p-type TFTs in CMOS. 67-2 and 67-3. In this case, since the transparent conductive wiring is directly connected to the source / drain electrodes, rather than the source / drain region where the ion concentration is reduced by counter doping, the contact resistance is relatively good.

When the present invention described above is applied to a liquid crystal display device which simultaneously forms a pixel portion and a circuit portion on the same substrate, the manufacturing process is as follows. The embodiment of the present invention described below is an example in which the pixel portion TFT is formed to be n type.

Referring to Fig. 8A, as described with reference to Figs. 5A and 6A to 5C and 6C, the source / drain electrodes 41S, 61S and 61 on the insulating substrate 100 in which the pixel portion and the circuit portion are defined. 41D, 61D, 61D ', source / drain regions 42S, 62S, 62S', 42D, 62D, 62D ', active layers 43, 63, 63', Gate insulating films 44, 64, 64 ', and gate electrodes 45, 65, 65' are formed, respectively.

Subsequently, an ion doping process using low concentration n-type ions is performed on the entire surface, and the exposed active layer is doped at low concentration. (The reference numerals 43L, 63L, and 63L 'are low concentration n-type ion regions formed in this process.) At this time, the low concentration n-type ion regions of the TFT of the pixel portion and the n-type TFT of the circuit portion are the LED regions 43L and 63L. Used as

Referring to FIG. 8B, after forming the photosensitive film pattern PR for exposing the P-type TFT of the circuit portion, an ion doping process using high concentration p-type ions is performed on the entire surface to expose the active layer 63 'of the p-type TFT. In other words, the portion doped with a low concentration of n-type ions in the previous process is counter-doped to convert into a high concentration of p-type ion region 63H.

Referring to FIG. 8C, after the second insulating film is formed on the entire surface, a photolithography process is performed, so that the drain region 42D of the pixel portion and the source / drain regions 62S, 62S ', 62D, 62D' of the circuit portion. A contact hole is formed to expose the gap. Subsequently, after the transparent conductive layer is formed on the entire surface, a photolithography process is performed to form the pixel electrode 47 connected to the drain region of the pixel portion. Transparent conductive wirings 67-1, 67-2 and 67-3 connecting the electrode and the drain electrode are formed.

At this time, as mentioned, the source and drain regions 61S 'and 61D', which are high concentration n-type ion regions, are doped with high concentration p-type ions in the P-type thin film transistor (see FIG. 8B), In order to prevent the contact resistance with the transparent conductive wiring layer from being weakened, the counter-doped portion can be removed so that the transparent conductive wiring can be directly connected to the source / drain electrodes as shown in FIG. 9.

In the present invention, the source / drain regions are formed by doping a high concentration of impurities so as to have low contact resistance with the source / drain electrodes, and the source / drain regions and the source / drain electrodes are formed using one photosensitive film pattern, thereby simplifying the manufacturing process. can do.

Claims (27)

Insulation board, A source / drain electrode formed on the insulating substrate; A source / drain region formed of high concentration impurity silicon on the source / drain electrode; An active layer formed to contact the source / drain region and the source / drain electrode; An LED region formed in the active layer and in contact with the source / drain region and the source / drain electrode; A thin film transistor comprising a gate electrode formed by interposing a gate insulating film on the active layer. The method according to claim 1, A protective film formed to have a contact hole exposing a portion of the source / drain region; And a connection wiring connected to the exposed source / drain regions and formed on the passivation layer. The method according to claim 2, The connection wiring is a thin film transistor, characterized in that formed of a transparent conductive material. The method according to claim 3, A thin film transistor, wherein the connection wiring is used as a pixel electrode. The method according to claim 1, And a contact hole exposing a portion of the source / drain electrode in the passivation layer and the source / drain region. Insulation board, A source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, an active layer formed to contact the source / drain region and the source / drain electrode, and A first thin film transistor formed on an active layer, the first thin film transistor including an LED region in contact with the source / drain region and the source / drain electrode, and a gate electrode interposed with a gate insulating layer on the active layer; A source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, an active layer formed to contact the source / drain region and the source / drain electrode, and A second thin film transistor formed on the active layer, the second thin film transistor including a high concentration impurity region in contact with the source / drain region and the source / drain electrode, and a gate electrode having a gate insulating layer interposed therebetween; A passivation layer covering the first and second thin film transistors and having contact holes exposing source / drain regions of the first and second thin film transistors, respectively; And a connection wiring electrically connecting the source / drain regions exposed by the contact hole to form the CMOS structure between the first thin film transistor and the second thin film transistor. The method according to claim 6, The thin film transistor of claim 1, wherein the LED region of the first thin film transistor and the high concentration impurity region of the second thin film transistor have different conductivity types. The method according to claim 6, Each of the first and second thin film transistors has contact holes which are commonly present in the passivation layer and the source / drain regions so as to expose the source / drain electrodes, and the connection wiring is connected to the source / drain electrodes. Characteristic thin film transistor. Sequentially forming a first conductive layer and an impurity silicon layer on the insulating substrate; Etching the impurity silicon layer to form a source / drain region; Etching the first conductive layer to form a source / drain electrode under the source / drain region; Forming an active layer in contact with the source / drain region and the source / drain electrode; And forming a gate electrode having a gate insulating film interposed therebetween on the active layer. The method of claim 9, wherein the forming of the source / drain region and the source / drain electrode comprises: Forming a photoresist pattern for forming a source / drain on the impurity silicon layer; Over-etching the impurity silicon layer using the photoresist pattern as a mask to form the source / drain regions; And forming a source / drain electrode by etching the first conductive layer using the photoresist pattern as a mask. The method according to claim 9, And performing a low concentration ion doping process using the gate electrode as a mask to form a low concentration impurity region in the active layer. The method according to claim 9 or 10, Wherein the impurity silicon layer is etched isotropically and the first conductive layer is etched anisotropically. The method according to claim 9 or 10, The etching of the impurity silicon layer and the first conductive layer is a method of manufacturing a thin film transistor, characterized in that by the dry etching method. The method according to claim 9 or 10, And etching the impurity silicon layer and the first conductive layer simultaneously using an etchant having an etching selectivity higher than that of the first conductive layer. The method according to claim 9, Forming a protective film covering the exposed substrate; Forming a contact hole in the passivation layer to expose a portion of the source and drain regions; And forming a transparent wiring connected to the exposed source and drain regions. The method according to claim 9, Forming a protective film covering the exposed substrate; Forming a contact hole in the passivation layer and the source / drain region to expose a portion of the source / drain electrode; And forming a transparent wiring connected to the exposed source / drain electrodes. The method according to claim 9, The impurity silicon layer and the first conductive layer are each formed in a thin film transistor manufacturing method characterized in that about 200 ~ 2000Å. Defining a first thin film transistor region and a second thin film transistor region on the insulating substrate; Sequentially forming a first conductive layer and an impurity silicon layer on the insulating substrate; Etching the impurity silicon layer to form source / drain regions in each of the regions; Etching the first conductive layer to form source / drain electrodes positioned under the source / drain regions of the respective regions; Forming active layers formed in the respective regions so as to contact the source / drain regions and the source / drain electrodes, respectively; Forming a gate electrode interposed with a gate insulating film on the active layer in each of the regions; Forming a low concentration impurity region of a first conductivity type in an active layer of the first type thin film transistor region; Forming a high concentration impurity region of a second conductivity type in an active layer of the second type thin film transistor region; Forming a passivation layer covering each of the regions, wherein the passivation layer is formed to expose the source / drain regions of each region; And forming a connection wiring connecting the exposed source / drain regions to form a CMOS structure between the first type thin film transistor and the second type thin film transistor. The method according to claim 18, The connection wiring is a thin film transistor manufacturing method characterized in that formed with a transparent conductive material. The method according to claim 18, Forming a passivation layer covering the first type and the second type thin film transistor regions and having a contact hole exposing the drain region of the first type thin film transistor; And forming a pixel electrode connected to the drain region of the exposed first type thin film transistor. The method of claim 18, wherein the forming of the source / drain region and the source / drain electrode comprises: Forming a photoresist pattern for forming a source / drain on the impurity silicon layer; Over-etching the impurity silicon layer using the photoresist pattern as a mask to form the source / drain regions; And etching the first conductive layer using the photoresist pattern as a mask, and forming a source / drain electrode to be selectively exposed to the thin film transistor. The method of claim 18, wherein the forming of the high-concentration impurity region of the second conductivity type of the second type thin film transistor includes: Forming a photoresist pattern covering the first thin film transistor region; And doping impurities having a second conductivity type on the exposed entire surface of the substrate at a high concentration. A liquid crystal display device comprising a pixel portion thin film transistor and a CMOS portion circuit type first and second type thin film transistors, Insulation board, A source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, an active layer formed on the source / drain region and the source / drain electrode, and the active layer A pixel portion thin film transistor formed on the active material layer, the LED region in contact with the source / drain region and the source / drain electrode, and a gate electrode having a gate insulating layer interposed therebetween on the active layer; A circuit part first thin film transistor formed on the insulating substrate to have the same structure as the pixel part thin film transistor; A source / drain electrode formed on the insulating substrate, a source / drain region formed of high concentration impurity silicon on the source / drain electrode, an active layer formed to contact the source / drain region and the source / drain electrode, and A second thin film transistor formed on the active layer, the second thin film transistor including a high concentration impurity region in contact with the source / drain region and the source / drain electrode, and a gate electrode having a gate insulating film interposed therebetween; The pixel portion thin film transistor and the circuit portion first and second thin film transistors are covered, and the drain regions of the pixel portion thin film transistor and the source / drain regions of the circuit portion first thin film transistor and the circuit portion second thin film transistor are respectively formed. A protective film having a contact hole, A pixel electrode connected to the exposed drain region of the pixel portion thin film transistor; And a connection wiring electrically connecting the source / drain regions of the circuit part first thin film transistor and the circuit part second thin film transistor so that the circuit part first thin film transistor and the circuit part second thin film transistor have a CMOS structure. LCD display device. The method according to claim 23, And the LED region of the pixel portion thin film transistor and the circuit portion first thin film transistor and the high concentration impurity region of the circuit portion second thin film transistor have different conductivity types. The method according to claim 23, A contact hole common to the passivation layer and the source / drain region is formed to expose the circuit part second thin film transistor source / drain electrode, and the connection line connected to the circuit part second thin film transistor is connected to the exposed source. Liquid crystal display characterized in that it is connected to the drain electrode. A liquid crystal display device manufacturing method comprising: a pixel portion thin film transistor and a CMOS circuit portion type 1 and type 2 thin film transistor; Sequentially forming a first conductive layer and a first conductive impurity silicon layer on the insulating substrate; Etching the impurity silicon layer to form source / drain regions, respectively; Etching the first conductive layer to form source / drain electrodes positioned under the respective source / drain regions, respectively; Forming an active layer in contact with each of the source / drain regions and a source / drain electrode disposed below the source / drain region; Forming a gate electrode having a gate insulating film interposed therebetween on each of the active layers; Forming a low concentration impurity region of a first conductivity type in the active layer of the thin film transistor of the pixel portion and the active layer of the first type thin film transistor of the circuit portion; Forming a high concentration impurity region of a second conductivity type in an active layer of the circuit part type 2 thin film transistor; Forming a passivation layer covering the entire surface of the exposed substrate and having a contact hole exposing a drain region of the pixel portion thin film transistor and a source / drain region of the first type and the second type thin film transistor of the circuit portion, respectively; Sources of the circuit part type 1 and the second type thin film transistor such that the pixel electrode connected to the drain region of the pixel part thin film transistor, the circuit part type 1 thin film transistor and the circuit part type 2 thin film transistor have a CMOS structure. Forming a connection wiring for electrically connecting the drain region. The method of claim 26, An etching process using the passivation layer as a mask in the source / drain regions to expose a portion of the source / drain electrodes, and the connection wiring is connected to the exposed source / drain electrodes Manufacturing method of And forming a contact hole in the passivation layer and the source / drain region to expose a portion of the source / drain electrode.

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