JPH0493036A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To disperse a current route against static electricity from the outside without increasing an area and to enhance the withstand voltage to an electrostatic breakdown by a method wherein contact holes of a source and a drain are not arranged in positions which are symmetric with respect to a line with reference to a gate electrode. CONSTITUTION:An element isolation region on the surface of a p-type silicon substrate 1 is precribed by a field insulating film 2; gate electrodes 4 are formed in the element isolation region via a gate insulating film 3. A source and a drain of an LDD structure composed of an n<+> layer 7 and an n<-> layer 8 are formed in a self-aligned manner with an insulating film 6 and the gate electrodes 4. A metal silicide layer 5 of titanium silicide or the like is formed on the surface of the source and the drain. Contact holes 10, 10A, 10B, 10C are opened in an interlayer insulating film 9. At an internal gate, the contact hole 10 and the contact hole 10A are arranged so as to be faced with the gate electrode 4, at an input/output buffer part, the contact hole 10B and the contact hole 10C are arranged so as to be faced with the gate electrode 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a MOS transistor in which a metal silicide layer is formed on the surface of a diffusion layer.

[Conventional technology]

2. Description of the Related Art As semiconductor integrated circuit devices become more highly integrated, device miniaturization is rapidly progressing. The reduction of the device is performed not only in the horizontal direction but also in the vertical direction. For this reason,
The problem has become serious that the layer resistance of the source, drain, and diffusion layer of the MO8+- transistor increases rapidly, and the operating speed of the circuit decreases significantly.

Therefore, in recent years, a method of forming a metal silicide layer with low layer resistance on the surfaces of the source, drain, and diffusion layers has been proposed, for example, by C. C. Lau et al. in 1982. Sl-
, 7], pages 4-717 (C., Lau e
tal:IEDM Tech, Dig,, pp7]
4-717.1982). Silicidation of the source and drain surfaces is effective in improving device characteristics because the layer resistance can be reduced from the conventional several tens to hundreds of ohms/hole to several ohms/hole.

[Problem to be solved by the invention]

However, there is a problem that the resistance to electrostatic discharge damage in MOS devices in which silicide is applied to the diffusion layers such as the source and drain described above is lower than that in the case where silicide is not applied to the diffusion layers.・Cheno
Rayo Ri, 1.986 I.E.D.
M Technical Tijes l-, pages 484-487 (K, L, Chen et aIEDM Te
ch, Dig, pP484-487.1986).

The reason for this is that because the layer resistance of the metal silicide layer is low, current due to static electricity from the outside concentrates from the interface between the silicide and the semiconductor substrate to the end of the gate electrode, and local heat generation in this area causes p-n This is thought to be because thermal breakdown of the bond is likely to occur.

Therefore, in a semiconductor integrated circuit, especially an input/output halafah of an MO3 type integrated circuit, the electrostatic breakdown resistance of the MOS (MOS) transistor constituting the protection circuit is reduced, which poses an important problem in terms of device reliability.

In order to improve the resistance to electrostatic damage as described above, it is necessary to alleviate the concentration of electrostatic discharge current and to lower the discharge current density. This includes the MOS of the input/output protection section.
It is conceivable to widen the gate width of the transistor and space the contact hole from the I electrode, but this would result in a significant increase in the area of the input/output protection section, which is unrealistic.

[Means to solve the problem]

A semiconductor integrated circuit device of the present invention has a gate electrode formed on a semiconductor substrate via a gate insulating film, and a source and a drain formed in self-alignment with the gate electrode, and In a semiconductor integrated circuit device in which a metal silicide layer is formed on the surface of the drain and on the surface of the diffusion layer, holes to the source and drain contacts 1 of the transistor having the metal silicide layer are formed at least in the input/output circuit section of the transistor. It is arranged at a position that is not line symmetrical with respect to the gate electrode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan view showing a part of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along line AA″ in FIG.

An element isolation region is defined on the surface of the p-type silicon substrate 1 by a field insulating film 2, and a gate electrode 4 is formed in the element region on the surface of the p-type silicon substrate 1 via a gate insulating film 3. In this embodiment, the gate electrode 4 has a laminated structure (polycide structure) of, for example, a tungsten silicide film 4a and a polycrystalline silicon film 4a. Insulating film (side wall)6. For example, the n+ layer 7. An LDDI source and drain consisting of an n-layer 8 are formed. A metal silicide layer 5, such as titanium silicide, is formed on the surfaces of the source and drain. Contact holes 10 are formed in the interlayer insulating film 9 for electrical connection to the metal silicide layer 5. l0A10B, IOC is opened. 1st
As shown in Figure (a), in the internal gate (internal circuit), a contact hole 10 and a contact hole 10A are arranged opposite to the gate electrode 4. On the other hand, in a part of the crowd buffer, for example, a contact hole], OB, and a contact hole 10C are arranged so as not to be line-symmetrical with respect to the gate electrode 4.

FIG. 2 is a plan view showing a portion of a semiconductor integrated circuit device according to a second embodiment of the present invention. In this embodiment, the contact hole 10B10C of a part of the input/output buffer is connected to the gate electrode 4.
They are arranged at points symmetrical positions with respect to each other. Therefore, the effect of current dispersion is large. Similarly, for the internal gate, contact hole 10. IOA to gate electrode 4
Since the inner gates are not placed in line-symmetrical positions with respect to each other, the internal gates also have enhanced resistance to electrostatic discharge damage.

Incidentally, FIG. 3 shows an example of measurement results of the on-current of a transistor with various contact hole arrangements in a MOS transistor in which a metal silicide layer is not formed on the source and drain.

From this measurement result, there is a concern that the on-current will decrease with the arrangement of the contact holes of the present invention. However, this decrease in on-current is due to the layer resistance of the source and drain, and this concern can be resolved by keeping the layer resistance low.

〔Effect of the invention〕

As explained above, the present invention provides a MOS transistor having a low resistance metal silicide layer on the source and drain;
In particular, in transistors in the input/output circuit section, by not arranging the source and drain contact holes in a line-symmetrical position with respect to the gate electrode, the current path for external static electricity can be distributed without increasing the area. , This is effective in improving resistance to electrostatic discharge damage.

FIG. 3 is a plan view for explaining the second embodiment of the present invention, and a characteristic diagram for explaining the present invention in detail.

1...p-type silicon substrate, 2...field insulating film, 4
・・・Coo 1~Electrode, 5...Metal silicide 1~Sensitivity, 10
, IOA, IOB, IOC/contact hole.

Claims (1)

[Claims] 1. A gate electrode formed on a semiconductor substrate via a gate insulating film, and a source and a drain formed in self-alignment with the gate electrode, the source and drain In a semiconductor integrated circuit device in which a metal silicide layer is formed on a surface and a surface of a diffusion layer, contact holes for the source and drain of the transistor having the metal silicide layer are line symmetrical with respect to the gate electrode of the transistor. A semiconductor integrated circuit characterized in that it is arranged in a position that does not 2. The semiconductor integrated circuit device according to claim 1, wherein the transistor is a transistor constituting an input/output circuit.