JP3453776B2 - Active matrix substrate manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (TFT).
and an active matrix substrate with a built-in peripheral circuit formed by an anistor) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a TFT using a polycrystalline silicon film
Has been used for an active matrix substrate with a built-in peripheral circuit, taking advantage of its good electrical characteristics. In particular, for a small liquid crystal panel for a viewfinder or the like, an active matrix substrate with a built-in peripheral circuit is indispensable because of mounting problems related to fine pitch terminal connection.
On the other hand, the polycrystalline silicon TFT has a relatively large off-current, and it is difficult to retain the electric charge written in the pixel electrode.
Therefore, various measures have been taken to secure the display quality of the panel. As a means for this, attention has recently been paid to an offset gate structure and an LDD (Lightly Dope).
dDrain) structure TFT. Both structures are basically common in that there is a small distance between the gate electrode and the high-concentration impurity regions forming the source / drain regions. These structures can alleviate the concentration of the electric field at the drain end due to the distance, so that the off current can be reduced to a sufficient level.

[0003]

In order to form an offset gate structure or an LDD structure, some distance is required between the gate electrode and the high concentration impurity region forming the source / drain regions as described above. However, the manufacturing method becomes a problem. Since the diffusion coefficient of impurities in polycrystalline silicon is large in the polycrystalline silicon TFT, the distance is preferably about 1 to 2 μm. An overetch method is generally used as a method for obtaining such a distance. For example,
The gate electrode is etched using the resist as a mask, then high-concentration impurity ion implantation is performed to form the source / drain using the gate electrode and the resist as a mask, and then the gate electrode is overetched using the resist as a mask. The high-concentration impurity regions of the source / drain are basically determined by the mask at the time of ion implantation. To be precise, the high-concentration impurity region is enlarged by about 1 μm due to diffusion by the heat treatment for activation performed after the ion implantation. However, an offset structure can be formed by making the amount of overetching of the gate electrode sufficiently large in consideration of the diffusion. Further, the LDD structure can be obtained by removing the resist after over-etching and then implanting impurity ions of low concentration using the gate electrode as a mask.

However, in forming the above-mentioned offset structure and LDD structure by overetching, it is difficult to control the channel length accurately. For example,
When the gate electrode material is polycrystalline silicon, etching is usually performed by plasma etching. With standard etching, the end point of etching can be known from the change in the emission intensity of plasma, but with overetching, the etching has already been completed, and the end point of overetching cannot be known from the change in the emission intensity of plasma. . In addition, the etching rate of the etching apparatus slightly changes depending on the usage conditions, and it is difficult to control the overetch amount with high accuracy. The variation in the width of the gate electrode, that is, the gate length and the offset length causes variation in the electrical characteristics of the TFT. In particular, the ON current of the TFT largely depends on these lengths.

In the CMOS type active matrix substrate with a built-in peripheral circuit, there are three types of TFTs: a P-channel type TFT and an N-channel type TFT which form a peripheral circuit, and an N-channel type TFT which forms a pixel TFT.
It is the pixel TFT that wants to control the off-current, and there is a general demand that the TFT that constitutes the peripheral circuit has a large on-current and uniform characteristics. Standard T
In the manufacturing process of the FT, the above-mentioned three types of TFTs are also over-etched, which causes variations in TFT characteristics as described above.

FIG. 2 is a TFT sectional view showing a process of manufacturing a pixel TFT with a standard offset structure in a conventional active matrix substrate. Figure 2
In, the above three types of TFTs are formed on the insulating substrate. Reference numerals 206, 208, and 210 denote semiconductor layers serving as sources, drains, and channels of N-channel type pixel TFTs, N-channel type TFTs and P-channel type TFTs constituting peripheral circuits, respectively. In FIG. 2A, the gate insulating film 2
After forming 11, the gate electrode 212 is used as a resist mask 2
Patterning with No. 13 and leaving the resist as N
High-concentration phosphorus ion implantation 214 is performed to form the source / drain of the channel TFT. Next, as shown in FIG. 2B, the gate electrode 212 is overetched by 1 to 2 μm on one side using the resist 213 as a mask.
A, 212B and 212C are obtained. The gate electrode size in the pattern design is reflected on the gate electrode 212 shown in FIG. 2A, but the final gate electrode size is the above-mentioned 212.
It will be decided by A, 212B, 212C. That is,
The size of the gate electrode depends on the amount of overetch. The problem here is that the above-mentioned over-etching cannot detect the etching end point as described above, so that the over-etching amount varies, and hence the gate size may vary. Next, after removing the unnecessary resist 213 in FIG. 2C, two types of N-channel TFTs are masked with a resist 215, and high-concentration boron ions for forming the source / drain of the P-channel TFT are formed. Implanting 216 is performed. If the amount of boron ions is larger than the amount of phosphorus ions, a P-type source 209 and drain 209 'can be formed in 210. In the steps up to this point, the N-channel type TFT which constitutes the pixel and the peripheral circuit becomes the offset gate type TFT, and the P-channel type TFT becomes the standard self-alignment type TFT. Pixel TFT can obtain desired low off current,
Since the N-channel TFT that constitutes the peripheral circuit has an offset gate structure, a sufficient on-current may not be obtained in some cases. In this case, following FIG. 2C, the unnecessary resist 215 is removed, the pixel TFT and the P-channel TFT are masked with resist, and phosphorus ion implantation is performed to form the peripheral circuit N-channel TFT. Can be a standard self-aligned TFT. Also,
If the pixel TFT is to have an LDD structure, the unnecessary resist may be removed and phosphorus ion implantation with a relatively low concentration may be performed.

As described above, according to the conventional technique, the gate of the TFT constituting the peripheral circuit of the active matrix substrate is also over-etched, so that the variation in the electric characteristics of the TFT cannot be avoided. There is also a problem that the size of the TFT pattern design must be determined in consideration of the gate overetch.

Therefore, the object of the present invention is to solve the above-mentioned problems, to make the off current of the pixel TFT sufficiently low, and for the TFT constituting the peripheral circuit, the active matrix substrate and its manufacture in which uniform electric characteristics can be obtained. To propose a method.

[0009]

A method of manufacturing an active matrix substrate according to the present invention comprises a step of forming a silicon thin film on an insulating substrate, a step of forming a gate insulating film, an N channel type which constitutes a pixel TFT, Steps of forming gate electrodes of N-channel type and P-channel type TFTs forming a peripheral circuit, and N-channel type and P-channel type forming the peripheral circuit while leaving a resist for forming the gate electrode A step of forming a resist on the area where the TFT is to be formed, and using the gate electrode of the pixel TFT and the resist left thereon as a mask, high-concentration N-type impurity ion implantation is performed to perform the source / drain of the pixel TFT. And the resist left on the gate electrode of the pixel TFT is used to cover the gate electrode of the pixel TFT. And shortening the gate length of the pixel TFT, and the resist left on the gate electrode of the pixel TFT and the resist on the N-channel type and P-channel type TFT forming planned regions forming the peripheral circuit. And a source / drain of the N-channel type TFT forming the peripheral circuit by performing high-concentration N-type impurity ion implantation using the gate electrode of the N-channel type TFT forming the peripheral circuit as a mask. And the source / drain of the P-channel type TFT forming the peripheral circuit is formed by ion-implanting a high-concentration P-type impurity using the gate electrode of the P-channel type TFT forming the peripheral circuit as a mask. And a forming step.

Further, in the method for manufacturing an active matrix substrate of the present invention, a step of forming a silicon thin film on the insulating substrate, a step of forming a gate insulating film, and a pixel TFT.
Forming the gate electrodes of N-channel type TFTs forming the N-channel type and peripheral circuits forming the N-channel type and the P-channel type TFTs forming the peripheral circuit, and forming the peripheral circuits while leaving the resist for forming the gate electrodes. A step of forming a resist on the N-channel type and P-channel type TFT formation planned regions, and ion implantation of high-concentration N-type impurities using the gate electrode of the pixel TFT and the resist left thereon as a mask are performed. Forming the source / drain of the pixel TFT; and using the resist left on the gate electrode of the pixel TFT to overetch the gate electrode of the pixel TFT to shorten the gate length of the pixel TFT. , N-channel type and P which constitute the peripheral circuit and the resist left on the gate electrode of the pixel TFT
Step of removing the resist on the area where the channel type TFT is to be formed, and N channel type TF which constitutes the peripheral circuit
High-concentration N-type impurity is ion-implanted by using the gate electrode of T as a mask to form the source / drain of the N-channel type TFT which constitutes the peripheral circuit, and the P-channel type TFT which constitutes the peripheral circuit. P-channel TFT for forming the peripheral circuit by performing ion implantation of high-concentration P-type impurities using the gate electrode of
LDD of the pixel TFT by performing the step of forming source / drain of
And a step of forming a region.

The active matrix substrate of the present invention is
In an active matrix substrate with a built-in peripheral circuit formed on an insulating substrate, the pixel TFT is an offset or LDD type N-channel TFT, and the N-channel TFT and the P-channel TFT forming the peripheral circuit are self-aligned type. It is characterized by being composed of a TFT.
As described above, the pixel TFT is an offset type or LDD
With the structure, the leak current of the pixel TFT can be reduced, so that the retention characteristic of the charges written in the pixel electrode is improved. Further, while the pixel TFT has an offset type or LDD structure, it has a TF that constitutes a peripheral circuit.
Since T can have a standard self-aligned structure, the peripheral circuits can operate at high speed.

[0012]

EXAMPLES The present invention will be described below based on examples. FIG. 1 is an embodiment of the present invention and shows a cross-sectional view of three types of TFTs constituting an active matrix substrate. Since the point of the present invention is the relative positional relationship of the source, drain, channel, and gate of the TFT, the cross-sectional view of the TFT shown in this embodiment shows only these element parts. In FIG. 1, there are three types of TFTs on a transparent insulating substrate 101, TFT-A is a pixel TFT, N-channel type TFT is an offset gate type, and TFT-B and TFT-C form a peripheral circuit of an active matrix substrate. These TFTs are a non-offset gate N-channel TFT and a P-channel TFT, respectively. The TFT-A is composed of the source / drain of the N ⁺ high concentration impurity regions 105 and 105 ′, the channel region 106, the gate insulating film 111, and the gate electrode 112. The length of the channel region 106 is the gate electrode 11
It is longer than the width of 2 and forms a so-called offset gate structure. T
FT-B is a non-offset gate structure, that is, a standard self-aligned N-channel TFT, 107,
107 'is the source / drain of the N ⁺ high concentration impurity region,
The TFT-C is a standard P-channel TFT having a self-aligned structure, and 109 and 109 ′ are the source / drain of the P ⁺ high concentration impurity region. Since the pixel TFT-A is an offset gate type TFT, the off current is small, and the TFT-B and the TFT-C forming the peripheral circuit have a standard self-aligned structure and a large on current can be obtained. That is, the charges written in the pixel electrodes are sufficiently retained, and the peripheral circuits can operate at high speed. Further, as will be described later in detail, the TF according to the present invention which constitutes a peripheral circuit.
Since T can be processed by a method capable of detecting the etching end point in forming the gate electrode, T has excellent uniformity in electrical characteristics. Therefore, the active matrix substrate composed of such TFTs enables high definition and high quality liquid crystal display.

Next, a method of manufacturing the active matrix substrate of the present invention will be described based on the embodiment shown in FIG. Figure 3
In (a), reference numerals 306, 308, and 310 denote semiconductor layers serving as sources, drains, and channels of N-channel type pixel TFTs, N-channel type TFTs and P-channel type TFTs constituting peripheral circuits, respectively. After forming the channel layer, a gate insulating film 311 is formed, a gate electrode material is then deposited, and the gate electrode 312 is photoetched. If the gate electrode material is polycrystalline silicon, the etching is dry etching using CF ₄ plasma.
It is possible to confirm the etching end point and precisely control the dimensions. Next, as shown in FIG. 3B, while leaving the resist 313 whose gate electrode is etched, the TFTs constituting the peripheral circuit are masked with another resist 315, and the source / source of the N-channel type TFT which is a pixel TFT is masked. High-concentration phosphorus ion implantation 314 for forming the drain is performed. Next, as shown in FIG. 3C, the resists 313 and 31 are formed.
Using 5 as a mask, the gate electrode is overetched by 1 to 2 μm on each side to obtain a gate electrode 312A. At this time, since the TFTs forming the peripheral circuit are masked by the resist 315, the gate size that determines the channel length of these TFTs is not affected by any influence. Therefore, the gate size is accurately determined by the etching shown in FIG. On the other hand, the gate of the pixel TFT has an offset structure due to the size reduction due to the overetching. Next, after removing the unnecessary resists 313 and 315 in FIG. 4A, the N-channel TFT is masked with a resist 317, and high-concentration boron ion implantation for forming the source / drain of the P-channel TFT is performed. Perform 318. Next, as shown in FIG. 4B, the unnecessary resist 31 is removed.
7 is removed, a new resist 319 is used to mask the pixel channel and the P-channel type TFT forming the peripheral circuit, and the source 307 and drain 307 ′ of the N-channel type TFT forming the peripheral circuit are formed by high-concentration phosphorus ion implantation 320.
To form. In the steps up to this point, the pixel TFT becomes an offset gate type TFT, and N forming the peripheral circuit is formed.
The channel type TFT and the P channel type TFT are standard self-aligned type TFTs. Furthermore, the pixel TFT is L
When it is desired to form a DD structure, the unnecessary resist 319 may be removed following FIG. 4B, and then phosphorus ions may be implanted at a relatively low concentration.

[0014]

As described above, according to the present invention, the pixel TFT has an offset structure and the TF which constitutes the peripheral circuit.
Since T can have a standard self-alignment structure, the charges written in the pixel electrode are sufficiently retained and the peripheral circuit can operate at high speed. Further, since the gate length of the TFTs forming the peripheral circuit can be uniformly determined to a value reflecting the pattern design value with high accuracy, it is possible to obtain a TFT having excellent uniformity of electrical characteristics. Therefore, the active matrix substrate composed of such TFTs enables high definition and high quality liquid crystal display.

[Brief description of drawings]

FIG. 1 is a sectional view of a TFT constituting an active matrix substrate according to the present invention.

FIG. 2 is a sectional view showing a method for manufacturing an active matrix substrate according to a conventional technique.

FIG. 3 is a first sectional view showing a method for manufacturing an active matrix substrate according to the present invention.

FIG. 4 is a second cross-sectional view showing the method of manufacturing the active matrix substrate according to the present invention.

[Explanation of symbols]

101,201,301 Glass substrate 105,107,109,205,207,209,305,307,309 Source, drain 111,211,311 Gate insulating film 112,212,312 Gate electrode 213,215,313,315,317,319 Photoresist

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 H01L 29/78

Claims (2)

(57) [Claims] 1. A step of forming a silicon thin film on an insulating substrate, a step of forming a gate insulating film, and N-channel type TFTs forming a pixel TFT, and N-channel type and P-channel type TFTs forming a peripheral circuit. Forming a gate electrode; forming a resist on the N-channel type and P-channel type TFT formation planned regions forming the peripheral circuit while leaving the resist for forming the gate electrode; A step of forming a source / drain of the pixel TFT by performing high-concentration N-type impurity ion implantation using the gate electrode of the pixel TFT and the resist left thereon as a mask, and leaving the gate electrode of the pixel TFT on the gate electrode. Over-etching the gate electrode of the pixel TFT by using the formed resist to shorten the gate length of the pixel TFT, and the pixel TF. A step of removing the resist left on the gate electrode of T and the resist on the N-channel type and P-channel type TFT forming planned regions forming the peripheral circuit, and the step of removing the N-channel type TFT forming the peripheral circuit. A high concentration N-type impurity is ion-implanted using the gate electrode as a mask to form the source / drain of the N-channel type TFT configuring the peripheral circuit, and the gate of the P-channel type TFT configuring the peripheral circuit. Forming a source / drain of a P-channel type TFT constituting the peripheral circuit by ion-implanting high-concentration P-type impurities using the electrodes as a mask. . 2. A step of forming a silicon thin film on an insulating substrate, a step of forming a gate insulating film, and N-channel type TFTs forming a pixel TFT, and N-channel type and P-channel type TFTs forming a peripheral circuit. Forming a gate electrode; forming a resist on the N-channel type and P-channel type TFT formation planned regions forming the peripheral circuit while leaving the resist for forming the gate electrode; A step of forming a source / drain of the pixel TFT by performing high-concentration N-type impurity ion implantation using the gate electrode of the pixel TFT and the resist left thereon as a mask, and leaving the gate electrode of the pixel TFT on the gate electrode. Over-etching the gate electrode of the pixel TFT by using the formed resist to shorten the gate length of the pixel TFT, and the pixel TF. A step of removing the resist left on the gate electrode of T and the resist on the N-channel type and P-channel type TFT forming planned regions forming the peripheral circuit, and the step of removing the N-channel type TFT forming the peripheral circuit. A high concentration N-type impurity is ion-implanted using the gate electrode as a mask to form the source / drain of the N-channel type TFT configuring the peripheral circuit, and the gate of the P-channel type TFT configuring the peripheral circuit. High-concentration P-type impurity is ion-implanted by using the electrode as a mask to form the source / drain of the P-channel TFT forming the peripheral circuit, and low-concentration N-type impurity is ion-implanted. And a step of forming an LDD region of the pixel TFT, the method of manufacturing an active matrix substrate.