CN115000179A - Thin film transistor, manufacturing method thereof and display panel - Google Patents

Thin film transistor, manufacturing method thereof and display panel Download PDF

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Publication number
CN115000179A
CN115000179A CN202210717810.3A CN202210717810A CN115000179A CN 115000179 A CN115000179 A CN 115000179A CN 202210717810 A CN202210717810 A CN 202210717810A CN 115000179 A CN115000179 A CN 115000179A
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channel
amorphous silicon
doped
thin film
film transistor
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刘念
卢马才
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TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application provides a thin film transistor and a manufacturing method thereof, and a display panel, wherein the thin film transistor comprises: a channel portion; the two doping parts are arranged at intervals and are respectively positioned on two opposite sides of the channel part, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part; the grid is positioned on one side of the channel part and is arranged corresponding to the channel part; a first electrode contacting one of the doped portions; and a second electrode spaced apart from the first electrode, the second electrode being in contact with the other doped portion.

Description

Thin film transistor, manufacturing method thereof and display panel
Technical Field
The present application relates to the field of display technologies, and in particular, to a thin film transistor, a manufacturing method thereof, and a display panel.
Background
The low temperature polysilicon thin film transistor has the advantages of high mobility and good stability, so that the low temperature polysilicon thin film transistor is widely applied to small-size display. However, the off-state leakage current of the LTPS TFT greatly affects the display effect.
Therefore, it is necessary to provide a solution to reduce the off-state leakage current of the ltps tft.
Disclosure of Invention
An object of the present application is to provide a thin film transistor, a method for manufacturing the same, and a display panel, so as to reduce off-state leakage current of the thin film transistor, thereby facilitating improvement of display effect of the display panel.
In order to realize the purpose, the technical scheme is as follows:
a thin film transistor, comprising:
a channel portion;
the two doping parts are respectively positioned at two opposite sides of the channel part, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part;
the grid electrode is positioned on one side of the channel part and is arranged corresponding to the channel part;
a first electrode in contact with one of the doped portions; and
and the second electrode is arranged at a distance from the first electrode and is in contact with the other doped part.
In the thin film transistor of some embodiments, the first electrode and the second electrode are located at different film layers from the channel portion, the lightly doped portion is located at a side of the heavily doped portion away from the first electrode and the second electrode, the first electrode is in contact with the heavily doped portion of one of the doped portions, and the second electrode is in contact with the heavily doped portion of the other of the doped portions.
In the thin film transistor of some embodiments, a step is formed between the heavily doped portion and the lightly doped portion, and a portion of the channel extends along the step and is in contact with the heavily doped portion and the lightly doped portion.
In the thin film transistor of some embodiments, the first electrode and the second electrode are located at different film layers from the channel portion, and the lightly doped portion extends from a side of the heavily doped portion near the channel portion to a surface of the heavily doped portion near the first electrode and the second electrode.
In the thin film transistor of some embodiments, the gate electrode overlaps the lightly doped portion, and the gate electrode does not overlap the heavily doped portion.
In the thin film transistor of some embodiments, the gate overlaps both the lightly doped portion and the heavily doped portion.
In the thin film transistor of some embodiments, a thickness of the lightly doped portion is greater than or equal to 10 micrometers and less than or equal to 40 micrometers, a thickness of the heavily doped portion is greater than or equal to 10 micrometers and less than or equal to 40 micrometers, and a thickness of the channel portion is greater than or equal to 40 micrometers and less than or equal to 60 micrometers.
A method of manufacturing a thin film transistor, the method comprising:
forming two doping parts arranged at intervals and a channel part, wherein the channel part is positioned between the two doping parts, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part;
forming a gate on one side of the channel part, wherein the gate is arranged corresponding to the channel part;
and forming a first electrode and a second electrode on one side of the channel part, wherein the first electrode is in contact with one doped part, and the second electrode is in contact with the other doped part.
In some embodiments, the method for manufacturing a thin film transistor includes the steps of:
forming an amorphous silicon lightly doped layer and an amorphous silicon heavily doped layer which are sequentially superposed;
patterning the amorphous silicon light-doped layer and the amorphous silicon heavy-doped layer by adopting a first composition process to obtain an amorphous silicon light-doped pattern and an amorphous silicon heavy-doped pattern positioned on the amorphous silicon light-doped pattern, wherein the amorphous silicon light-doped pattern extends outwards relative to the amorphous silicon heavy-doped pattern;
forming an amorphous silicon channel layer covering the amorphous silicon light-doped patterns and the amorphous silicon heavy-doped patterns, and patterning the amorphous silicon channel layer by adopting a second composition process to obtain amorphous silicon channel patterns, wherein the amorphous silicon channel patterns are positioned between two adjacent amorphous silicon light-doped patterns and are in contact with the amorphous silicon light-doped patterns and the amorphous silicon heavy-doped patterns;
and carrying out crystallization treatment on the amorphous silicon lightly doped pattern, the amorphous silicon heavily doped pattern and the amorphous silicon channel pattern, wherein the amorphous silicon lightly doped pattern is crystallized to form the lightly doped part, the amorphous silicon heavily doped pattern is crystallized to form the heavily doped part, and the amorphous silicon channel pattern is crystallized to form the channel part.
A display panel, the display panel comprising:
the above thin film transistor; and
and the light-emitting unit is electrically connected with the thin film transistor.
Has the advantages that: the application provides a thin film transistor and a manufacturing method thereof, and a display panel, wherein two doping parts arranged at intervals are respectively positioned at two opposite sides of a channel part, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part to weaken a leakage field when the thin film transistor is in a closed state, so that the leakage current when the thin film transistor is in the closed state is reduced, the improvement of a thermal electron annealing effect is facilitated, and the stability of the thin film transistor is further improved. In addition, at least part of the light doping part is overlapped with the heavy doping part, so that the light doping part and the heavy doping part can be prepared by patterning different film layers, ion implantation equipment is not needed for doping and preparing the light doping part and the heavy doping part, and the manufacturing cost of the thin film transistor is reduced.
Drawings
Fig. 1 is a schematic view of a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart illustrating a process of manufacturing a thin film transistor array substrate according to an embodiment of the present disclosure;
FIGS. 3A-3J are schematic views illustrating a process of fabricating a thin film transistor array substrate according to an embodiment of the present application;
fig. 4 is a schematic view of a thin film transistor array substrate according to another embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic view of a thin film transistor array substrate according to an embodiment of the present application. The thin film transistor array substrate 100 includes a substrate 10 and a thin film transistor 11 disposed on the substrate 10, and a buffer layer 12 is disposed between the thin film transistor 11 and the substrate 10.
The substrate 10 is a glass substrate. It will be appreciated that the substrate 10 may also be a flexible substrate.
The buffer layer 12 is made of at least one material selected from silicon nitride and silicon oxide. The buffer layer 12 has a thickness of 2000 angstroms or more and 4000 angstroms or less.
The thin film transistor 11 includes a channel portion 111, two doping portions 112 arranged at intervals, a gate insulating layer 113, a gate electrode 114, an interlayer insulating layer 115, a first electrode 1161, and a second electrode 1162.
The two doped portions 112 are respectively located at two opposite sides of the channel portion 111, at least one doped portion 112 includes a lightly doped portion 1121 and a heavily doped portion 1122, at least a portion of the lightly doped portion 1121 overlaps the heavily doped portion 1122, the lightly doped portion 1121 extends toward the channel portion 111 relative to the heavily doped portion 1122, and the lightly doped portion 1121 contacts the channel portion 111, so that a leakage field when the thin film transistor 11 is in an off state is reduced, and further a leakage current when the thin film transistor 11 is in the off state is reduced.
Specifically, the two doped portions 112 each include a lightly doped portion 1121 and a heavily doped portion 1122, the lightly doped portion 1121 is located on the buffer layer 12, the heavily doped portion 1122 is located on a surface of the lightly doped portion 1121 away from the buffer layer 12, the lightly doped portion 1121 extends outward relative to the heavily doped portion 1122, and a step L is formed between the heavily doped portion 1122 and the lightly doped portion 1121.
The heavily doped portion 1122 in one of the doped portions 112 serves as a source contact portion, the heavily doped portion 1122 in the other doped portion 112 serves as a drain contact portion, the lightly doped portion 1121 and the heavily doped portion 1122 are made of polysilicon, the lightly doped portion 1121 and the heavily doped portion 1122 are formed of amorphous silicon doped with phosphorus ions or arsenic ions, the ion-doped amorphous silicon is crystallized to obtain ion-doped polysilicon, and the doping concentration of the ions in the lightly doped portion 1121 is less than that of the ions in the heavily doped portion 1122.
The lightly doped portions 1121 have a thickness of greater than or equal to 10 micrometers and less than or equal to 40 micrometers, and the heavily doped portions 1122 have a thickness of greater than or equal to 10 micrometers and less than or equal to 40 micrometers. For example, the thickness of the lightly doped portion 1121 is 15 micrometers, 20 micrometers, 30 micrometers, or 40 micrometers. The heavily doped portions 1122 have a thickness of 15 microns, 20 microns, 30 microns, or 40 microns.
A portion of the channel portion 111 is located between two spaced apart doped portions 112, and another portion of the channel portion 111 extends along the step L and is in contact with the heavily doped portion 1122 and the lightly doped portion 1121, i.e., the channel portion 111 overlaps the doped portions 112.
The channel portion 111 is made of polysilicon, and the thickness of the channel portion 111 is greater than or equal to 40 micrometers and less than or equal to 60 micrometers. For example, the thickness of the channel portion 111 is 45 micrometers, 50 micrometers, 55 micrometers, or 60 micrometers.
The gate insulating layer 113 covers the two doped portions 112, the channel portion 111, and the buffer layer 12. The gate insulating layer 113 is made of a material selected from at least one of silicon nitride and silicon oxide. The thickness of the gate insulating layer 113 is greater than or equal to 1000 angstroms and less than or equal to 1500 angstroms.
The gate 114 is located at one side of the channel portion 111, the gate 114 is disposed corresponding to the channel portion 111, the gate 114 overlaps the lightly doped portion 1121, the gate 114 does not overlap the heavily doped portion 1122, so as to ensure that more portions of the gate 114 and the channel portion 111 overlap, and more portions of the channel portion 111 are controlled by the gate 114, so that a current is prevented from being small when the thin film transistor 11 is in an on state, and at the same time, a parasitic capacitance between the heavily doped portion 1122 and the gate 114 is prevented from being too large. The gate 114 is made of at least one material selected from molybdenum, aluminum, titanium, copper, and silver. The thickness of the gate 114 is greater than or equal to 2500 angstroms and less than or equal to 4000 angstroms.
It can be understood that the gate 114 and the lightly doped portion 1121 may overlap with each other, and the gate 114 and the heavily doped portion 1122 also overlap with each other, so that in the case that the contact portion between the channel portion 111 and the lightly doped portion 1121 is smaller, the situation that the contact portion between the channel portion 111 and the lightly doped portion 1121 cannot overlap with the gate 114 due to process variations is avoided, and further, the current is smaller when the thin film transistor 11 is in the on state is avoided.
Specifically, the gate electrode 114 is disposed on a surface of the gate insulating layer 113 away from the substrate 10, and is disposed corresponding to the channel portion 111.
The interlayer insulating layer 115 covers the gate electrode 114 and the gate insulating layer 113. The material for forming the interlayer insulating layer 115 is selected from at least one of silicon nitride and silicon oxide. The thickness of the interlayer insulating layer 115 is 2000 angstroms or more and 5000 angstroms or less.
One of the first electrode 1161 and the second electrode 1162 is a source, and the other of the first electrode 1161 and the second electrode 1162 is a drain. The first electrode 1161 and the second electrode 1162 are made of at least one material selected from molybdenum, aluminum, titanium, copper, and silver. The thickness of the first electrode 1161 and the second electrode 1162 is greater than or equal to 4000 angstroms and less than or equal to 8000 angstroms.
The first electrode 1161 and the second electrode 1162 are located in different film layers from the channel portion 111, the first electrode 1161 and the second electrode 1162 are disposed at the same layer and at intervals, the lightly doped portion 1121 is located at one side of the heavily doped portion 1122 away from the first electrode 1161 and the second electrode 1162, the first electrode 1161 is in contact with the heavily doped portion 1122 of one doped portion 112, and the second electrode 1162 is in contact with the heavily doped portion 1122 of the other doped portion 112.
Specifically, the first electrode 1161 and the second electrode 1162 are disposed at intervals on a surface of the interlayer insulating layer 115 away from the gate insulating layer 113, the first electrode 1161 is in contact with the heavily doped portion 1122 of one doped portion 112 through a first contact hole 100a penetrating the interlayer insulating layer 115 and the gate insulating layer 113, and the second electrode 1162 is in contact with the heavily doped portion 1122 of the other doped portion 112 through a second contact hole 100b penetrating the interlayer insulating layer 115 and the gate insulating layer 113.
In the thin film transistor of the thin film transistor array substrate, the light doping part is overlapped with the heavy doping part, and the light doping part is contacted with the channel part, so that a leakage electric field when the thin film transistor is in a closed state is reduced, the reduction of the leakage current of the thin film transistor is facilitated, the improvement of a thermal electron annealing effect is facilitated, and the stability of the thin film transistor is improved. In addition, compared with the traditional polycrystalline silicon active layer, the heavily doped part and the lightly doped part are arranged on the same layer and ion doping is realized by adopting ion implantation equipment, the lightly doped part and the heavily doped part in the embodiment are prepared by patterning different film layers, and the lightly doped part and the heavily doped part are not required to be prepared by doping by using the ion implantation equipment, so that the manufacturing cost of the thin film transistor array substrate is reduced.
The thin film transistor 11 shown in fig. 1 is a top gate thin film transistor, and the thin film transistor 11 may be a bottom gate thin film transistor.
Fig. 2 is a schematic flow chart illustrating a process of manufacturing a thin film transistor array substrate according to an embodiment of the present application. The manufacturing method of the thin film transistor array substrate comprises the following steps:
s100: two doping parts and a channel part which are arranged at intervals are formed, one channel part is positioned between the two doping parts, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part.
Specifically, first, a substrate 10 is provided, a buffer layer 12 is disposed on the substrate 10, and an amorphous silicon lightly doped layer 131 and an amorphous silicon heavily doped layer 132 are sequentially formed on the buffer layer 12 by chemical vapor deposition, as shown in fig. 3A.
Then, a first photoresist layer is coated on the amorphous silicon heavily doped layer 132, the first photoresist layer is sequentially subjected to exposure through a first photomask and development through a first developing solution to obtain two first photoresist patterns 141 arranged at intervals, and the amorphous silicon lightly doped layer 131 and the amorphous silicon heavily doped layer 132 which are not covered by the first photoresist patterns 141 are etched to obtain an amorphous silicon lightly doped pattern 1311 and a first amorphous silicon heavily doped pattern 1321 located on the amorphous silicon lightly doped pattern 1311, as shown in fig. 3B.
Next, the first photoresist pattern 141 is subjected to ashing treatment using oxygen gas, to obtain a second photoresist pattern 142, and the area and height of the second photoresist pattern 142 are both reduced with respect to the first photoresist pattern 141, as shown in fig. 3C.
Next, the first amorphous silicon heavily doped pattern 1321 uncovered by the second photoresist pattern 142 is etched, and the remaining second photoresist pattern 142 is removed to obtain a second amorphous silicon heavily doped pattern 1322, wherein the amorphous silicon lightly doped pattern 1311 extends outward relative to the second amorphous silicon heavily doped pattern 1322 and a step L is formed therebetween, as shown in fig. 3D.
Next, an amorphous silicon channel layer 15 covering the second amorphous silicon heavily doped pattern 1322, the amorphous silicon lightly doped pattern 1311, and the buffer layer 12 is formed, as shown in fig. 3E; and forming a second photoresist layer on the amorphous silicon channel layer 15, exposing the second photoresist layer through a second photomask and treating the second photoresist layer with a second developing solution, etching the amorphous silicon channel layer 15 uncovered by the developed second photoresist layer, and removing the remaining second photoresist layer to obtain an amorphous silicon channel pattern 151, wherein a part of the amorphous silicon channel pattern 151 is located between two adjacent amorphous silicon lightly doped patterns 1311, and another part of the amorphous silicon channel pattern 151 extends along the step L and is in contact with the amorphous silicon lightly doped pattern 1311 and the second amorphous silicon heavily doped pattern 1322, as shown in fig. 3F.
Finally, the amorphous silicon lightly doped pattern 1311, the second amorphous silicon heavily doped pattern 1322, and the amorphous silicon channel pattern 151 are crystallized, the amorphous silicon lightly doped pattern 1311 is crystallized into the lightly doped portions 1121, the second amorphous silicon heavily doped pattern 1322 is crystallized into the heavily doped portions 1122, the amorphous silicon channel pattern 151 is crystallized into the channel portions 111, one lightly doped portion 1121 and the heavily doped portion 1122 on one lightly doped portion 1121 constitute one doped portion 112, a portion of the channel portion 111 is located between two adjacent lightly doped portions 1121, and the other portion of the channel portion 111 is in contact with the lightly doped portions 1121 and the heavily doped portions 1122 along the step L, as shown in fig. 3G.
S200: and forming a grid electrode on one side of the channel part, wherein the grid electrode is arranged corresponding to the channel part.
Specifically, a gate insulating layer 113 covering the channel portion 111, the doping portion 112, and the buffer layer 12 is formed; then, a first conductive layer is formed on the surface of the gate insulating layer 113 away from the substrate 10, and the first conductive layer is patterned by a patterning process to obtain a gate 114, where the gate 114 is disposed corresponding to the channel portion 111, as shown in fig. 3H.
S300: and forming a first electrode and a second electrode on one side of the channel part, wherein the first electrode is contacted with one doped part, and the second electrode is contacted with the other doped part.
Specifically, an interlayer insulating layer 115 covering the gate 114 and the gate insulating layer 113 is formed, and after the interlayer insulating layer 115 and the gate insulating layer 113 are subjected to a patterning process, a first contact hole 100a and a second contact hole 100b penetrating through the interlayer insulating layer 115 and the gate insulating layer 113 are obtained, wherein the first contact hole 100a is arranged corresponding to the heavily doped portion 1122 of one doped portion 112, and the second contact hole 100b is arranged corresponding to the heavily doped portion 1122 of the other doped portion 112, as shown in fig. 3I; forming a second conductive layer in the first contact hole 100a and the second contact hole 100b and on the surface of the interlayer insulating layer 115, and patterning the second conductive layer by using a patterning process to obtain a first electrode 1161 and a second electrode 1162, where the first electrode 1161 contacts the heavily doped portion 1122 of one doped portion 112 through the first contact hole 100a, and the second electrode 1162 contacts the heavily doped portion 1122 of the other doped portion 112 through the second contact hole 100b, as shown in fig. 3J.
In the manufacturing method of the thin film transistor array substrate of the embodiment, the lightly doped portion, the heavily doped portion and the channel portion of the doped portion are prepared by chemical deposition, etching process and crystallization, and ion implantation equipment is not required, which is beneficial to reducing the manufacturing cost of the thin film transistor array substrate. In addition, a photomask is used in the manufacturing process of the light doping part and the heavy doping part, which is beneficial to reducing the photomask required by manufacturing the thin film transistor array substrate.
Please refer to fig. 4, which is a schematic diagram of a thin film transistor array substrate according to another embodiment of the present disclosure. The tft array substrate shown in fig. 4 is substantially similar to the tft array substrate shown in fig. 1, and the same parts are not repeated, except that in the tft array substrate shown in fig. 4, the heavily doped portion 1122 is disposed on the buffer layer 12, the lightly doped portion 1121 extends from a side surface of the heavily doped portion 1122 close to the channel portion 111 to a surface of the heavily doped portion 1122 close to the first electrode 1161 and the second electrode 1162, the lightly doped portion 1121 exposes a portion of the heavily doped portion 1122, and the channel portion 111 only contacts the lightly doped portion 1121.
In the thin film transistor of the thin film transistor array substrate, the light doping part extends to the heavy doping part from the side surface of the heavy doping part, and the light doping part is in contact with the channel part, so that a leakage electric field when the thin film transistor is in a closed state is reduced, the reduction of the leakage current of the thin film transistor is facilitated, the improvement of a thermal electron annealing effect is facilitated, the stability of the thin film transistor is improved, and the display effect of the display panel is improved. In addition, the manufacturing process of the heavily doped part, the lightly doped part and the channel part in the thin film transistor array substrate can also be prepared by the chemical deposition, etching and crystallization processes, and ion implantation equipment is not required, so that the manufacturing cost of the thin film transistor array substrate is reduced.
It should be noted that when the manufacturing processes of the heavily doped portion, the lightly doped portion, and the channel portion are prepared by the above chemical deposition, etching, and crystallization processes, the manufacturing processes of the heavily doped portion and the lightly doped portion in the thin film transistor array substrate of this embodiment need to use two independent photomasks respectively.
The application also provides a display panel, which can be one of a liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel and a sub-millimeter light-emitting diode display panel. The display panel comprises the thin film transistor array substrate and a light-emitting unit, wherein the light-emitting unit is electrically connected with the thin film transistor in the thin film transistor array substrate.
In the thin film transistor of the display panel, the light doping part is overlapped with the heavy doping part, and the light doping part is contacted with the channel part, so that a leakage electric field when the thin film transistor is in an off state is reduced, the reduction of the leakage current of the thin film transistor is facilitated, the improvement of a thermal electron annealing effect is facilitated, the stability of the thin film transistor is further improved, and the display effect of the display panel is further improved. In addition, compared with the traditional polycrystalline silicon active layer, the heavily doped part and the lightly doped part are arranged on the same layer and ion doping is realized by adopting ion implantation equipment, the lightly doped part and the heavily doped part in the embodiment can be prepared by patterning different film layers, and the lightly doped part and the heavily doped part are not required to be prepared by doping by using the ion implantation equipment, so that the manufacturing cost of the display panel is reduced.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A thin film transistor, comprising:
a channel portion;
the two doping parts are respectively positioned at two opposite sides of the channel part, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part;
the grid electrode is positioned on one side of the channel part and is arranged corresponding to the channel part;
a first electrode in contact with one of the doped portions; and
and the second electrode is arranged at a distance from the first electrode and is in contact with the other doped part.
2. The thin film transistor of claim 1, wherein the first and second electrodes are on different layers from the channel portion, the lightly doped portion is on a side of the heavily doped portion away from the first and second electrodes, the first electrode is in contact with the heavily doped portion of one of the doped portions, and the second electrode is in contact with the heavily doped portion of the other of the doped portions.
3. The thin film transistor of claim 2, wherein a step is formed between the heavily doped portion and the lightly doped portion, and a portion of the channel extends along the step and contacts the heavily doped portion and the lightly doped portion.
4. The thin film transistor of claim 1, wherein the first and second electrodes are located on different layers from the channel portion, and the lightly doped portion extends from a side of the heavily doped portion near the channel portion to a surface of the heavily doped portion near the first and second electrodes.
5. The thin film transistor of claim 1, wherein the gate overlaps the lightly doped portion and the gate does not overlap the heavily doped portion.
6. The thin film transistor of claim 1, wherein the gate overlaps both the lightly doped portion and the heavily doped portion.
7. The thin film transistor according to claim 1, wherein a thickness of the lightly doped portion is greater than or equal to 10 micrometers and less than or equal to 40 micrometers, a thickness of the heavily doped portion is greater than or equal to 10 micrometers and less than or equal to 40 micrometers, and a thickness of the channel portion is greater than or equal to 40 micrometers and less than or equal to 60 micrometers.
8. A method of manufacturing a thin film transistor, the method comprising:
forming two doping parts and a channel part which are arranged at intervals, wherein one channel part is positioned between the two doping parts, at least one doping part comprises a light doping part and a heavy doping part, at least part of the light doping part is overlapped with the heavy doping part, the light doping part extends towards the channel part relative to the heavy doping part, and the light doping part is contacted with the channel part;
forming a gate on one side of the channel part, wherein the gate is arranged corresponding to the channel part;
and forming a first electrode and a second electrode on one side of the channel part, wherein the first electrode is contacted with one doped part, and the second electrode is contacted with the other doped part.
9. The method for manufacturing a thin film transistor according to claim 8, wherein the step of forming the two doped portions and the channel portion which are arranged at intervals comprises the steps of:
forming an amorphous silicon lightly doped layer and an amorphous silicon heavily doped layer which are sequentially superposed;
patterning the amorphous silicon lightly doped layer and the amorphous silicon heavily doped layer by adopting a first composition process to obtain amorphous silicon lightly doped patterns and amorphous silicon heavily doped patterns positioned on the amorphous silicon lightly doped patterns, wherein the amorphous silicon lightly doped patterns extend outwards relative to the amorphous silicon heavily doped patterns;
forming an amorphous silicon channel layer covering the amorphous silicon light-doped patterns and the amorphous silicon heavy-doped patterns, and patterning the amorphous silicon channel layer by adopting a second composition process to obtain amorphous silicon channel patterns, wherein the amorphous silicon channel patterns are positioned between two adjacent amorphous silicon light-doped patterns and are in contact with the amorphous silicon light-doped patterns and the amorphous silicon heavy-doped patterns;
and carrying out crystallization treatment on the amorphous silicon lightly doped pattern, the amorphous silicon heavily doped pattern and the amorphous silicon channel pattern, wherein the amorphous silicon lightly doped pattern is crystallized to form the lightly doped part, the amorphous silicon heavily doped pattern is crystallized to form the heavily doped part, and the amorphous silicon channel pattern is crystallized to form the channel part.
10. A display panel, comprising:
the thin film transistor according to any one of claims 1 to 7; and
and the light-emitting unit is electrically connected with the thin film transistor.
CN202210717810.3A 2022-06-23 2022-06-23 Thin film transistor, manufacturing method thereof and display panel Pending CN115000179A (en)

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