KR101419239B1 - Thin Film Transtistor, Method for Manufacturing the Same and Method for Manufacturing Flat Panel Display Device Using the Same - Google Patents

Abstract

The present invention relates to a thin film transistor in which device characteristics are improved by reducing the thickness of a gate insulating film on a source / drain electrode in a top gate structure by performing a process of defining a channel region separately from formation of a source / drain electrode, A method of manufacturing a thin film transistor according to the present invention includes depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer, A step of forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width, forming a source / drain region corresponding to both sides of the semiconductor layer and in contact with the impurity layer, Forming a source electrode and a drain electrode on the semiconductor layer; Forming a gate insulating film on the substrate including the semiconductor layer and the source / drain electrodes, forming a gate electrode on the gate insulating film in correspondence with the center of the semiconductor layer, And forming a second electrode on the second electrode.

An alternating magnetic field crystallization (AMFC), a thin film transistor, an amorphous silicon layer, a crystalline silicon

Description

[0001] The present invention relates to a thin film transistor (TFT), a method of manufacturing the same,

The present invention relates to a thin film transistor and more particularly to a method of forming a channel region separately from a formation of a source / drain electrode and reducing a thickness of a gate insulating film above a source / drain electrode in a top gate structure, A method of manufacturing the same, and a method of manufacturing a display using the thin film transistor.

Recently, the demand for low temperature polysilicon thin film transistors as driving elements for display devices such as active matrix liquid crystal display devices (AMLCD) and active matrix organic light emitting diodes (AMOLED) has been increasing.

A thin film transistor (TFT) is mainly used as a switching device for driving a display device, and amorphous silicon is mainly used as an active layer of the thin film transistor.

In particular, a liquid crystal display device using a liquid crystal arranged in a predetermined direction according to an electric field as a component of a display device employs a thin film transistor as a switching device. Today, in order to realize a high response speed and low power consumption, Research on the use of polysilicon as the active layer has been actively conducted.

A process for producing a liquid crystal display device using polysilicon as a channel is generally a process for forming amorphous silicon on a substrate such as glass by a plasma chemical vapor deposition (PECVD) method and crystallizing the deposited amorphous silicon It proceeds.

As a method of crystallizing the amorphous silicon, there are a high temperature heating method of crystallizing the amorphous silicon through a process of heating and cooling the amorphous silicon for a long time in a high temperature furnace, a high temperature heating method of instantaneously irradiating a high intensity laser energy, An annealing method or the like is used.

Since the amorphous silicon layer is heated at a high temperature not lower than the glass transition temperature of the crystallization method, various methods for crystallizing amorphous silicon at low temperature are not suitable because it is not suitable for application to liquid crystal display devices using glass or the like as a substrate Respectively.

Among them, AMFC (Alternating Magnetic Field Crystallization) method has been proposed in which crystallization proceeds by applying a magnetic field at which crystallization progresses at a relatively low temperature.

The AMFC crystallization method promotes crystallization by applying an alternating magnetic field to amorphous silicon to form an induced electromotive force in the silicon layer. By the FEMIC and AMFC crystallization, the silicon layer can undergo crystallization at about 500 ° C or about 430 ° C.

Amorphous silicon has a very high resistivity value of about 10 ⁶ ~ 10 ¹⁰ Ω-㎝, which is a resistivity at room temperature. However, when the temperature of amorphous silicon is increased by external heating, the resistivity rapidly decelerates and joule heating occurs It is known that AMFC crystallization promotes crystallization.

However, the AMFC crystallization method has an advantage that crystallization is possible at a low temperature, but has a disadvantage in that the voltage characteristics of the crystallized silicon are not good. That is, the channel layer formed by the AMFC crystallization is not a good crystalline material, and the thin film transistor including the crystalline silicon has a problem that the threshold voltage (Vth) is shifted to a negative value, have.

Hereinafter, a conventional thin film transistor will be described with reference to the accompanying drawings.

1A is a cross-sectional view of a conventional amorphous silicon thin film transistor, and FIG. 1B is a cross-sectional view illustrating the structure of the semiconductor layer of FIG. 1A.

1A and 1B, a conventional thin film transistor using amorphous silicon has a structure in which a gate insulating film 3, an amorphous silicon layer 4a and an n + layer 4b are sequentially stacked by a PECVD (Plasma Enhanced Chemical Vapor Deposition) At this time, the semiconductor layer 4 is composed of the amorphous silicon layer 4a and the n + layer 4b.

That is, a conventional thin film transistor using amorphous silicon has a gate electrode 2 formed on a predetermined portion of a substrate 1, a gate insulating film 3 formed on the entire surface of the substrate 1 including the gate electrode 2, A semiconductor layer 4 formed of a laminate of the amorphous silicon layer 4a and the n + layer 4b on the gate insulating film 3 and formed in the shape of a star so as to cover the gate electrode 2, And source / drain electrodes 5a / 5b formed on both sides of the source / drain electrodes 4a and 4b.

In a display device using such a thin film transistor, a contact hole is formed on the gate insulating film 3 including the source / drain electrodes 5a / 5b and exposes a part of the drain electrode 5b An interlayer insulating film 6 and a pixel electrode 7 formed by filling the contact hole and making contact with the drain electrode 5b.

The semiconductor layer 4 defines a region between the source and drain electrodes 5a and 5b as a channel and the n + layer 4b corresponding to the channel and the amorphous silicon layer 4a Is removed.

Hereinafter, an example in which a semiconductor layer crystallized by an AMFC (Alternating Magnetic Field Crystallization) method is used instead of the amorphous silicon layer will be described.

FIG. 2A is a cross-sectional view illustrating a thin film transistor having a self-crystallized (AMFC) semiconductor layer, and FIG. 2B is a cross-sectional view illustrating the structure of the semiconductor layer of FIG.

2A and 2B, a thin film transistor using a self-crystallized semiconductor layer is formed by sequentially depositing a buffer layer 11 made of an oxide film (SiO2) and a first amorphous silicon layer, applying a magnetic field thereto, The first amorphous silicon layer is crystallized to form a crystalline silicon layer 12a, and then the second amorphous silicon layer 12b and the n + layer 12c are sequentially deposited again.

That is, the thin film transistor using the self-crystallized semiconductor layer comprises a substrate 10, a buffer layer 11 formed on the entire surface of the substrate 10, a crystalline silicon layer 12a on the buffer layer 11, A semiconductor layer 12 formed of a laminate of an amorphous silicon layer 12b and an n + layer 12c and patterned in a predetermined region on the substrate 10; a source electrode 12 formed on both sides of the semiconductor layer 12; A gate insulating film 14 formed on the entire surface including the gate electrode 13b and the drain electrode 13a and the source and drain electrodes 13b and 13a and the gate insulating film 14 corresponding to the center of the gate insulating film 14. [ And a gate electrode 15 formed on the gate electrode 15.

In a display device using such a thin film transistor, a protective film 16 formed on the gate insulating film 14 including the gate electrode 15 and a predetermined portion of the protective film 16 and the gate insulating film 14 And a pixel electrode 17 which is exposed in a portion of the drain electrode 13a and which is buried in the contact and makes contact with the drain electrode 13a.

The semiconductor layer 12 defines a region between the source / drain electrodes 13b / 13a as a channel, and the n + layer 12c corresponding to the channel and the second amorphous silicon layer (12b) is removed.

During the formation of the semiconductor layer using the self-crystallization method, the second amorphous silicon layer 12b and the n + layer 12c are continuously deposited after the AMFC crystallization.

After the formation of the source / drain electrodes, the thickness of the gate insulating layer 14 is adjusted to the thickness of the source / drain electrodes 13b / 13a, the n + layer (the impurity layer The first amorphous silicon layer 12c, the second amorphous silicon layer 12b and the crystalline silicon layer 12a crystallized in the magnetic field crystallization method, The thickness of the gate insulating film 14 of the device including the semiconductor layer is relatively higher than that of the thin film transistor including the semiconductor layer formed by another method. That is, in the case of a thin film transistor using a magnetic field crystallization semiconductor layer, there is some limit in reducing the thickness of the gate insulating film.

3A and 3B are graphs showing device characteristics of the thin film transistor according to the thickness of the gate insulating film of the self-crystallizing semiconductor layer.

FIG. 3A is a graph showing the device characteristics of the thin film transistor when the thickness of the gate insulating film is 1500 ANGSTROM, and FIG. 3B is a graph showing the device characteristics of the thin film transistor when the gate insulating film is 2500 ANGSTROM.

As can be seen from the graphs, when the gate insulating film thickness is thin, the area of the sub-threshold voltage is smaller than that of the thick gate insulating film. When the device thickness is thick, the device characteristics of the thin film transistor are stabilized The results are shown in Fig.

In the above-mentioned graphs, the magnetic field crystallization semiconductor layer (AMFC) has a very characteristic dependency on the gate insulating film thickness, and in particular, it has an extreme device performance difference in the sub-threshold region. Particularly, when such a thin film transistor is used for a thin film transistor for driving an organic electroluminescent element having a large driving current, it can be considered that the thickness of the above-described gate insulating film greatly affects the device characteristics. Therefore, it is necessary to develop a device structure for lowering the thickness of the gate insulating film without causing process problems.

However, the conventional method of forming a thin film transistor using the semiconductor layer crystallized by the self-crystallization has the following problems.

An amorphous silicon layer and an impurity layer to be used as an offset barrier are deposited after AMFC (Alternating Magnetic Field Crystallization) crystallization.

As described above, there is a discontinuous interface at the interface between the amorphous silicon layer formed to prevent offsetting again and the crystallized AMFC layer below the crystallized AMFC layer. As a result, the electron mobility of the semiconductor layer And the electrical characteristics of the thin film transistor using the thin film transistor are deteriorated.

In addition, the magnetic field crystallization semiconductor layer (AMFC) has a very characteristic dependence on the thickness of the gate insulating film. Particularly, in the sub-threshold region, the AMFC has extreme device performance differences. Particularly, when such a thin film transistor is used for a thin film transistor for driving an organic electroluminescence element having a large driving current, it can be considered that the thickness of the gate insulating film greatly affects the device characteristics. However, in the case of a thin film transistor including a semiconductor layer crystallized by a general self-crystallization method, the gate insulating film substructure includes a semiconductor layer, a source / drain electrode, and the like. In order to ensure sufficient step coverage, There is a limit to reducing the thickness. Therefore, it is necessary to develop a device structure for lowering the thickness of the gate insulating film without causing process problems. Conventionally, since the thickness of the gate insulating film has to be set to about 1.5 times the thickness of the lower structure for stabilizing step coverage, it has been difficult to lower the thickness to about 3000 ANGSTROM or less. As a result, the characteristics of the thin film transistor were lowered by the increased gate insulating film thickness.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises the steps of defining a channel region separately from formation of a source / drain electrode, The present invention also provides a method of manufacturing a thin film transistor and a method of manufacturing the same using the same.

According to an aspect of the present invention, there is provided a thin film transistor comprising: a substrate; a channel region formed at a center thereof; a crystalline silicon layer formed by a magnetic field crystallization method; A source / drain electrode formed in contact with the impurity layer of the semiconductor layer, the source / drain electrode being spaced apart from the channel portion by a first distance outward; A gate insulating film formed on a substrate; And a gate electrode spaced apart from the source and drain electrodes and corresponding to the center of the semiconductor layer. Here, the first interval is 2 탆 to 6 탆. The gate insulating film is 1000 to 2000 ANGSTROM or less. For example, the gate insulating film is made of SiO2.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor including depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer, Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width, forming a source / drain electrode corresponding to both sides of the semiconductor layer and contacting the impurity layer, And defining a channel of the semiconductor layer at a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively; and forming a gate insulating film on the substrate including the semiconductor layer and the source / ; And forming a gate electrode on the gate insulating layer in correspondence with the center of the semiconductor layer.

Here, the gate electrode is formed so as not to overlap with the source / drain electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor including: depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; A step of forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer by the same width, depositing a metal layer on the substrate including the semiconductor layer, Forming a photoresist pattern having a first height portion and a source / drain electrode defining portion as a second height portion (> first height portion) as a channel defining portion of the semiconductor layer; And etching the impurity layer to define a channel of the semiconductor layer; and a step of ashing the photoresist pattern to entirely reduce the thickness of the first height portion Forming a source / drain electrode corresponding to both sides of the semiconductor layer and contacting the impurity layer by etching the metal layer using the photoresist film ashing pattern as a mask; Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, forming a gate insulating layer on the substrate including the semiconductor layer and the source / drain electrode; And forming a gate electrode on the gate insulating layer in correspondence with the center of the semiconductor layer.

A method of manufacturing a display device for achieving the same object includes the steps of forming a protective film on the gate insulating film including the gate electrode in the method of manufacturing the thin film transistor described above, Forming a contact hole exposing the drain electrode; And forming a pixel electrode connected to the drain electrode by embedding the contact hole.

The method of manufacturing a thin film transistor of the present invention and the method of manufacturing a display using the same have the following effects.

First, the region where the source / drain electrode and the semiconductor layer overlap each other is reduced, and the step coverage can be ensured by the small thickness of the gate insulating film due to the reduction of overlapping portions of the gate insulating film substructure. Accordingly, the thickness of the gate insulating film can be reduced to 2000 angstroms or less, preferably 1500 angstroms or less.

Secondly, the channel width definition is performed separately from the formation of the source / drain electrodes to set the separation distance between the channel and the source / drain electrode, thereby eliminating the planar overlapped region between the source / drain electrode and the gate electrode , The thickness of the gate insulating film can be reduced.

Third, the amorphous silicon layer is crystallized by a magnetic field crystallization method, and the impurity layer is discontinuously layered on the amorphous silicon layer to perform patterning, so that the impurity layer diffuses into the crystallized silicon layer during crystallization, So that the characteristics of the semiconductor layer can be improved.

Fourth, the formation of the thin film transistor can be performed by a total of three masks in the definition of 'semiconductor layer and channel', 'definition of source / drain electrode' and 'definition of gate electrode', thereby reducing the number of masks used.

Fifth, when used in an active matrix organic electroluminescent device, the driving characteristics are improved by improving the saturation characteristics of the driving thin film transistor and the region where the mutual conductance value is maximum (gm Max) is directed toward the flat band voltage Vfb Thereby reducing the required voltage level of the transfer characteristics of the thin film transistor.

FIGS. 4A and 4B are cross-sectional views illustrating a channel forming method and a gate electrode forming method of an example self-crystallizing semiconductor layer, and FIGS. 5A and 5B are plan views of FIGS. 4A and 4B.

As shown in FIGS. 4A and 5A, the semiconductor layer is formed by an example of the self-crystallization method by depositing a buffer layer 51 and a first amorphous silicon layer on the substrate 50 in a primary succession, The first amorphous silicon layer is crystallized at a predetermined temperature to form a crystalline silicon layer 52a, and then the second amorphous silicon layer 52b and the n + layer 53 are sequentially deposited again.

Next, the semiconductor layers 53, 52b and 52a are defined by selectively removing the n + layer 53, the second amorphous silicon layer 52b, and the crystalline silicon layer 52a.

Next, a metal layer is deposited on the buffer layer 51 including the semiconductor layers 53, 52b and 52a, and a photoresist layer is deposited on the metal layer, followed by exposure and development to form a photoresist pattern 55 .

The metal layer is selectively removed using the photoresist pattern 55 as a mask to form source / drain electrode source / drain electrodes 54a / 54b corresponding to both sides of the semiconductor layer and in contact with the n + layer 53 do.

Then, the thickness of the upper part of the n + layer 53, the second amorphous silicon layer 52b and the crystalline silicon layer 52a of the semiconductor layer exposed under the source / drain electrodes 54a / 54b is removed, ≪ / RTI > Here, the channel width is the same as the spacing distance between the source electrode 52a and the drain electrode 52b. In this case, a reference numeral 63 denotes a semiconductor layer in which a channel is completely defined and patterned.

The gate insulating layer 56 is formed on the entire surface of the buffer layer 51 including the source / drain electrodes 54a / 54b and the semiconductor layer 63, as shown in FIGS. 4B and 5B.

A metal layer is deposited on the gate insulating layer 56 and selectively removed to form a gate electrode 57 that partially overlaps the source / drain electrodes 54a / 54b, such as region A.

That is, since the channel of the thin film transistor is defined together with the formation of the source / drain electrode, a thickness of a part of the crystalline silicon layer 52a located on both sides of the channel, a thickness of the second amorphous silicon layer The gate insulating film 56 must be formed to have a sufficient thickness because a step is formed by the sum of the thicknesses of the n + layer 52b, the n + layer 53 and the source / drain electrodes 54a / 54b. It has been necessary to form the gate electrode 57 to be overlapped with some of the source / drain electrodes 54a / 54b through the step for sufficient and stable patterning.

A method of manufacturing a thin film transistor, a method of manufacturing the same, and a method of manufacturing a display using the thin film transistor according to the present invention are characterized in that the source and drain electrodes and the gate electrode are not overlapped with each other, And a stable step coverage structure can be obtained even if the gate insulating film is deposited with a small thickness by minimizing a step generated on both sides of the channel of the channel.

Hereinafter, a thin film transistor of the present invention, a method of manufacturing the same, and a method of manufacturing a display using the same will be described in detail with reference to the accompanying drawings.

- First Embodiment -

FIGS. 6A and 6B are cross-sectional views illustrating a channel forming method and a gate electrode forming method of a self-crystallizing semiconductor layer in a method for manufacturing a thin film transistor according to a first embodiment of the present invention. FIGS. 7A and 7B are cross- Fig.

6A and 7A, the formation of a thin film transistor having a semiconductor layer by a self-crystallization method according to the first embodiment of the present invention is performed by forming a buffer layer 101 and an amorphous silicon layer And the n + layer 102b are sequentially deposited on the crystalline silicon layer 102a after the amorphous silicon layer 102a is crystallized at a predetermined temperature by applying a magnetic field to the amorphous silicon layer 102a.

Next, the semiconductor layer 102 is defined by selectively removing the n + layer 102b and the crystalline silicon layer 102a.

Next, a metal layer is deposited on the buffer layer 101 including the semiconductor layer 102, a photoresist layer is deposited on the metal layer, and exposed and developed to form a first photoresist pattern (not shown).

The source / drain electrode source / drain electrodes 104a / 104b corresponding to both sides of the semiconductor layer 102 and in contact with the n + layer 102b are selectively removed using the first photoresist pattern as a mask, .

A photoresist layer is formed on the buffer layer 101 including the source and drain electrodes 104a and 104b and the semiconductor layer 102 and selectively removed to form a second photoresist pattern 105. [ The second photoresist pattern 105 is formed to have a thickness of 2 to 6 μm in the center of the semiconductor layer 102 as compared with the first photoresist pattern and defines a channel of the semiconductor layer 102.

The exposed portion of the n + layer 102b and the upper portion of the crystalline silicon layer 102a are removed using the second photoresist pattern 105 as a mask to form the semiconductor layer 102 having the L width, Lt; / RTI > channel.

6B and 7B, a gate insulating layer 106 is formed on the entire surface of the buffer layer 101 including the source / drain electrodes 104a / 104b and the semiconductor layer 102. Next, as shown in FIG.

A metal layer is deposited on the gate insulating layer 106 and is selectively removed to correspond to a central portion of the semiconductor layer 102 so as not to overlap with the source / drain electrodes 104a / 104b, Thereby forming the gate electrode 107.

That is, in the method of manufacturing a thin film transistor of the present invention, since the channel and the source / drain electrode are separately formed, in the region where the semiconductor layer 102 and the source / drain electrodes 104a and 104b are in contact with each other, Since the step thickness corresponds only to the thickness of the metal of the source / drain electrodes 104a / 104b, step coverage can be secured relative to the above-described structure, So that it can be formed into a thickness. Since the space between the source electrode 104a and the drain electrode 104b and the channel between them is 2 to 6 占 퐉, the gate electrode 107 formed on the insulating film of the gate insulating film 106 And may have sufficient clearance to be spaced apart from the source / drain electrodes 104a / 104b.

Referring to FIG. 7B, the thin film transistor of the present invention is formed on a substrate 100, a channel portion is defined at the center, and a crystalline silicon layer 102a formed by a magnetic field crystallization method and a region other than the channel portion A semiconductor layer 102 made of an impurity layer 102b (n + layer) formed on the crystalline silicon layer and corresponding to the impurity layer 102b of the semiconductor layer 102, And a gate insulating layer 106 formed on the substrate 100 including the source and drain electrodes 104a and 104b and the semiconductor layer 102. The source and drain electrodes 104a and 104b are formed in contact with the source and drain electrodes 104a and 104b, And a gate electrode 107 formed to correspond to the center of the semiconductor layer 102, spaced apart from the gate electrode 104a and the drain electrode 104b.

Here, the first interval between the edge of the channel portion and the edge of the source / drain electrode 104a / 104b is 2 占 퐉 to 6 占 퐉.

The gate insulating layer 106 has a thickness of 1000 to 2000 ANGSTROM or less. For example, the gate insulating layer 106 is made of SiO2.

Hereinafter, a method of manufacturing a display device including a method of manufacturing a thin film transistor according to a first embodiment of the present invention will be described in detail.

8A to 8L are process cross-sectional views illustrating a method of manufacturing a display device according to a first embodiment of the present invention.

The manufacturing method of the display device according to the first embodiment of the present invention is performed in the following procedure.

First, as shown in FIG. 8A, a buffer layer 101 and an amorphous silicon layer 112a made of an oxide film (SiO 2) are sequentially deposited on a substrate 100. Here, the buffer layer 101 and the amorphous silicon layer 112a are sequentially deposited on the substrate 100 by using a plasma enhanced chemical vapor deposition (PECVD) equipment.

8B, a magnetic field is applied to the substrate 100 to crystallize the amorphous silicon layer 112a to form a crystalline silicon layer 112b.

As shown in FIG. 8C, an n + layer 113 is formed on the crystalline silicon layer 112b.

The n + layer 113 and the crystalline silicon layer 112b are selectively removed by a first mask (not shown) to form the n + layer pattern 113a and the crystalline silicon layer pattern 112c of the same width, .

The metal layer 104 is entirely deposited on the buffer layer 101 including the n + layer pattern 113a and the crystalline silicon layer pattern 112c, as shown in FIG. 8E.

8F, a photoresist layer is coated on the entire surface of the metal layer 104, and exposed and developed by a second mask (not shown) to form a first photoresist pattern having a first interval on the n + layer pattern 113a 115).

Using the first photoresist pattern 115 as a mask, the metal layer 104 is selectively removed to form the source / drain electrodes 104a / 104b.

Then, the first photoresist pattern 115 is removed.

8G, a photoresist layer is coated on the entire surface of the buffer layer 101 including the source / drain electrodes 104a / 104b, exposed and exposed by a third mask (not shown) A second photoresist pattern 105 having a shape coming in at a first interval (2 to 6 mu m) from both sides is formed.

Then, a channel is defined by removing the thickness of the upper part of the n + layer 113a and the crystalline silicon layer pattern 112c exposed using the second photoresist pattern 105 as a mask. The patterned crystalline silicon layer pattern serves as the ohmic contact layer 102b and the lower portion 102a serves as a crystalline silicon layer pattern. The crystalline silicon layer pattern 102a and the ohmic contact layer 102b The semiconductor layer 102 is formed of a stacked body of the semiconductor layers 102 and 103. At this time, the thickness at which the crystalline silicon layer pattern 102a is removed is set to about 100 angstroms or more. The over etch is formed in a part of the upper part of the crystalline silicon layer pattern 102a in order to remove the contaminated surface of the crystalline silicon layer pattern 102a in the process of defining the channel and the like.

8G, the second photoresist pattern 105 is stripped and removed.

A gate insulating layer 106 is deposited on the buffer layer 101 including the source / drain electrodes 104a / 104b and the semiconductor layer 102 as shown in FIG. 8I. The gate insulating film is preferably formed of a SiO2 component.

8J, a metal layer is deposited on the gate insulating layer 106, and then a photoresist layer (not shown) is coated. Then, the photoresist layer is exposed and developed by a fourth mask (not shown) ). Next, using the photoresist pattern as a mask, the metal layer is selectively removed to form a gate electrode 107. Here, the gate electrode is formed so as not to overlap with the source / drain electrode.

The thin film transistor according to the first embodiment including the gate electrode 107, the source / drain electrodes 104a / 104b and the semiconductor layer 102 crystallized by the AMFC method is defined by such a process.

Here, the thin film transistor may be used as a driving device for driving each pixel such as a liquid crystal display device or an organic light emitting device, and display is performed through a pixel electrode connected to the thin film transistor.

Hereinafter, a method for forming a pixel electrode for driving each pixel of a display device by adding another process to the above-described process will be described.

8K, a protective film 108 is formed on the entire surface of the gate insulating film 106 including the gate electrode 107.

Next, a photoresist layer is coated on the entire surface of the protective layer 108, and then a photoresist layer pattern is formed by selectively removing the photoresist layer using a fifth mask (not shown), and the protective layer 108 and gate A protective film pattern 108a and a gate insulating film pattern 106a are formed so as to expose a part of the drain electrode 104b by selectively removing the insulating film 106. A contact hole C ).

As shown in FIG. 8L, a transparent electrode material is deposited on the entire surface of the protective film pattern 108a after the contact hole C is filled. Then, a photosensitive film is coated on the transparent electrode material and patterned by a sixth mask (not shown) And then the transparent electrode material is patterned to form a pixel electrode 109 electrically connected to the drain electrode 104b.

- Second Embodiment -

9A and 9B are cross-sectional views illustrating a channel forming method of a self-crystallizing semiconductor layer in a method of manufacturing a thin film transistor according to a second embodiment of the present invention.

9A, the formation of a thin film transistor having a semiconductor layer by a self-crystallization method according to the second embodiment of the present invention is performed by forming a buffer layer 201 on the substrate 200 and a thin film transistor having the same structure as the amorphous silicon layer 202a Layer is sequentially and continuously deposited, and a magnetic field is applied thereto to crystallize the amorphous silicon layer at a predetermined temperature to form a crystalline silicon layer 202a, and then the n + layer 202b is deposited in order.

Next, the semiconductor layer 202 is defined by selectively removing the n + layer 202b and the crystalline silicon layer 202a.

Next, a metal layer (see 214 in FIG. 10F) is deposited on the buffer layer 201 including the semiconductor layer 202, and the photoresist layer is entirely coated on the metal layer. Then, the photoresist layer is exposed and developed using a mask to form a channel defining portion of the semiconductor layer 202 in a first height portion and a first height portion and a source / drain electrode defining portion in a second height portion (first height portion) A photoresist pattern 205 is formed.

The metal layer and the impurity layer 202b are etched using the first photoresist pattern 205 as a mask to define the metal layer pattern 214a and the channel of the semiconductor layer 202. [

The first photoresist pattern 205 is ashed so that the first height portion is entirely removed in the first photoresist pattern 205 as shown in FIG. 9B, thereby forming a second photoresist pattern 205a .

At this time, the second photoresist pattern 205a is formed outside the first photoresist pattern 205 by about 2 to 6 mu m.

Next, the metal layer pattern 214a is selectively removed using the second photoresist pattern 205a as a mask to define a source / drain electrode (see 204a / 204b in FIG. 10I).

As described above, in the above-described method for forming a thin film transistor, the channel and the source / drain electrode of the semiconductor layer can be defined by a single mask, whereby the same effect is obtained as compared with the first embodiment, Can be reduced.

FIGS. 10A to 10N are cross-sectional views showing a manufacturing method of a display device according to a second embodiment of the present invention, and FIGS. 11A to 11J are cross-sectional views illustrating a manufacturing method of a display device according to a second embodiment of the present invention to be.

A manufacturing method of a display device according to a second embodiment of the present invention is performed in the following procedure.

First, as shown in FIGS. 10A and 11A, a buffer layer 201 and an amorphous silicon layer 212 made of an oxide film (SiO 2) are sequentially deposited on a substrate 200. Here, the buffer layer 201 and the amorphous silicon layer 212 are sequentially deposited on the substrate 200 by using a plasma enhanced chemical vapor deposition (PECVD) equipment.

10B and 11B, a magnetic field is applied to the substrate 200 to crystallize the amorphous silicon layer 212 to form a crystalline silicon layer 212a.

As shown in FIGS. 10C and 11C, an n + layer 213 is formed on the crystalline silicon layer 212a.

As shown in FIGS. 10D and 11D, the n + layer 213 and the crystalline silicon layer 212a are selectively removed by a first mask (not shown) to form an n + layer pattern 213a and a crystalline silicon layer pattern 212b.

The metal layer 214 is entirely deposited on the buffer layer 201 including the n + layer pattern 213a and the crystalline silicon layer pattern 212b, as shown in FIGS. 10E and 11E.

As shown in FIGS. 10F and 11F, the photoresist layer is coated on the entire surface of the metal layer 214 and exposed and developed using a second mask (not shown) to form the channel defining portion of the semiconductor layer into the first height portion and the source / The first photoresist pattern 205 having the drain electrode defining portion as the second height portion (> the first height portion) is formed.

The metal layer 214 and the impurity layer 202b are etched using the first photoresist pattern 205 as a mask to form a metal layer pattern 214a and a channel of the semiconductor layer 202 as shown in FIGS. define. Thereby forming a semiconductor layer 202 with a laminate of the crystalline silicon pattern 202a and the n + layer pattern 212b left.

In the first photoresist pattern 205, the first photoresist pattern 205 is ashed so that the first height portion is entirely removed, and the second photoresist pattern 205a is ashed as shown in FIGS. 10h and 11h. .

At this time, the second photoresist pattern 205a is formed outside the first photoresist pattern 205 by about 2 to 6 mu m.

Next, the metal layer pattern 214a is selectively removed using the second photoresist pattern 205a as a mask to form a source / drain electrode (see 204a / 204b in FIG. 10i) as shown in FIGS. 10I and 11I do.

10J and 12J, the second photoresist pattern 205a is stripped and removed.

The gate insulating layer 206 is entirely deposited on the buffer layer 201 including the source and drain electrodes 204a and 204b and the semiconductor layer 202 as shown in FIG. The gate insulating film is preferably formed of a SiO2 component.

A metal layer 207 is deposited on the gate insulating layer 206 and then a photoresist layer (not shown) is coated. Then, the photoresist layer is exposed and developed by a third mask (not shown) .

As shown in FIG. 10L, the metal layer 207 is selectively removed using the photoresist pattern as a mask to form a gate electrode 207a. Here, the gate electrode 207a is formed so as not to overlap with the source / drain electrodes 204a / 204b.

A thin film transistor according to the second embodiment including the gate electrode 207a, the source / drain electrodes 204a / 204b and the semiconductor layer 202 crystallized by the AMFC method is defined by such a process.

Here, the thin film transistor may be used as a driving device for driving each pixel such as a liquid crystal display device or an organic light emitting device, and display is performed through a pixel electrode connected to the thin film transistor.

Hereinafter, a method for forming a pixel electrode for driving each pixel of a display device by adding another process to the above-described process will be described.

The entire surface of the protective film 208 is formed on the gate insulating film 206 including the gate electrode 207a as shown in FIG.

Next, a photoresist layer (not shown) is coated on the entire surface of the protective layer, and then the photoresist layer is selectively removed using a fourth mask (not shown) to form a photoresist pattern. 206 are selectively removed to form a protective film pattern 208 and a gate insulating film pattern 206a to expose a part of the drain electrode 204b and a contact hole C is formed in an exposed portion of the drain electrode 204b define.

10N, a transparent electrode material is deposited on the entire surface of the protective film pattern 208, the photoresist film is coated on the transparent electrode material, and the pattern is patterned by a sixth mask (not shown) Then, the transparent electrode material is patterned to form a pixel electrode 209 which is electrically connected to the drain electrode 204b.

The top gate type AMFC (self-crystallizing semiconductor layer) is formed in the amorphous silicon forming process by merely adding a magnetic field crystallization process to the amorphous silicon thin film transistor. It is possible to realize a device with high reliability.

As described above, it is possible to ensure excellent uniformity over the laser crystallized semiconductor layer through the magnetic-field-crystallized semiconductor layer, which can be used when an active matrix organic light-emitting device or a drive IC is formed in the panel. As a result, a narrow bezel can be realized with superior device performance and reliability as compared with a thin film transistor using a semiconductor layer made of a conventional amorphous silicon layer, and more circuits can be integrated.

 A method of manufacturing a thin film transistor according to the present invention includes the steps of crystallizing an amorphous silicon layer for magnetic field crystallization, depositing an impurity layer and patterning the semiconductor layer, patterning the channel and the source / drain electrodes separately, It is possible to stabilize the step coverage even if the gate insulating film formed on the relatively low thickness is deposited by reducing the stepped portion of the overlapped portion of the electrode and the semiconductor layer.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1A is a cross-sectional view of a conventional amorphous silicon thin film transistor

1B is a cross-sectional view showing the structure of the semiconductor layer of FIG. 1A

2A is a cross-sectional view showing a thin film transistor having a self-crystallizing semiconductor layer

FIG. 2B is a cross-sectional view showing the structure of the semiconductor layer of FIG. 2A

3A and 3B are graphs showing the device characteristics of the thin film transistor according to the thickness of the gate insulating film of the self-crystallizing semiconductor layer

FIGS. 4A and 4B are cross-sectional views showing a channel forming process and a gate electrode forming process of an example self-crystallizing semiconductor layer

Figs. 5A and 5B are plan views of Figs. 4A and 4B

6A and 6B are cross-sectional views illustrating a channel formation process and a gate electrode formation process of a self-crystallizing semiconductor layer in a method of manufacturing a thin film transistor according to a first embodiment of the present invention

Figs. 7A and 7B are plan views of Figs. 6A and 6B

8A to 8L are cross-sectional views showing the manufacturing method of the display device according to the first embodiment of the present invention

9A and 9B are cross-sectional views illustrating a channel forming method of a self-crystallizing semiconductor layer in a method of manufacturing a thin film transistor according to a second embodiment of the present invention

10A to 10N are cross-sectional views showing a manufacturing method of a display device according to a second embodiment of the present invention

11A to 11J are process plan views showing a manufacturing method of a display device according to a second embodiment of the present invention

DESCRIPTION OF THE REFERENCE CHARACTERS

100, 200: substrate 101, 201: buffer layer

102, 202: semiconductor layer 104a, 204a: source electrode

104b, 204b: drain electrode 106, 206: gate insulating film

107, 207a: gate electrode 108, 208:

Claims (16)

A semiconductor layer formed on the substrate and having a channel portion defined at the center thereof and including a crystalline silicon layer formed by a magnetic field crystallization method and an impurity layer formed on the crystalline silicon layer in correspondence with an area other than the channel portion; A source / drain electrode spaced apart from the channel portion by a first distance and in contact with the impurity layer of the semiconductor layer; A gate insulating film formed on the substrate including the source / drain electrodes and the semiconductor layer; And And a gate electrode spaced apart from the source electrode and the drain electrode and corresponding to a center of the semiconductor layer. The method according to claim 1, Wherein the first spacing is 2 占 퐉 to 6 占 퐉. The method according to claim 1, Wherein the gate insulating film has a thickness of 1000 to 2000 ANGSTROM or less. The method of claim 3, Wherein the gate insulating film is SiO2. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Forming a source / drain electrode corresponding to both sides of the semiconductor layer and in contact with the impurity layer; Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively; Forming a gate insulating film on the substrate including the semiconductor layer and the source / drain electrodes; And And forming a gate electrode on the gate insulating layer in correspondence with the center of the semiconductor layer. 6. The method of claim 5, Wherein the first spacing is between 2 탆 and 6 탆. 6. The method of claim 5, Wherein the gate electrode is formed so as not to overlap with the source / drain electrode. 6. The method of claim 5, Wherein the gate insulating layer has a thickness of 1000 to 2000 ANGSTROM or less. 9. The method of claim 8, Wherein the gate insulating film is SiO2. 6. The method of claim 5, Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively, And removing a portion of the upper portion of the impurity layer and the crystallized silicon layer corresponding to the channel. 11. The method of claim 10, Wherein a thickness of the crystallized silicon layer is 100 angstroms or more. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Depositing a metal layer on the substrate including the semiconductor layer; forming a channel defining portion of the semiconductor layer on the metal layer with a first height portion and a source / drain electrode defining portion as a second height portion (first height portion) Forming a photoresist pattern; Defining a channel of the semiconductor layer by etching the metal layer and the impurity layer using the photoresist pattern as a mask; Forming a photoresist film ashing pattern by ashing the photoresist pattern to entirely remove the thickness of the first height portion; Etching the metal layer using the photoresist film ashing pattern as a mask to form source / drain electrodes corresponding to both sides of the semiconductor layer and in contact with the impurity layer; Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively; Forming a gate insulating film on the substrate including the semiconductor layer and the source / drain electrodes; And And forming a gate electrode on the gate insulating layer in correspondence with the center of the semiconductor layer. 13. The method of claim 12, Wherein the first spacing is between 2 탆 and 6 탆. 13. The method of claim 12, Wherein the gate electrode is formed so as not to overlap with the source / drain electrode. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Forming a source / drain electrode corresponding to both sides of the semiconductor layer and in contact with the impurity layer; Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively; Forming a gate insulating film on the substrate including the semiconductor layer and the source / drain electrodes; Forming a gate electrode on the gate insulating film in correspondence with the center of the semiconductor layer; Forming a protective film on the gate insulating film including the gate electrode; Selectively removing the protective film and the gate insulating film to form a contact hole exposing the drain electrode; And And filling the contact hole with the drain electrode to form a pixel electrode connected to the drain electrode. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Depositing a metal layer on the substrate including the semiconductor layer; forming a channel defining portion of the semiconductor layer on the metal layer with a first height portion and a source / drain electrode defining portion as a second height portion (first height portion) Forming a photoresist pattern; Defining a channel of the semiconductor layer by etching the metal layer and the impurity layer using the photoresist pattern as a mask; Forming a photoresist film ashing pattern by ashing the photoresist pattern to entirely remove the thickness of the first height portion; Etching the metal layer using the photoresist film ashing pattern as a mask to form source / drain electrodes corresponding to both sides of the semiconductor layer and in contact with the impurity layer; Defining a channel of the semiconductor layer in a first gap toward the center of the semiconductor layer from the source electrode and the drain electrode, respectively; Forming a gate insulating film on the substrate including the semiconductor layer and the source / drain electrodes; Forming a gate electrode on the gate insulating film in correspondence with the center of the semiconductor layer; Forming a protective film on the gate insulating film including the gate electrode; Selectively removing the protective film and the gate insulating film to form a contact hole exposing the drain electrode; And And filling the contact hole with the drain electrode to form a pixel electrode connected to the drain electrode.

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