KR20080085277A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An array substrate for an LCD(Liquid Crystal Display) and a method for manufacturing the same are provided to improve the electron mobility of a thin film transistor by using a silicon layer crystallized through alternating magnetic field crystallization. A first intrinsic amorphous silicon layer is formed on a substrate(101). The fist intrinsic amorphous silicon layer is crystallized into a poly-silicon layer(111) through alternating magnetic field crystallization. A second intrinsic amorphous silicon layer and an impurity-doped amorphous silicon layer are sequentially formed on the poly-silicon layer. A three-layered structure semiconductor layer(125) is formed by pattern-etching the impurity-doped amorphous silicon layer, the second intrinsic amorphous silicon layer, and the poly-silicon layer. A source electrode(133) and a drain electrode(136) are formed on the semiconductor layer, and a data line(130) is formed on the substrate. A portion of the impurity-doped amorphous silicon layer and the second intrinsic amorphous silicon layer, which are exposed between the source electrode and the drain electrode, are removed to expose the poly-silicon layer partially and form ohmic contact layers(122) and intrinsic silicon layers(117) having the same shape as the ohmic contact layers. A gate-insulating layer(140) is formed on the resultant substrate including the source electrode, the drain electrode, and the exposed portion of the poly-silicon layer. A gate electrode and a gate line connected to the gate electrode are formed on the gate-insulating layer. The gate electrode corresponds to the poly-silicon layer while the gate line crosses the data line. A passivation layer(155) is formed on the resultant substrate including the gate electrode and the gate line. The passivation layer has a drain contact hole(157) for exposing the drain electrode. A pixel electrode(160) is formed on the passivation layer. The pixel electrode is connected to the drain electrode through the contact hole.

Description

Array substrate for liquid crystal display device and method for manufacturing same {Array substrate for Liquid Crystal Display Device and method of fabricating the same}

1 is a cross-sectional view of one pixel region within an array substrate for a liquid crystal display device having a thin film transistor composed of a general polysilicon semiconductor layer.

2 is a cross-sectional view showing one pixel region of an array substrate for a liquid crystal display device having a coplanar structure thin film transistor having an alternating current self-crystallization silicon layer according to an embodiment of the present invention.

3A to 3K are cross-sectional views of manufacturing steps of one pixel region of an array substrate for a liquid crystal display device having a coplanar structure thin film transistor having an alternating current self-crystallization silicon layer according to the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 103 buffer layer

111: First Silicon Layer (AC Self-crystallized)

111a: first silicon layer of second thickness 111b: first silicon layer of first thickness

117: second pure amorphous silicon layer spaced apart from each other

122: ohmic contact layer spaced apart from each other 125: semiconductor layer

130: data wiring 133: source electrode

136: drain electrode 140: gate insulating film

150: gate wiring 155: protective layer

157: drain contact hole 160: pixel electrode

P: pixel region t1: first thickness of the first silicon layer

t2: second thickness of the first silicon layer t3: thickness of the second pure amorphous silicon

t4: thickness of the ohmic contact layer

The present invention relates to a liquid crystal display device, and more particularly, to a structure of a thin film transistor formed in each pixel region of an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate to obtain an image effect by using a difference in refractive index of light according to the anisotropy of the liquid crystal. Means an image display device by a non-light emitting element.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner is attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because low-temperature processing is possible, so that an inexpensive insulating substrate can be used.

However, since hydrogenated amorphous silicon (a-Si: H) is disordered in its atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, in a state of quasi-stable state when light irradiation or electric field is applied. When used as a thin film transistor element is changed, the stability is a problem, and has a low mobility of about 0.1 to 1.0 cm 2 / V · s has a problem that is difficult to use as a circuit element constituting the drive circuit.

Therefore, in recent years, an array substrate for a liquid crystal display device that uses a polysilicon having a mobility value of 1.0 cm 2 / V · s or more and has excellent electrical characteristics as a semiconductor layer to form a thin film transistor has been proposed.

1 is a cross-sectional view of one pixel region inside an array substrate for a liquid crystal display device having a thin film transistor composed of a general polysilicon semiconductor layer.

As shown, each pixel region P on the substrate 10 is heavily doped source and drain regions 13d and 13e and an undoped active region 13a corresponding to the upper gate electrode 21. And a polysilicon semiconductor layer 13 composed of the lightly doped LDD regions 13b and 13c between the active region 13a and the source and drain regions 13d and 13e. The gate insulating layer 16 is formed on the gate insulating layer 16, and the gate electrode 21 is formed on the gate insulating layer 16.

In addition, an interlayer insulating layer 25 having first and second semiconductor layer contact holes 28a and 28b exposing the source and drain regions 13d and 13e, respectively, is formed on the gate electrode 21. The source and drain electrodes 30 and 32 are in contact with the source and drain regions 13d and 13e and spaced apart from each other through the first and second semiconductor layer contact holes 28a and 28b, respectively. And a protective layer 35 having a drain contact hole 38 exposing a portion of the drain electrode 32 over the source and drain electrodes 30 and 32, and an upper portion of the protective layer 35. The pixel electrode 40 is formed in contact with the drain electrode 32 through the drain contact hole 38.

At this time, looking at the structure of the semiconductor layer 13 in more detail, it can be seen that the semiconductor layer 13 consists of three parts. That is, the semiconductor layer 13 may be doped with an active region 13a made of pure polysilicon in a non-doped state corresponding to the gate electrode 21, and doped with a low concentration of impurities on both sides of the active region 13a. LDD regions 13b and 13c and source and drain regions 13d and 13e doped with a high concentration of impurities, respectively, outside the LDD regions 13b and 13c.

The reason for forming the polysilicon semiconductor layer 13 as the structure including the LDD regions 13b and 13c is to effectively reduce the leakage current.

However, in manufacturing an array substrate for a liquid crystal display device having a thin film transistor having polysilicon as a semiconductor layer having the above-described structure, low-doped LDD regions 13b and 13c should be formed, and thus doping blocking for LDD doping Since the mask process needs to be further progressed to form a mask, this causes a problem of productivity deterioration due to an increase in manufacturing cost due to a long manufacturing process time and an increase in manufacturing process.

Accordingly, the present invention for solving the above-described problem does not require a doping process, so that the mask process can be omitted, and at the same time, an array substrate for a liquid crystal display device having a thin film transistor including a semiconductor layer having excellent mobility characteristics. And it aims at providing the manufacturing method.

In addition, another object of the present invention is to reduce manufacturing cost and improve productivity by shortening the manufacturing time and simplifying the manufacturing process by omitting a mask process for proceeding the doping process.

In order to achieve the above object, an array substrate for a liquid crystal display device according to an embodiment of the present invention, the substrate; A semiconductor layer having a triple layer structure in which polysilicon layers, pure amorphous silicon layers spaced apart from each other, and ohmic contact layers spaced apart from each other are sequentially stacked; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other, and data lines connected to the source electrodes and formed on the substrate; A gate insulating film formed over the data line and the source and drain electrodes; A source electrode and a drain electrode spaced apart from each other on the gate insulating layer, a gate electrode formed corresponding to a spaced area between the two electrodes, and a gate wire connected to the gate electrode and crossing the data wire to define a pixel area; A protective layer having a drain contact hole exposing the drain electrode on the entire surface of the gate wiring and the gate electrode; And a pixel electrode formed on the passivation layer and in contact with the drain electrode through the drain contact hole in the pixel region.

In this case, the region of the polysilicon layer overlapping the ohmic contact layers spaced apart from each other formed on the upper portion has a first thickness, and other regions have a second thickness thinner than the first thickness. The first thickness is 1200 kPa to 2000 kPa, and the second thickness is 800 kPa to 1800 kPa.

In addition, the lower portion of the polysilicon layer is characterized in that the buffer layer is further formed on the front surface, each of the source and drain electrodes is characterized by covering the side surface of the semiconductor layer of the triple layer structure.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes the steps of forming a first pure amorphous silicon layer of a first thickness on a substrate; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing an alternating magnetic field crystallization process; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer on the polysilicon layer; Patterning the impurity, the second pure amorphous silicon layer, and the polysilicon layer to form a semiconductor layer having a triple layer structure; Forming source and drain electrodes spaced apart from each other on the semiconductor layer of the triple layer structure, and simultaneously forming data lines connected to the source electrodes on the substrate; Pure impurities of pure amorphous silicon having the same shape as the ohmic contact layer and an ohmic contact layer spaced apart from each other by exposing the polysilicon layer by removing impurities and a second pure amorphous silicon layer exposed between the source and drain electrodes. Forming a silicon layer; Forming a gate insulating film over the source and drain electrodes, the data lines, and the exposed polysilicon layer; Forming a gate electrode on the gate insulating layer corresponding to the polysilicon layer, and simultaneously forming a gate wiring connected to the gate electrode and crossing the data wiring; Forming a protective layer having a drain contact hole exposing the drain electrode over the gate electrode and the gate wiring; Forming a pixel electrode connected to the drain electrode through the drain contact hole on the passivation layer.

In this case, the alternating magnetic field crystallization process is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C., and the AC magnetic field generating device is positioned above and below the substrate with respect to the substrate located in the chamber. And it is characterized in that the progress in the form of a horizontal reciprocating motion in a horizontal direction, characterized in that for 1 to 60 seconds.

In addition, forming the pure silicon layer of pure amorphous silicon having the same shape as the ohmic contact layer and the ohmic contact layer spaced apart from each other while exposing the polysilicon layer, the poly exposed between the ohmic contact layer Removing the silicon layer so as to have a second thickness that is 200 kHz to 400 보다 thinner than the first thickness, wherein each of the spaced source and drain electrodes includes an upper portion of the semiconductor layer to the side of the semiconductor layer. It is characterized by forming so as to completely cover.

The method may further include performing a hydrogenation process of exposing the surface of the AC self-crystallization silicon layer exposed between the source and drain electrodes to the hydrogen (H ₂ ) plasma before forming the gate insulating layer.

In addition, before forming the first pure amorphous silicon layer, further comprising the step of heat-treating the substrate for 30 to 60 minutes in the atmosphere of 700 ℃ to 750 ℃, further comprising the step of forming a buffer layer on the front surface over the substrate do.

The thin film transistor according to the present invention includes a semiconductor layer having a triple layer structure in which a polysilicon layer, a pure amorphous silicon layer spaced apart from each other, and an ohmic contact layer spaced apart from each other are sequentially stacked; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other; A gate insulating film formed on the entire surface of the source and drain electrodes; And a source electrode and a drain electrode spaced apart from each other on the gate insulating layer, and a gate electrode corresponding to a spaced area between the two electrodes.

In this case, the region of the polysilicon layer overlapping the ohmic contact layer spaced apart from each other formed on the upper portion has a first thickness, and the other regions have a second thickness thinner than the first thickness. Each of the source and drain electrodes is formed to cover the side surface of the semiconductor layer of the triple layer structure.

Hereinafter, an array substrate for a liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a cross-sectional view of one pixel area of an array substrate for a liquid crystal display device having a coplanar structure thin film transistor having an alternating current self-crystallization silicon layer according to an exemplary embodiment of the present invention. For convenience of description, a region in which the thin film transistor, which is a switching element, is to be formed in each pixel region P is defined as a switching region TrA.

As shown, a buffer layer 103 is formed on the transparent insulating substrate 101, and in the switching region TrA above the buffer layer 103, pure amorphous silicon is crystallized by an alternating magnetic field to have polysilicon characteristics. The first silicon layer 111 and the impurity amorphous silicon formed while being spaced apart from each other on the second silicon layer 117 of pure amorphous silicon spaced apart from each other on the upper portion and the second silicon layer 117 spaced apart from each other The semiconductor layer 125 having a partially triple layer structure formed of the ohmic contact layer 122 is formed. In this case, when the structure of the semiconductor layer 125 is described in more detail, only the first silicon layer 111 having a polysilicon characteristic crystallized by an alternating magnetic field is formed in the central portion thereof, and the first and second sides of the semiconductor layer 125 are formed on both sides thereof. A second silicon layer 117 of pure amorphous silicon and an ohmic contact layer 122 of impurity amorphous silicon are formed on one silicon layer 111. Accordingly, the first silicon layer 111 is exposed between the ohmic contact layers 122 formed at both sides thereof. In addition, the first silicon layer 111 may have a thickness t1 of the portion 111a exposed between the ohmic contact layer 122 as the thickness t2 of the portion 111b of the triple layer. It is characterized by being thinly formed.

In the semiconductor layer 125, the first and second silicon layers 111 and 117 and the ohmic contact layer 122 are formed so that their ends coincide with each other.

Next, both sides of the semiconductor layer 125 having the triple layer structure having such a structure cover the ohmic contact layers 122 formed to be spaced apart from each other, and expose the first silicon layer 111a in the center portion to expose the source and drain. The electrodes 133 and 136 are formed spaced apart from each other.

In addition, the source and drain electrodes 133 and 136 may be formed on the substrate 101 when the buffer layer 103 or the buffer layer 103 is omitted, as well as the top and side surfaces of the semiconductor layer 125. It is characterized by being extended upward.

In addition, the data line 130 is formed on the buffer layer 103 and connected to the source electrode 133.

In addition, the gate insulating layer 140 is formed on the entire surface of the first silicon layer 111a exposed at the center between the source and drain electrodes 133 and 136, the data line 130, and the source and drain electrodes 133 and 136. The gate electrode 150 is formed on the gate insulating layer 140 to correspond to the semiconductor layer 125 in the switching region TrA. In this case, the gate electrode 150 overlaps both ends of the first silicon layer 111a exposed at the center between the source and drain electrodes 133 and 136 and the source and drain electrodes 133 and 136 facing each other. It is characterized by being formed. In this case, the semiconductor layer 125, the source and drain electrodes 133 and 136, the gate insulating layer 140, and the gate electrode 150 form a thin film transistor.

In addition, the gate insulating layer 140 is connected to the gate electrode 150 and at the same time intersects the data line 130 to define a pixel region P, and a gate line (not shown) is formed. The passivation layer 155 is formed on the entire surface of the wiring (not shown) and the gate electrode 150. At this time, the protective layer 155 and the gate insulating layer 140 disposed below the drain insulating hole 157 exposing the drain electrode 136 are formed by removing a corresponding portion of the drain electrode 136. .

In addition, a pixel electrode 160 is formed in the pixel region P on the passivation layer 155 having the drain contact hole 157 and in contact with the drain electrode 136 through the drain contact hole 157. have.

The array substrate 101 for a liquid crystal display device according to the present invention having such a structure includes a semiconductor layer 125 including a first silicon layer 111 whose thin film transistor Tr is crystallized by an alternating magnetic field. A conventional array substrate having polysilicon as a semiconductor layer having a polysilicon including an LDD layer formed by a doping process, having a high mobility compared to a conventional thin film transistor having a double layer semiconductor layer of pure amorphous silicon and impurity amorphous silicon. In contrast, since the configuration is relatively simple, productivity is improved in terms of manufacturing method.

Hereinafter, the manufacturing method of the array substrate for liquid crystal display devices which has the above-mentioned structure is demonstrated.

3A to 3K are cross-sectional views illustrating manufacturing steps of one pixel region of an array substrate for a liquid crystal display device having a coplanar structure thin film transistor having an alternating current self-crystallization silicon layer according to the present invention.

First, as shown in FIG. 3A, the transparent insulating substrate 101 is moved to a chamber 190 of a chemical vapor deposition (CVD) apparatus, and then a mixed gas atmosphere of SiH ₄ / N ₂ , SiH _{4 is used.} After forming a mixed gas atmosphere of any one of a / NH ₃ mixed gas atmosphere and a SiH ₄ / N ₂ O mixed gas atmosphere, silicon nitride (SiNx) is formed on the substrate 101 by forming a plasma in the chamber 190. Alternatively, a buffer layer 103 of silicon oxide (SiO ₂ ) is formed on the entire surface.

Next, a mixed gas atmosphere (SiH ₄ / N) for forming the buffer layer 103 while the substrate 101 on which the buffer layer 103 is formed is positioned in the chamber 190 for forming the buffer layer 103 as it is. ₂ , SiH ₄ / NH ₃ , or SiH ₄ / N ₂ O mixed gas atmosphere) to SiH ₄ / H ₂ mixed gas atmosphere, and then form a plasma in the chamber 190 to the buffer layer 103 A first pure amorphous silicon layer 109 having a first thickness t1 of about 1200 kPa to 2000 kPa is formed. In this case, the first pure amorphous silicon layer 109 may be formed directly on the substrate 101 without forming the buffer layer 103 by omitting the process of forming the buffer layer 103. The buffer layer 103 has to undergo an alternating magnetic field crystallization due to the characteristics of the present invention. In this case, the heat treatment process of 700 ° C. to 750 ° C. is simultaneously performed, and the substrate 101 is formed due to the heat generated by the heat treatment process. In the case of a glass material, alkali ions, for example, potassium ions (K +), sodium ions (Na +), etc. present in the glass material may be generated, and the film properties of the semiconductor layer crystallized by the alkali ions may be reduced. For sake.

Next, as shown in FIG. 3B, the substrate 101 on which the first pure amorphous silicon layer (109 of FIG. 3A) of the first thickness t1 is formed is placed in the chamber of the chemical vapor deposition apparatus (190 in FIG. 3A). ) Into chamber 193 of the alternating current self crystallization process equipment.

The AC self-crystallization process chamber 193 may form a high temperature atmosphere of about 500 ° C. to 1000 ° C., and more specifically, centers a stage (not shown) in which the substrate 101 is located in the chamber 193. This feature is capable of forming an alternating magnetic field above and below.

After placing the substrate 101 on which the first pure amorphous silicon layer (109 of FIG. 3B) is formed on a stage (not shown) in the AC self-crystallization process chamber 193 having these characteristics, the AC self-crystallization process chamber After warming the internal atmosphere (193) to 700 ° C to 750 ° C, a magnetic field (AMF) perpendicular to the substrate 101 is applied for 1 second to 60 seconds in the warmed atmosphere.

At this time, it is preferable to expose the surface of the substrate 101 to the alternating magnetic field (AMF) in such a manner that the alternating magnetic field generator 195 located above and below the substrate 101 performs a linear reciprocating motion. . That is, the first pure amorphous silicon layer (109 in FIG. 3A) is exposed to an alternating magnetic field in a scan form. When the process of exposing to a scan type alternating magnetic field in such a heated atmosphere proceeds to recrystallization of the first pure amorphous silicon layer (109 of FIG. 3A), the first alternating self crystallization silicon layer 110 having polysilicon characteristics Will change to

On the other hand, when explaining the principle of crystallization of amorphous silicon using the alternating magnetic field used in the present invention, the main energy source of the crystallization is heat, the alternating magnetic field plays an auxiliary role. At this time, a current is induced inside the pure amorphous silicon layer by the alternating magnetic field, and the joule heat is generated by the induced internal current to accelerate the crystallization, and by applying the force to move the atoms by the alternating magnetic field It will promote crystallization.

The first alternating current self-crystallization silicon layer 110 having the polysilicon characteristics formed by the self-crystallization process has a mobility of 20 cm 2 / V · s to 30 cm 2 / V · s, which is 0.1 cm 2 / V · s to It can be seen that the mobility properties are improved by several tens to several hundred times compared to the pure amorphous silicon layer having a mobility of about 1 cm 2 / V · s.

The process of crystallizing by exposing to an alternating magnetic field (AMF) in such a high temperature atmosphere is called an alternating magnetic field crystallization (AMFC) process.

Since the substrate 101 is exposed to a high temperature of about 700 ° C. to 750 ° C. during the AMFC process, the substrate 101 may be deformed more precisely, so that shrinkage may occur. In order to form nothing on the substrate 101, that is, before forming the buffer layer 103 or the first pure amorphous silicon layer (109 of FIG. 3A), the substrate 101 may be 700 ° C. to 750. In the high temperature atmosphere of about ℃ to 30 minutes to 60 minutes after changing the temperature of the heat treatment further proceeds, it is preferable to proceed with the AMFC process.

Next, as shown in FIG. 3C, the substrate 101 having completed the AMFC process is moved back into the chamber 190 of the chemical vapor deposition apparatus in the AC self-crystallization process chamber (193 of FIG. 3B). After forming the atmosphere in the chamber 190 of the chemical vapor deposition equipment into a mixed gas atmosphere of SiH ₄ / H ₂ , and then forming a plasma, 300 to 500 kPa on the first AC self-crystallization silicon layer 110 having the polysilicon characteristics. A second pure amorphous silicon layer 115 having a third thickness t3 of a degree is formed.

Next, the atmosphere in the chamber is changed to SiH ₄ / PH ₃ / H ₂ in a state where the substrate 101 on which the second pure amorphous silicon layer 115 is continuously formed is placed in the chamber 190 of the chemical vapor deposition apparatus. After changing to the mixed gas atmosphere of the impurity amorphous silicon layer 120, characterized in that phosphorus (P) is mixed as an impurity inside the second pure amorphous silicon layer 115 by forming a plasma 300 Å It is formed to have a fourth thickness t4 of about 500 kHz.

Next, as shown in FIG. 3D, the sequentially laminated first alternating magnetic silicon layer 110, the second pure amorphous silicon layer 115, and the impurity amorphous silicon layer 120 are coated with a photoresist and an exposure mask is applied. By masking and patterning a series of unit processes such as exposure, development, and etching, the first silicon layer 111 having polysilicon characteristics in the switching region TrA and the second silicon layer 116 of pure amorphous silicon are patterned. ) And a third semiconductor layer 125 composed of a third silicon layer 121 of impurity amorphous silicon.

Next, as shown in FIG. 3E, a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), is formed on the semiconductor layer 125 having the triple layer structure. Data that extends in one direction over the buffer layer 103 by forming a photoresist pattern 181 by etching one or two materials selected from chromium (Cr) and performing a mask process thereon and etching the same. Source and drain electrodes are formed to form a wiring 130, and at the same time, are spaced apart from each other on the semiconductor layer 125 in the switching region TrA and extend to the buffer layer 103 to cover the side surface of the semiconductor layer 125. 133 and 136 are formed. In this case, the source electrode 133 is connected to the data line 130.

Next, as shown in FIG. 3F, the photoresist pattern 181 formed to pattern it over the source and drain electrodes 133 and 136 and the data line 130 is stripped and removed. A third silicon layer of impurity amorphous silicon exposed between the source and drain electrodes 133 and 136 by dry etching the semiconductor layer 125 having a triple layer structure exposed between the source and drain electrodes 133 and 136. The alternating magnetic crystallized first exposed by removing the second silicon layer (116 of FIG. 3E) while removing the second silicon layer (116 of FIG. 3E) of pure amorphous silicon below and 121 of FIG. 3E. In the region overlapping with the source and drain electrodes 133 and 136 by removing a predetermined thickness from the surface of the silicon layer 111, the structure has a triple layer structure, that is, a portion exposed between the two electrodes 133 and 136. center Not corresponding to the self-exchange and form the shape of the semiconductor layer 125 has a single layer structure of the crystallized first silicon layer (111a).

At this time, in the case of the alternating current self-crystallized first silicon layer 111, the thickness t5 that is etched and removed from the surface thereof is preferably 200 kPa to 400 kPa. Therefore, the portion 111b overlapping the source and drain electrodes 133 and 136 is maintained at 1200 Å to 2000 인, which is the first thickness t1 as originally formed, and the source and drain electrodes 133 and 136. Corresponding to the portion 111a exposed in between, the first thickness t1 has a second thickness t2 = t1-t5 of about 800 kPa to about 1800 kPa, which is reduced from about 200 kPa to about 400 kPa. .

In this case, the third silicon layer of the impurity amorphous silicon in the form of being spaced apart from each other by the center portion is formed to form an ohmic contact layer 122.

Next, as shown in FIG. 3G, the photoresist pattern (181 of FIG. 3F) remaining on the data line 130 and the source and drain electrodes 133 and 136 is stripped or ashed. After the removal and the removal, the substrate 101 from which the photoresist pattern 181 of FIG. 3F is removed is moved to a chamber 190 of a plasma generating apparatus, for example, a chemical vapor deposition apparatus, and then a hydrogen (H ₂ ) gas. A hydrogenation process is performed in which the plasma is exposed to the plasma for about 300 to 600 seconds. This may be a part of the surface damaged or contaminated by dry etching, etc. This may cause a problem that the characteristics at the interface with the gate insulating film formed thereon may be degraded in a later step, the source and drain This is to stabilize the surface state by exposing the surface of the first silicon layer 111a exposed between the electrodes to hydrogen (H ₂ ) plasma.

Next, as shown in FIG. 3H, an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is disposed on the entire surface of the hydrogen (H ₂ ) plasma-treated substrate 101. The gate insulating layer 140 is formed on the front surface by the same method of forming the same, that is, by using a chemical vapor deposition apparatus, and the second metal material, for example, aluminum (Al) on the front surface of the gate insulating layer 140 is successively formed. ), One or two materials of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), chromium (Cr) are continuously deposited to form a metal layer 145 having a single layer or a double layer structure.

Next, as shown in FIG. 3I, a mask process is performed to pattern the metal layer 145 of FIG. 3I to cross the data line 130 to define the pixel region P on the gate insulating layer 140. A gate line (not shown) is formed, and at the same time, a gate electrode 150 is formed in the switching region TrA, connected to the gate line (not shown), and corresponding to the semiconductor layer 125.

In this case, the gate electrode 150 overlaps the ohmic contact layer 122 spaced apart from each other so as to correspond to the entire surface of the first silicon layer 111a exposed between the source and drain electrodes 133 and 136, respectively. In this case, both ends of the ohmic contact layer 122 and each of the gate electrode 150 may not be extended to the outside of the ohmic contact layer 122. It is preferable to position the inside of.

Next, as shown in FIG. 3J, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited or organic insulating on the gate wiring (not shown) and the gate electrode 150. The protective layer 155 is formed by applying a material such as photo acryl or benzocyclobutene (BCB).

Thereafter, the passivation layer 155 and the gate insulating layer 140 disposed thereunder are patterned by a mask process to form a drain contact hole 157 exposing a part of the drain electrode 136.

Next, as shown in FIG. 3K, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the protective layer 155 having the drain contact hole 157. And forming a pixel electrode 160 in contact with the drain electrode 136 through the drain contact hole 157 in the pixel region P by performing a mask process and patterning the thin film having a coplanar structure according to the present invention. The array substrate 101 for a liquid crystal display device including the transistor is completed.

The array substrate for a liquid crystal display device according to the present invention has an effect of improving the mobility characteristics of a thin film transistor by several tens to hundred times as compared to a conventional array substrate having amorphous silicon as a semiconductor layer by AMFC treating a pure amorphous silicon layer. Therefore, the thin film transistor having the semiconductor layer having the polysilicon characteristic, which is treated with AMFC, can be used as a driving device as well as a switching device. Therefore, since the external driving circuit is not required, the cost can be reduced. At the same time, it is possible to increase the degree of integration of the driving device, which makes the product compact.

In addition, in the conventional method for manufacturing an array substrate for a liquid crystal display device including a thin film transistor having a coplanar structure using polysilicon, a 7-9 mask process is usually completed by performing doping, etc. In the case of an array substrate for a liquid crystal display according to the present invention, a process such as doping is not required separately, and a product can be completed by a five mask process including a thin film transistor structure having a top gate coplanar structure. Through this has the effect of improving productivity.

In addition, the array substrate for a liquid crystal display device according to the present invention implements a thin film transistor having a coplanar structure in which a gate electrode is positioned on a semiconductor layer. The AC self-crystallization process includes the source and drain electrodes, the data wiring, and the gate electrode. And by proceeding before the formation of the gate wiring has the advantage that the choice of the metal material constituting the data wiring with the gate electrode, gate wiring, source and drain electrodes.

Claims (17)

A substrate; A semiconductor layer having a triple layer structure in which polysilicon layers, pure amorphous silicon layers spaced apart from each other, and ohmic contact layers spaced apart from each other are sequentially stacked; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other, and data lines connected to the source electrodes and formed on the substrate; A gate insulating film formed over the data line and the source and drain electrodes; A source electrode and a drain electrode spaced apart from each other on the gate insulating layer, a gate electrode formed corresponding to a spaced area between the two electrodes, and a gate wire connected to the gate electrode and crossing the data wire to define a pixel area; A protective layer having a drain contact hole exposing the drain electrode on the entire surface of the gate wiring and the gate electrode; A pixel electrode formed on the protective layer in contact with the drain electrode through the drain contact hole in the pixel area Array substrate for a liquid crystal display device comprising a. The method of claim 1, The polysilicon layer may have a first thickness in a region overlapping the spaced apart ohmic contact layers formed on the polysilicon layer, and the other region may have a second thickness that is thinner than the first thickness. Board. The method of claim 2, And the first thickness is 1200 kPa to 2000 kPa and the second thickness is 800 kPa to 1800 kPa. The method of claim 1, And a buffer layer further formed on a front surface of the lower portion of the polysilicon layer. The method of claim 1, And each of the source and drain electrodes is formed to cover a side surface of the triple layer structure semiconductor layer. Forming a first layer of pure amorphous silicon of a first thickness on the substrate; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing an alternating magnetic field crystallization process; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer on the polysilicon layer; Patterning the impurity, the second pure amorphous silicon layer, and the polysilicon layer to form a semiconductor layer having a triple layer structure; Forming source and drain electrodes spaced apart from each other on the semiconductor layer of the triple layer structure, and simultaneously forming data lines connected to the source electrodes on the substrate; Pure impurities of pure amorphous silicon having the same shape as the ohmic contact layer and an ohmic contact layer spaced apart from each other by exposing the polysilicon layer by removing impurities and a second pure amorphous silicon layer exposed between the source and drain electrodes. Forming a silicon layer; Forming a gate insulating film over the source and drain electrodes, the data lines, and the exposed polysilicon layer; Forming a gate electrode on the gate insulating layer corresponding to the polysilicon layer, and simultaneously forming a gate wiring connected to the gate electrode and crossing the data wiring; Forming a protective layer having a drain contact hole exposing the drain electrode over the gate electrode and the gate wiring; Forming a pixel electrode connected to the drain electrode through the drain contact hole on the passivation layer; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 6, The alternating magnetic field crystallization process is performed in a chamber having an atmosphere of 700 ° C to 750 ° C. The method of claim 7, wherein The alternating magnetic field crystallization process is characterized in that the alternating magnetic field generating device is positioned in a vertical linear reciprocating motion of the alternating magnetic field generating device located above and below the substrate with respect to the substrate located in the chamber. Method of manufacturing a substrate. The method of claim 7, wherein The alternating magnetic field crystallization process is performed for 1 to 60 seconds. The method of claim 6, Forming a pure silicon layer of pure amorphous silicon having the same shape as the ohmic contact layer and the ohmic contact layer spaced apart from each other while exposing the polysilicon layer, And removing the polysilicon layer exposed between the ohmic contact layers so as to have a second thickness that is 200 s to 400 s thinner than the first thickness. The method of claim 6, Wherein the source and drain electrodes spaced apart from each other are formed to completely cover side surfaces of the semiconductor layer, including an upper portion of the semiconductor layer. The method of claim 6, A method of fabricating an array substrate for a liquid crystal display device, further comprising: performing a hydrogenation process of exposing an AC self-crystallized silicon layer surface exposed between the source and drain electrodes to a hydrogen (H ₂ ) plasma prior to forming the gate insulating layer. Way. The method of claim 6, Before forming the first pure amorphous silicon layer, The method of manufacturing an array substrate for a liquid crystal display device further comprising the step of heat-treating the substrate for 30 to 60 minutes in an atmosphere of 700 ℃ to 750 ℃. The method of claim 6, Before forming the first pure amorphous silicon layer, A method of manufacturing an array substrate for a liquid crystal display device further comprising the step of forming a buffer layer over the substrate. A semiconductor layer having a triple layer structure in which polysilicon layers, pure amorphous silicon layers spaced apart from each other, and ohmic contact layers spaced apart from each other are sequentially stacked; Source and drain electrodes formed on the ohmic contact layers spaced apart from each other; A gate insulating film formed on the entire surface of the source and drain electrodes; Source and drain electrodes spaced apart from each other on the gate insulating layer, and a gate electrode corresponding to a spaced area between the two electrodes Thin film transistor comprising a. The method of claim 15, The polysilicon layer is a thin film transistor, characterized in that the region overlapping with the spaced apart ohmic contact layer formed on the upper portion has a first thickness, the other region has a second thickness thinner than the first thickness. The method of claim 15, Each of the source and drain electrodes is formed to cover the side surface of the semiconductor layer of the triple layer structure.

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