KR101325666B1 - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention is a substrate; A gate electrode formed on the substrate; A gate insulating film formed over the gate electrode; A first silicon layer of polysilicon sequentially stacked over the gate insulating film and having a first region of a first thickness and a second region of a second thickness, a second silicon layer of pure amorphous silicon, and impurity amorphous silicon spaced apart from each other A semiconductor layer having a triple layer structure composed of an ohmic contact layer; An array substrate for a liquid crystal display device including a source and a drain electrode formed on and in contact with the ohmic contact layer, respectively, and a method of manufacturing the same.

Array Substrate, Semiconductor Layer, Polysilicon, Alternating Self Crystallization

Description

Array substrate for liquid crystal display device and method of fabricating the same

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of a portion including a thin film transistor in one pixel area of an array substrate of a conventional liquid crystal display device.

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

4A to 4G are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display device according to a first exemplary embodiment of the present invention.

5 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

6A to 6G are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

7A and 7B are sectional views showing pixel areas including thin film transistors of an array substrate for a liquid crystal display device according to a modification of the first and second embodiments, respectively;

8A through 8C are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display device according to a modification of the second exemplary embodiment of the present invention.

Description of the Related Art

201: substrate 205: gate electrode

208: gate insulating film 214: first silicon layer (of polysilicon)

214a and 214b: first and second regions of the first silicon layer

219: second silicon layer (of pure amorphous silicon)

225: ohmic contact layer 244: source electrode

246: drain electrode 250: protective layer

253: drain contact hole 260: pixel electrode

299: chamber of plasma generator

chA: channel region t1: first thickness (thickness of the first region)

t2: second thickness (thickness of the second region)

P: Pixel Area Tr: Thin Film Transistor

TrA: Switching Area

The present invention relates to a liquid crystal display device, and more particularly, to a structure of a thin film transistor formed in each pixel region of an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Of these liquid crystal display devices, an active matrix type liquid crystal display device having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, .

Referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, a structure of a liquid crystal display device will be described. As illustrated, the array substrate 10 and the color filter substrate 20 are disposed with the liquid crystal layer 30 therebetween. In this case, the bottom substrate array substrate 10 is vertically intersected with the upper surface of the transparent substrate 12 to define a plurality of pixel regions P and a plurality of gate wirings 14 and data wirings 16. A thin film transistor T is provided at an intersection point of the two wires 14 and 16 and is connected one-to-one with the pixel electrode 18 provided in each pixel region P.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

A back-light is provided on the outer surface of the array substrate to supply light. An on / off signal of the thin film transistor T is sequentially scanned by the gate wiring 14, When the image signal of the data line 16 is transferred to the pixel electrode 18 of the selected pixel region P, the liquid crystal molecules therebetween are driven by the vertical electric field therebetween. As a result, It is possible to display branch images.

In the liquid crystal display having the above structure, the most important component is a thin film transistor which is formed for each pixel region and is connected to the gate and data lines and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode. Can be.

The cross-sectional structure of the thin film transistor, which serves as such a switching element, will be described with reference to FIG.

2 is a cross-sectional view of a portion in which a thin film transistor is formed in an array substrate of a conventional liquid crystal display.

The gate electrode 60 is formed on the transparent insulating substrate 59, and the gate insulating layer 68 is formed on the entire surface of the gate electrode 60. In addition, a semiconductor layer including an active layer 70a made of pure amorphous silicon on the gate insulating layer corresponding to the gate electrode, and an ohmic contact layer 70b made of amorphous silicon containing impurities in a form spaced apart from each other. 70) is formed.

In addition, the ohmic contact layer 70b formed to expose the active layer 70a below and spaced apart from each other is in contact with the ohmic contact layer 70b and is spaced apart from each other to correspond to the gate electrode 60. The source electrode 76 and the drain electrode 78 are formed while exposing the layer 70a.

The thin film transistor Tr includes the gate electrode 60, the gate insulating film 68, and the source and drain electrodes 76 and 78 spaced apart from each other, and are sequentially stacked on the substrate 59. To achieve.

A passivation layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed on the front surface of the thin film transistor Tr having such a structure, and each passivation layer 86 is formed on the passivation layer 86. A pixel electrode 88 is formed in each pixel region P to contact the drain electrode 78 through the drain contact hole 80, and the gate electrode 60 is formed on the same layer on which the gate electrode 60 is formed. ) And a data line (not shown) connected to the source electrode 76 is further formed on the same layer on which the source and drain electrodes 76 and 78 are formed. )

However, in the case of a thin film transistor which is generally configured in a conventional array substrate for a liquid crystal display device, it can be seen that the semiconductor layer uses amorphous silicon. When the semiconductor layer is formed using the amorphous silicon, the amorphous silicon Since (a-Si: H) has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus change into a quasi-stable state when irradiating light or applying an electric field to a thin film transistor device. When it is used, stability is a problem, and the electric field effect mobility is low, such as 0.1 ~ 1.0 ㎠ / V · s, so that the electrical characteristics are not good, it is also a problem to use as a driving circuit.

In order to solve the above problems, an object of the present invention is to provide an array substrate for a liquid crystal display device having a thin film transistor having excellent device performance and reliability by crystallizing amorphous silicon by a simple process and a method of manufacturing the same.

Furthermore, by significantly improving the mobility characteristics, it can be used as a driving circuit and can be driven without the attachment of an external driving circuit board, thereby reducing costs and increasing the integration of the driving device. Another aim is to make it compact.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; A gate electrode formed on the substrate; A gate insulating film formed over the gate electrode; A first silicon layer formed of crystallized polysilicon sequentially stacked over the gate insulating film, the first silicon layer having a first region of a first thickness and a second region of a second thickness, and a second silicon layer made of pure amorphous silicon; A semiconductor layer having a triple layer structure composed of an ohmic contact layer of impurity amorphous silicon spaced apart; And source and drain electrodes formed on and in contact with the ohmic contact layer, respectively.

In this case, a protective layer formed by exposing the drain electrode over the source and drain electrodes; A gate electrode formed on the protective layer and in contact with the exposed drain electrode, the gate wire being connected to the gate electrode; And a data line connected to the source electrode and crossing the gate line.

In addition, the first thickness and the second thickness is characterized in that it is 1200 kPa to 2000 kPa.

In addition, the first thickness has a larger value than the second thickness, wherein the second region is characterized in that corresponding to the separation region of the ohmic contact layer, wherein the first thickness is 1200 ~ 2000Å, The difference between the first thickness and the second thickness is 200 kPa to 400 kPa, and the second silicon layer is formed to have the same shape as the ohmic contact layer.

The source and drain electrodes may be formed to completely cover both ends of the semiconductor layer to their side surfaces, and both ends of the source and drain electrodes and the semiconductor layer may be formed to coincide with each other.

In addition, the second silicon layer and the ohmic contact layer is characterized in that it has a thickness of 300 kPa to 500 kPa.

A method of manufacturing an array substrate for a liquid crystal display device according to a first aspect of the present invention includes forming a gate electrode on the substrate; Forming a gate insulating film over the gate electrode; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing alternating magnetic field crystallization; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer on the polysilicon layer; Simultaneously forming the impurity amorphous silicon layer, the second pure amorphous silicon layer, and the polysilicon layer to form a sequential first and second silicon layer and an ohmic contact layer on the gate electrode; Forming source and drain electrodes spaced apart from each other on the ohmic contact layer; And removing the ohmic contact layer exposed between the source and drain electrodes to form an ohmic contact layer spaced apart from each other.

A method of manufacturing an array substrate for a liquid crystal display device according to a second aspect of the present invention includes forming a gate electrode on the substrate; Forming a gate insulating film over the gate electrode; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing alternating magnetic field crystallization; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer over the polysilicon layer; Forming a metal layer over the impurity amorphous silicon layer; Source and drain electrodes spaced apart from each other by simultaneously patterning the metal layer, the impurity, the second pure amorphous silicon layer, and the polysilicon layer, ohmic contact layers sequentially spaced apart from each other, and second and first silicon layers It includes a step.

In the manufacturing method according to the first and second aspects, the alternating magnetic field crystallization is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C., and the alternating magnetic crystallization is performed in the chamber. The AC magnetic field generating device is positioned above and below the substrate and linearly reciprocates horizontally, and the AC magnetic crystallization is performed for 1 to 60 seconds.

Further, in the manufacturing method according to the first and second aspects, the second silicon layer exposed between the spaced apart ohmic contact layers is completely removed, and at the same time, the first silicon layer below the first silicon layer is smaller than the first thickness. The method further includes performing a dry etching to a state having a thin second thickness, wherein the dry etching is performed such that a difference between the first thickness and the second thickness is 200 kPa to 400 kPa. After etching, the method may further include performing a hydrogenation process of exposing the plasma to hydrogen (H ₂ ) atmosphere, wherein the hydrogenation process is performed for 300 to 600 seconds.

Further, the manufacturing method according to the first and second features, the method comprising: forming a protective layer exposing the drain electrode over the source and drain electrodes; The method may further include forming a pixel electrode in contact with the exposed drain electrode over the passivation layer. The forming of the gate electrode may further include forming a gate wiring connected to the gate electrode. The forming of the source and drain electrodes may further include forming a data line connected to the source electrode and crossing the gate line. In addition, before the gate electrode is formed, the substrate may further include a heat treatment for 30 minutes to 60 minutes in an atmosphere of 700 ° C to 750 ° C.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

As shown, in the case of the array substrate 101 for a liquid crystal display device according to the present invention, a gate electrode 105 and a gate wiring connected thereto are formed on the transparent insulating substrate 101. A gate insulating layer 108 is formed on the gate line and the gate electrode 105.

In addition, the first silicon layer 114 and the second silicon layer 119 of pure amorphous silicon and the upper spaced apart from each other, characterized in that the pure amorphous silicon crystallized by an alternating magnetic field over the gate insulating film 108. The semiconductor layer 130 having a triple layer structure formed of an ohmic contact layer 125 of impurity amorphous silicon is formed.

In addition, source and drain electrodes 144 and 146 are spaced apart from each other on the ohmic contact layer 125 of the semiconductor layer 130 having such a structure, and the source electrode formed on the semiconductor layer 130 A pixel line P is defined to cross the gate line (not shown), and a data line (not shown) is formed on the gate insulating layer 108. In this case, the gate electrode 105, the gate insulating layer 108, the first and second silicon layers 114 and 119, the ohmic contact layer 125, and the source and drain electrodes 144 and 146 are formed of a thin film transistor Tr. To achieve.

In addition, a passivation layer 150 having a drain contact hole 153 exposing a part of the drain electrode 146 over the source and drain electrodes 144 and 146 and a data line (not shown) is formed. A pixel electrode 160 is formed on the layer 150 to contact the drain electrode 146 through the drain contact hole 153.

In the array substrate 101 for a liquid crystal display device having such a structure, in particular, the thin film transistor Tr having the first and second silicon layers 114 and 119 and the ohmic contact layer 125 is the first silicon layer 114. The pure amorphous silicon is crystallized into polysilicon through an alternating current self crystallization process in which a) is exposed to an alternating magnetic field in a vacuum chamber having a specific temperature, and the mobility characteristics are significantly improved.

In this case, the second silicon layer 119 of pure amorphous silicon formed on the crystallized first silicon layer 114 has a much higher mobility due to the polysilicon characteristic to further increase the off current I _off . This is caused by an increase in leakage current at the boundary between the ohmic contact layer 125 containing impurities and the crystallized first silicon layer 114. Therefore, in order to reduce the increase in leakage current, the second silicon layer 119 of pure amorphous silicon is formed.

A method of manufacturing an array substrate for a liquid crystal display device according to a first embodiment of the present invention having such a structure will be described.

4A to 4G are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display device according to a first exemplary embodiment of the present invention.

First, as shown in FIG. 4A, a chromium (Cr) or molybdenum (Mo) is deposited on a transparent insulating substrate 101 by using a sputtering device, for example, a metal having a relatively high melting point, and then patterned. The gate electrode 105 is connected to the gate electrode 105 to form a gate wiring (not shown) extending in one direction.

Subsequently, the substrate 101 on which the gate wiring (not shown) and the gate electrode 105 are formed is moved to the chamber 190 of a chemical vapor deposition (CVD) apparatus, and then, depending on the material to be deposited. In order to form a gas atmosphere of a kind and form a silicon nitride (SiNx) layer, for example, a mixed gas atmosphere of SiH ₄ / N ₂ or a SiH ₄ / NH ₃ mixed gas is formed, and a silicon oxide (SiO ₂ ) layer is formed. In order to form, after forming a SiH ₄ / N ₂ O mixed gas atmosphere, by forming a plasma in the chamber 190, silicon oxide (SiO ₂ ) or on a substrate 101 on which the gate electrode 105 is formed; A gate insulating film 108 of silicon nitride (SiNx) is formed over the entire surface.

Next, as shown in FIG. 4B, after the gate insulating film 108 is formed, the mixed gas atmosphere for forming the above-described gate insulating film 108 in the same chamber 190 is a mixed gas of SiH ₄ / H ₂ . After changing to the atmosphere, a plasma is formed in the chamber 190 to form a first pure amorphous silicon layer 112 having a first thickness t1 of about 1200 to 2000 mW over the gate insulating film 108.

Next, as shown in FIG. 4C, the substrate 101 on which the first pure amorphous silicon layer (112 in FIG. 4C) of the first thickness t1 is formed is placed in the chamber of the chemical vapor deposition apparatus (190 in FIG. 4B). In the self-crystallization process chamber 193.

The self-crystallization process chamber 193 may form a high temperature atmosphere of about 500 ° C. to 1000 ° C., and more specifically, centers a stage (not shown) in which the substrate 101 is raised in the chamber 193. It is a feature that an alternating magnetic field can be formed above and below it.

After placing the substrate 101 on which the first pure amorphous silicon layer (112 of FIG. 4C) is formed on a stage (not shown) in the self-crystallization process chamber 193 having this characteristic, the atmosphere in the chamber 193 is Is heated to 700 ° C. to 750 ° C., and then a magnetic field (AMF) perpendicular to the substrate 101 is applied in this heated atmosphere.

At this time, the surface of the substrate 101 is exposed to the magnetic field for 1 to 60 seconds in such a manner that the AC magnetic field generating device 195 positioned above and below the substrate 101 performs a linear reciprocating motion. It is preferable. In other words, the first pure amorphous silicon layer 112 (in FIG. 4C) is exposed to an alternating magnetic field in a scan form. When the process proceeds, the first pure amorphous silicon layer 112 (in FIG. 4C) is crystallized to be changed to the polysilicon layer 113.

When explaining the principle of alternating current self-crystallization, the main energy source of the crystallization is heat, the alternating magnetic field plays an auxiliary role. At this time, a current is induced inside the pure amorphous silicon layer by the alternating magnetic field, and the joule heat is generated by the induced internal current to accelerate the crystallization, and by applying the force to move the atoms by the alternating magnetic field It will promote crystallization.

The polysilicon layer 113 formed by the alternating current self-crystallization process has a mobility of 20 cm 2 / V · s to 30 cm 2 / V · s, which is about 0.1 cm 2 / V · s to 1 cm 2 / V · s. It can be seen that it is several tens to several hundred times that of the pure amorphous silicon layer having mobility (112 of FIG. 4C).

The process of crystallizing by exposing to an alternating magnetic field in such a high temperature atmosphere is called alternating magnetic field crystallization (AMFC).

During the AMFC process, although the substrate 101 is exposed to a high temperature of about 700 ° C. to 750 ° C. even though it is a very short time (less than 1 minute), deformation of the substrate 101 may be more precisely caused by shrinkage. Before the step of forming a gate electrode 105 and a gate wiring (not shown) having a state in which nothing is formed on the substrate 101 in order to prevent an influence on a later process by deformation, After the step of further heat-treating the substrate in a high temperature atmosphere of about 700 ℃ to 750 ℃ it is preferable to proceed with the AMFC process, wherein the heat treatment is carried out by appropriately adjusting the heating and temperature to 30 to 60 minutes It is preferable.

Next, as shown in FIG. 4D, the substrate 101 having undergone the AMFC process is moved back into the chamber 190 of the chemical vapor deposition apparatus in the self-crystallization process chamber (193 of FIG. 4C), and then the chemical vapor phase The second pure amorphous silicon layer 118 on the polysilicon layer 113 is formed on the polysilicon layer 113 by forming a plasma after forming the atmosphere in the chamber 190 of the deposition apparatus in a mixed gas atmosphere of SiH ₄ / H ₂ . It is formed to have a thickness.

Subsequently, after changing the atmosphere in the chamber 190 to the mixed gas atmosphere of SiH ₄ / PH ₃ / H ₂ , the plasma is formed to impurity amorphous silicon layer 123 over the second pure silicon layer 118. It is formed to have a thickness of about 300 kPa to 500 kPa.

Next, as shown in FIG. 4E, a mask process is performed on the substrate 101 on which the impurity amorphous silicon layer 123 is formed, thereby forming the impurity amorphous silicon layer (123 of FIG. 4D) and the second pure amorphous material thereunder. The silicon layer (118 in FIG. 4D) and the polysilicon layer (113 in FIG. 4D) are simultaneously patterned to form the first silicon layer 114 of polysilicon, the second silicon layer 119 of pure amorphous silicon, and the second silicon An ohmic contact pattern 124 in a connected state of impurity amorphous silicon is formed on the layer.

Next, as shown in FIG. 4F, a source spaced apart from each other on the ohmic contact pattern (124 of FIG. 4E) by depositing and patterning a second metal material over the ohmic contact pattern (124 of FIG. 4E) in the connected state. Drain electrodes 144 and 146 and a data line (not shown) are formed on the gate insulating layer 108 and connected to the source electrode 144 and intersect the gate line (not shown).

Thereafter, dry etching is performed using the source and drain electrodes 144 and 146 spaced apart from each other as a mask to remove the ohmic contact patterns 124 of FIG. 4E exposed between the source and drain electrodes 144 and 146, respectively. The ohmic contact layer 125 is formed below the source and drain electrodes 144 and 146 and is separated.

As shown in FIG. 4G, an inorganic insulating material, such as silicon nitride (SiNx) or the like, may be formed on the substrate 101 on which the ohmic contact layer 125 is spaced apart from the source and drain electrodes 144 and 146. By depositing and patterning silicon oxide (SiO ₂ ), a protective layer 150 having a drain contact hole 153 exposing a portion of the drain electrode 146 is formed.

Then, in this state, the substrate is moved to a chamber of a plasma generator (eg, a chemical vapor deposition apparatus), and then a hydrogenation process is performed to expose the plasma for about 300 seconds to 600 seconds. In this case, the hydrogenation process can be omitted.

The drain contact hole is then deposited by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the passivation layer 150 having the drain contact hole 153. By forming the pixel electrode 160 in contact with the drain electrode 146 through 153, the array substrate 101 for liquid crystal display device having excellent mobility characteristics according to the first embodiment of the present invention can be completed. .

≪ Embodiment 2 >

The array substrate for a liquid crystal display device according to the second embodiment of the present invention is characterized in that not only mobility characteristics but also transfer curve characteristics of the thin film transistor are improved.

Although the thin film transistor having the AMFC-treated semiconductor layer formed on the array substrate for a liquid crystal display according to the first embodiment is improved in mobility characteristics, a curved graph showing a drain current change with respect to a gate voltage change is a switching element. Since the curve is formed smoothly in the region where the operation is possible, it is difficult to use as a switching element substantially.

Accordingly, the second embodiment of the present invention provides an array substrate for a liquid crystal display device and a method of manufacturing the same, wherein the transfer curve characteristics are also improved in addition to the mobility characteristics.

5 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to the present invention. At this time, the structure according to the second embodiment is different only from the structure of the semiconductor layer compared to the first embodiment described above, and other components are the same as the first embodiment described above, only the structure of the semiconductor layer will be described and other configurations The description of the elements is omitted.

As shown, pure silicon is made of polysilicon over the gate insulating film 208 and crystallized by AMFC treatment, and has a first thickness t1 and overlaps the source and drain electrodes 244 and 246. Located between the first region 214a and the first region 214a, that is, corresponding to the spaced apart regions (hereinafter, referred to as channel regions chA) of the source and drain electrodes 244 and 246. A first silicon layer 214 formed of a second region 214b having a second thickness t2 that is thinner than one thickness t1 is formed.

In addition, a second silicon layer 220 formed of pure amorphous silicon spaced apart from each other in correspondence with the first region 214a on the first silicon layer 214 has a thickness of about 300 kPa to about 500 kPa. The second contact layer 214b of the first silicon layer 214 is exposed on the second silicon layer 220 spaced apart from each other, and the ohmic contact layer 225 made of impurity amorphous silicon has a thickness of about 300 to 500 mW. It has and is formed.

In this case, the first and second silicon layers 214 and 220 and the ohmic contact layer 225 formed thereon form a semiconductor layer 231 having a triple layer structure, and the upper portion of the semiconductor layer 231 having such a structure. More precisely, source and drain electrodes 244 and 246 spaced apart from each other are formed on the ohmic contact layers 225 spaced apart from each other.

In the semiconductor layer 231 having the above-described structure, the first thickness t1 is 1200 kPa to 2000 kPa, and the second thickness t2 is 800 kPa to about 200 kPa to 400 kPa thinner than the first thickness t1. It is characterized by being 1800Å.

The first region 214a overlapping the source and drain electrodes 244 and 246 in the first silicon layer 214 made of polysilicon by being crystallized by an AMFC process has a first thickness t1 and these The second region 214b exposed in correspondence to the separation region between the two electrodes 244 and 246 is etched from 200 s to 400 s from the surface of the first region 214a to be 200 s to 400 s than the first thickness t1. It is formed with a second thickness t2 which is moderately thin.

Therefore, the contaminated portion of the manufacturing process (the first silicon layer 214 and the second silicon layer 220 are moved between chambers in order to perform the AC self-crystallization process, so that the contaminated portion may occur). Although not shown structurally in the above, the hydrogenation treatment is further performed so that at the interface between the first silicon layer 214 and the gate insulating film 208 and at the interface between the first silicon layer 214 and the second silicon layer 220. It is judged that the transfer curve characteristics are finally improved by improving the characteristics.

In addition, forming the first silicon layer 214 to have a first thickness t1 and a second thickness t2, respectively, is also an experimentally optimized result. After forming the first silicon layer 214 to the first thickness (t1, 1200Å to 2000Å) and etch it about 200Å to 400Å so that the second region 214b has a second thickness (t2, 800Å to 1800Å) This resulted in much better transfer curve characteristics compared to the case of etching more or less than this.

Therefore, the thicknesses t1 and t2 of the first silicon layer 214 may also be referred to as large feature configurations.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to a second embodiment of the present invention will be described. In this case, the steps up to the formation of the gate insulating film are the same as in the first embodiment, and thus description thereof is omitted.

 6A through 6G are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

First, as shown in FIG. 6A, after the gate insulating film 208 is formed in the chamber 290 of the chemical vapor deposition apparatus, the atmosphere in the chamber 290 is changed to a mixed gas atmosphere of SiH ₄ / H ₂ . By forming a plasma in the chamber 290, a first pure amorphous silicon layer 212 having a first thickness t1 of about 1200 μs to 2000 μs is formed on the gate insulating layer 208.

Next, as shown in FIG. 6B, the substrate 201 having the first pure amorphous silicon layer 212 having the first thickness t1 is placed in the chamber 290 of FIG. 6A. After moving to the self crystallization process chamber 293, the atmosphere in the self crystallization process chamber 293 is warmed to 700 ° C. to 750 ° C., and then an alternating magnetic field perpendicular to the substrate 201 is generated in this warmed atmosphere. 1 second to 60 seconds.

At this time, it is preferable to expose the substrate 201 to the alternating magnetic field (AMF) in such a manner that the alternating magnetic field generator 295 located above and below the substrate 201 performs a linear reciprocating motion. In other words, the first pure amorphous silicon layer (212 of FIG. 6A) on the substrate 201 is exposed to an alternating magnetic field (AMF) in a scan form. In this process, the first pure amorphous silicon layer (212 of FIG. 6A) is crystallized to be changed to the polysilicon layer 213.

Since the substrate 201 is exposed to a high temperature of about 700 ° C. to 750 ° C. during the AMFC process, deformation (particularly shrinkage) may occur, so that the substrate ( Before forming the gate electrode 205 and the gate wiring (not shown) on the 201), the heating temperature is further changed by changing the heating temperature for about 30 to 60 minutes in a high temperature atmosphere of about 700 to 750 ° C. It is preferable to proceed with the AMFC process.

Next, as shown in FIG. 6C, the substrate 201 having undergone the AMFC process is moved back into the chamber 290 of the chemical vapor deposition apparatus in the self crystallization process chamber (293 of FIG. 6B), and then the chemical vapor phase The second pure amorphous silicon layer 218 on the polysilicon layer 213 has a thickness of 300 kPa to 500 kPa by changing the atmosphere in the chamber 290 of the deposition equipment to a mixed gas atmosphere of SiH ₄ / H ₂ and then forming a plasma. Form to have.

Subsequently, after changing the atmosphere in the chamber 290 to the mixed gas atmosphere of SiH ₄ / PH ₃ / H ₂ , the plasma is formed to impurity amorphous silicon layer 223 over the second pure silicon layer 218. It is formed to have a thickness of about 300 kPa to 500 kPa.

Next, as shown in FIG. 6D, a mask process is performed on the substrate 201 on which the impurity amorphous silicon layer 223 of FIG. 6C is formed, thereby forming the impurity amorphous silicon layer 223 of FIG. 6C and the lower portion thereof. 2 The pure amorphous silicon layer (218 in FIG. 6C) and the polysilicon layer (213 in FIG. 6C) are simultaneously patterned to form the first silicon layer 214 of polysilicon and the second silicon layer 219 of pure amorphous silicon thereon. And an ohmic contact pattern 224 connected to the impurity amorphous silicon on the second silicon layer 219.

Next, as shown in FIG. 6E, the second metal material is deposited on the ohmic contact pattern 224 of FIG. 6D and patterned, thereby spaced apart from each other on the ohmic contact pattern 224 of FIG. 6D. Source and drain electrodes 244 and 246 and a data line (not shown) connected to the source electrode 244 and intersecting the gate line (not shown) on the gate insulating layer 208.

Thereafter, dry etching is performed using the source and drain electrodes 244 and 246 spaced apart from each other as a mask, and the ohmic contact pattern 224 of FIG. 6D is exposed between the source and drain electrodes 244 and 246. The first silicon layer of the first thickness t1 exposed by removing the second silicon layer (219 of FIG. 6D) and further dry etching to remove the second silicon layer (219 of FIG. 6D) is removed. 214 has a second thickness t2 of about 800 kPa to about 1800 kPa by removing the thickness of about 200 kPa to about 400 kPa based on the exposed surface.

In this case, the first region 214a, the source and drain of the first silicon layer 214 that is not removed by the source and drain electrodes 244 and 246 and maintains the first thickness t1, which is an initial thickness, is maintained. The first silicon layer 214 having a second thickness t2 that is exposed between the electrodes 244 and 246 and thinned is defined as a second region 214b.

In addition, at this time, the ohmic contact pattern 224 of FIG. 6D and the second silicon layer 219 of FIG. 6E are partially removed, and the ohmic contact layer 225 and the second silicon layer are separated from each other. 220 is formed.

Next, as shown in FIG. 6F, the substrate 201 having the first silicon layer 214 of polysilicon divided into the first and second regions 214a and 214b by varying the thicknesses t1 and t2, respectively. The plasma generator 299, for example, is moved to a chamber of a chemical vapor deposition apparatus, and then a hydrogenation process is performed to expose the plasma to the plasma for about 300 to 600 seconds in a hydrogen (H ₂ ) gas atmosphere.

The surface becomes contaminated by moving from the chamber of the chemical vapor deposition apparatus to the self-crystallization chamber for the progress of the AMFC, and in this state, the second amorphous silicon layer is formed, thereby deteriorating these interfacial properties. In the second embodiment of the present invention, the first silicon layer 214 and the second silicon layer 219 are etched by removing the surface of the region forming the channel, that is, the second region 214b, and removing the surface thereof. The damaged or contaminated portions at the interface between the interface and the first silicon layer 214 and the gate insulating film 208 are stabilized or removed to some extent, thereby improving the interface characteristics.

Therefore, in the case of the array substrate 201 having the semiconductor layer 231 having such a structure, the mobility characteristics are excellent and also the transfer curve characteristics are good, so that it can serve as a switching element or a driving element. do.

Next, after the hydrogenation process is completed, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the source and drain electrodes 244 and 246, as shown in FIG. 6G. The protective layer 250 having the drain contact hole 253 exposing a part of the drain electrode 246 is formed by patterning the patterned portion.

The drain contact hole is then deposited by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the passivation layer 250 having the drain contact hole 253. By forming the pixel electrode 260 in contact with the drain electrode 246 through 253, the array substrate 201 for liquid crystal display device having excellent mobility characteristics and transfer curve characteristics according to the second exemplary embodiment of the present invention is obtained. I can complete it.

In the case of the AMFC-treated array substrate for a liquid crystal display device having the polysilicon semiconductor layer according to the first and second embodiments described above, the source and drain electrodes of the cross-sectional structure except for the region where the channel is formed are lower in the cross-sectional structure. Although it has been shown that the structure completely covers the ohmic contact layer and the first and second silicon layers located on the other end, as shown in FIGS. 7A and 7B as modifications, the other ends other than the ends facing each other are shown. For example, the ends of the semiconductor layers 330 and 431 formed of a lower multilayer may be formed to coincide with each other. In this case, a wiring pattern semiconductor pattern (not shown) having the same structure as that of the semiconductor layers 330 and 431 disposed below the source electrodes 344 and 444 is formed below the data wiring (not shown).

In the case of the liquid crystal display array substrates 301 and 401 according to the modified example, other components are the same as those of the first and second embodiments described above, and thus, further description thereof will be omitted.

The cross-sectional structure of the source and drain electrodes and the underlying semiconductor layer is manufactured through a five mask process in which the semiconductor layer and the source and drain electrodes are respectively patterned through different mask processes, or the semiconductor layer, the source and drain electrodes May be produced by a four mask process patterning through one mask process including diffraction exposure or halftone exposure, which is a semiconductor layer structure under the source and drain electrodes except for the channel region. As long as it has a triple layer structure (a first silicon layer of polysilicon having a first and a second region / a second silicon layer of pure amorphous silicon / an ohmic contact layer of amorphous silicon mixed with impurities), it will fall within the scope of the present invention. .

The manufacturing method of the array substrate for a liquid crystal display device according to the modified example of the second embodiment of the present invention (see FIG. 7B) according to the four-mask process is simply different from the manufacturing method shown in the second embodiment. It demonstrates with reference.

8A through 8C are cross-sectional views illustrating manufacturing processes of one pixel area of an array substrate for a liquid crystal display according to a modification of the second exemplary embodiment of the present invention.

First, as shown in FIG. 8A, the process steps shown in the second embodiment are carried out to form a first pure amorphous silicon layer (not shown) having a first thickness (1200 Å to 2000 AM), followed by an AMFC process. Crystallization is performed by the polysilicon layer 413.

Thereafter, a second pure amorphous silicon layer 418 and an impurity amorphous silicon layer 423 are sequentially formed on the polysilicon layer 413.

Thereafter, a second metal material is deposited on the impurity amorphous silicon layer 423 to form a metal layer 438.

Next, by forming a photoresist layer on the metal layer 438 and performing a diffraction exposure or a halftone exposure using an exposure mask, a third thickness t3 corresponds to a region where a channel is to be formed corresponding to the gate electrode 205. A fourth photoresist pattern 481a formed of the first photoresist pattern 481a, and corresponding to a portion in which source and drain electrodes (not shown) spaced apart from the data line (not shown) are formed. A second photoresist pattern 481b of thickness t4 is formed.

As shown in FIG. 8B, the metal layer 438 of FIG. 8A, the impurities below and the second pure amorphous silicon layer 423 of FIG. 8A exposed outside the first and second photoresist patterns 481a and 481b. And 418) and the crystallized polysilicon layer (413 in FIG. 8A) by successively removing the data wiring (not shown), and the semiconductor pattern (not shown) having a triple layer structure under the data wiring (not shown), A source drain pattern 439 in a connected and connected state and a semiconductor pattern 430 having a triple layer structure are formed below the source drain pattern 439.

Next, as shown in FIG. 8C, the ashing is performed to remove the first photoresist pattern (481a in FIG. 8B) having a third thickness (FIG. 8B t3) corresponding to the channel region chA. The source drain pattern (439 of FIG. 8B) in the connected state is exposed.

Subsequently, the source and drain electrodes 444 and 446 spaced apart from each other are formed by etching and removing the exposed source and drain patterns 439 of FIG. 8B to the outside of the second photoresist pattern 481b. Subsequently, the impurity amorphous silicon pattern 424 of FIG. 8B and the second pure amorphous silicon pattern 419 below are exposed between the two electrodes 444 and 446 using the source and drain electrodes 444 and 446 as masks. And the ohmic contact layer 424 and the second silicon layer 420 and the first region 414a and the second thickness t1 spaced apart from each other by dry etching the polysilicon pattern 414 of FIG. 8B. A semiconductor layer 431 composed of a first silicon layer 414 of polysilicon having a second region 414b of thickness t2 is formed.

In this case, the source and drain electrodes 441 and 446 and the lower semiconductor layer 431 are formed at the same time through a single mask process as described above, so that their ends coincide.

Since the process proceeds in the same manner as the manufacturing method described with reference to FIGS. 6E to 6G of the first embodiment, the description thereof will be omitted.

The array substrate for a liquid crystal display device according to the present invention has an effect of improving the mobility characteristics by several tens to several hundred times by AMFC treatment of a pure amorphous silicon layer.

Therefore, the thin film transistor having the AMFC-treated semiconductor layer can be used as a driving device as well as a switching device. Since the external driving circuit is not provided separately, the cost can be reduced and the integration of the driving device can be increased. As a result, the product can be made compact.

In addition, in the conventional method for manufacturing an array substrate for a liquid crystal display device using polysilicon, a 7-9 mask process is typically performed by doping or the like, but the product is completed as described above. In the case of an array substrate, polysilicon is used as a semiconductor layer and does not require a separate process such as doping, and thus a product can be completed by a 4-5 mask process, thereby reducing productivity.

Claims (22)

A substrate; A gate electrode formed on the substrate; A gate insulating film formed over the gate electrode; A first silicon layer formed of crystallized polysilicon sequentially stacked over the gate insulating film, the first silicon layer having a first region of a first thickness and a second region of a second thickness, and a second silicon layer made of pure amorphous silicon; A semiconductor layer having a triple layer structure composed of an ohmic contact layer of impurity amorphous silicon spaced apart; Source and drain electrodes formed on and in contact with the ohmic contact layer, respectively And a plurality of pixel electrodes. The method of claim 1, A protective layer formed by exposing the drain electrode over the source and drain electrodes; A pixel electrode formed in contact with the exposed drain electrode on the passivation layer Array substrate for a liquid crystal display device further comprising. The method of claim 2, A gate wiring connected to the gate electrode and formed; A data line connected to the source electrode and crossing the gate line Array substrate for a liquid crystal display device further comprising. The method of claim 1, And the first thickness and the second thickness are equal to 1200 mW to 2000 mW. The method of claim 1, And the first thickness has a larger value than the second thickness, and wherein the second region corresponds to a spaced area of the ohmic contact layer. 6. The method of claim 5, And the first thickness is 1200 kPa to 2000 kPa, and the difference between the first thickness and the second thickness is 200 kPa to 400 kPa. 6. The method of claim 5, And the second silicon layer has the same shape as that of the ohmic contact layer. The method according to claim 1 or 5, And the source and drain electrodes are formed to completely cover both ends of the semiconductor layer to their side surfaces. The method according to claim 1 or 5, And the source and drain electrodes and both ends of the semiconductor layer coincide with each other. The method according to claim 1 or 5, And the second silicon layer and the ohmic contact layer have a thickness of 300 mW to 500 mW. Forming a gate electrode on the substrate; Forming a gate insulating film over the gate electrode; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing alternating magnetic field crystallization; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer on the polysilicon layer; Simultaneously forming the impurity amorphous silicon layer, the second pure amorphous silicon layer, and the polysilicon layer to form a sequential first and second silicon layer and an ohmic contact layer on the gate electrode; Forming source and drain electrodes spaced apart from each other on the ohmic contact layer; Removing the ohmic contact layer exposed between the source and drain electrodes to form an ohmic contact layer spaced apart from each other; And a plurality of pixel electrodes formed on the substrate. Forming a gate electrode on the substrate; Forming a gate insulating film over the gate electrode; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer into a polysilicon layer by performing alternating magnetic field crystallization; Sequentially forming a second pure amorphous silicon layer and an impurity amorphous silicon layer on the polysilicon layer; Forming a metal layer over the impurity amorphous silicon layer; Source and drain electrodes spaced apart from each other by simultaneously patterning the metal layer, the impurity, the second pure amorphous silicon layer, and the polysilicon layer, an ohmic contact layer spaced apart from each other sequentially, and a second and a first silicon layer. Steps to And a plurality of pixel electrodes formed on the substrate. 13. The method according to claim 11 or 12, The alternating magnetic field crystallization is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C. A method of manufacturing an array substrate for a liquid crystal display device. 13. The method of claim 12, And the alternating current self crystallization is performed such that an alternating current magnetic field generating device is linearly reciprocated horizontally and positioned above and below the substrate with respect to the substrate located in the chamber. 13. The method of claim 12, The alternating current self crystallization is performed for 1 second to 60 seconds. 13. The method according to claim 11 or 12, Dry etching is performed to completely remove the second silicon layer exposed between the spaced apart ohmic contact layers and to have a second thickness thinner than the first thickness with respect to the first silicon layer thereunder. A method of manufacturing an array substrate for a liquid crystal display further comprising the step of. 17. The method of claim 16, And the dry etching is performed such that a difference between the first thickness and the second thickness is 200 kPa to 400 kPa. 17. The method of claim 16, And performing a hydrogenation process of exposing the plasma to a hydrogen (H ₂ ) atmosphere after performing the dry etching. The method of claim 18, The hydrogenation process is a manufacturing method of an array substrate for a liquid crystal display device, characterized in that 300 seconds to 600 seconds. 13. The method according to claim 11 or 12, Forming a protective layer over the source and drain electrodes to expose the drain electrode; Forming a pixel electrode in contact with the exposed drain electrode over the passivation layer Method of manufacturing an array substrate for a liquid crystal display device further comprising. 13. The method according to claim 11 or 12, The forming of the gate electrode may further include forming a gate wiring connected to the gate electrode, and the forming of the source and drain electrodes may include: a data wiring connected to the source electrode and crossing the gate wiring; The method of manufacturing an array substrate for a liquid crystal display device further comprising the step of forming a. 13. The method according to claim 11 or 12, Before forming the gate electrode, The method of manufacturing an array substrate for a liquid crystal display device further comprising the step of heat-treating the substrate for 30 to 60 minutes in an atmosphere of 700 ℃ to 750 ℃.

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