KR20080085276A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An array substrate for an LCD(Liquid Crystal Display) and a method for manufacturing the same are provided to crystallize an amorphous silicon layer through a simple process, thereby improving the electric performance of a thin film transistor. A gate electrode(205) and a gate line are formed on a substrate(201). A gate-insulating layer(208) is formed on the gate electrode and the gate line. A first intrinsic amorphous silicon layer of a first thickness is formed on the gate-insulating layer. The first intrinsic amorphous silicon layer is crystallized into a polycrystalline silicon layer(213). The polycrystalline silicon layer is pattern-etched to form a first silicon layer. A second intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer, and a metal layer are sequentially formed over the first silicon layer. The metal layer, the impurity-doped amorphous silicon layer, and the second intrinsic amorphous silicon layer are pattern-etched to form a data line, a source electrode, a drain electrode, an ohmic contact layer, and a second silicon layer completely covering an end of the first silicon layer. A passivation layer is formed over the data line, the source electrode, and the drain electrode while the passivation layer exposes the drain electrode. A pixel electrode is formed on the passivation layer while the pixel electrode is contacted with the pixel electrode. The first intrinsic amorphous silicon layer is crystallized by alternating magnetic field crystallization.

Description

Array substrate for liquid crystal display device and method of fabricating the same

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of a portion including a thin film transistor in one pixel area of an array substrate of a conventional liquid crystal display device.

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

4 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

5A through 5H are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

201: substrate 205: gate electrode

208: gate insulating film 214: first silicon layer (of polysilicon)

220: second silicon layer (of pure amorphous silicon)

225: ohmic contact layer 244: source electrode

246: drain electrode 250: protective layer

253: drain contact hole 260: pixel electrode

ch: Channel area P: Pixel area

Tr: Thin Film Transistor TrA: Switching Area

The present invention relates to a liquid crystal display device, and more particularly, to a structure of a thin film transistor formed in each pixel region of an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. I am getting it.

Referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, a structure of the liquid crystal display device will be described. As illustrated, the array substrate 10 and the color filter substrate 20 are disposed with the liquid crystal layer 30 interposed therebetween. The face-to-face bonded structure includes a plurality of gate wirings 14 and a data wiring (10) arranged vertically and horizontally on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. 16, a thin film transistor T is provided at an intersection point of the two wires 14 and 16 so as to be connected one-to-one with the pixel electrode 18 provided in each pixel region P. As shown in FIG.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

In addition, a back-light is provided on the outer surface of the array substrate to supply light. The on / off signals of the thin film transistor T are sequentially scanned by the gate wiring 14. When the image signal of the data wiring 16 is transmitted to the pixel electrode 18 of the pixel region P applied and selected, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the light transmittance is changed. Branch images can be displayed.

In the liquid crystal display having the above structure, the most important component is a thin film transistor which is formed for each pixel region and is connected to the gate and data lines and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode. Can be.

The cross-sectional structure of the thin film transistor, which serves as such a switching element, will be described with reference to FIG.

2 is a cross-sectional view of a portion in which a thin film transistor is formed in an array substrate of a conventional liquid crystal display.

The gate electrode 60 is formed on the transparent insulating substrate 59, and the gate insulating layer 68 is formed on the entire surface of the gate electrode 60. The semiconductor layer 70 includes an active layer 70a made of pure amorphous silicon on the gate insulating layer, and an ohmic contact layer 70b made of amorphous silicon containing impurities in a form spaced apart from each other. ) Is formed.

In addition, the ohmic contact layer 70b formed to expose the active layer 70a below and spaced apart from each other is in contact with the ohmic contact layer 70b and is spaced apart from each other to correspond to the gate electrode 60. The source electrode 76 and the drain electrode 78 are formed while exposing the layer 70a.

The thin film transistor Tr includes the gate electrode 60, the gate insulating film 68, and the source and drain electrodes 76 and 78 spaced apart from each other, and are sequentially stacked on the substrate 59. )

A passivation layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed on the front surface of the thin film transistor Tr having such a structure, and each passivation layer 86 is formed on the passivation layer 86. A pixel electrode 88 is formed in each pixel region P to contact the drain electrode 78 through the drain contact hole 80, and the gate electrode 60 is formed on the same layer on which the gate electrode 60 is formed. ) And a data line (not shown) connected to the source electrode 76 is further formed on the same layer on which the source and drain electrodes 76 and 78 are formed. )

However, in the case of a thin film transistor which is generally configured in a conventional array substrate for a liquid crystal display device, it can be seen that the semiconductor layer uses amorphous silicon. When the semiconductor layer is formed using the amorphous silicon, the amorphous silicon ( a-Si: H) has a weak Si-Si bond and dangling bond because of its disordered atomic arrangement, which is converted into a quasi-stable state when irradiating light or applying an electric field to be used as a thin film transistor device. Stability is a problem, and the electric field effect mobility is low as 0.1 ~ 1.0 cm 2 / V · s, so that the electrical characteristics are not good, it is also a problem to use it as a device forming a drive circuit.

In order to solve the above problems, an object of the present invention is to provide an array substrate for a liquid crystal display device having a thin film transistor having excellent device performance and reliability by crystallizing amorphous silicon by a simple process and a method of manufacturing the same.

Furthermore, by significantly improving the mobility characteristics, it can be used as a driving circuit and can be driven without the attachment of an external driving circuit board, thereby reducing costs and increasing the integration of the driving device. Another aim is to make it compact.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; A gate electrode and a gate wiring formed on the substrate; A gate insulating film formed over the gate electrode and the gate wiring; The semiconductor layer is sequentially stacked on the gate insulating layer to correspond to the gate electrode, and includes a first silicon layer of polysilicon, a second silicon layer of pure amorphous silicon spaced apart from each other, and an ohmic contact layer of impurity amorphous silicon spaced apart from each other. A layer; Source and drain electrodes spaced apart from the ohmic contact layer; A data line formed over the gate insulating layer and crossing the gate line to define a pixel area; A protective layer formed on a front surface of the source and drain electrodes and the data line and in contact with an end side of each of the source and drain low electrodes and the ohmic contact layer; And a pixel electrode formed on the protective layer in contact with the drain electrode in the pixel area.

In this case, the second silicon layer is formed to completely cover the end and the side of the first silicon layer located below the second silicon layer and the ohmic contact layer is formed so that the ends thereof vertically Is characteristic.

In addition, the protective layer is characterized in that the drain contact hole for exposing the drain electrode is formed.

In addition, the portion of the first silicon layer overlapping with the source and drain electrodes has a first thickness, and other regions have a second thickness thinner than the first thickness, and the first thickness is 1200 Å to 2000 Å. Wherein the second thickness is 1000 kPa to 1800 kPa.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes the steps of forming a gate electrode and a gate wiring on the substrate; Forming a gate insulating film over the gate electrode and the gate wiring; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer with a polysilicon layer; Patterning the polysilicon layer to form a first silicon layer; Sequentially forming a second pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer over the patterned first silicon layer; Patterning the metal layer, the impurities under it, and the second pure amorphous silicon layer to cross the gate wiring to define a pixel region, and source and drain electrodes spaced apart from each other, and the same shape under the source and drain electrodes. Forming a second silicon layer spaced apart from each other in a form of completely covering an end of the ohmic contact layer and the first silicon layer; Forming a protective layer exposing the drain electrode over the data line and the source and drain electrodes; Forming a pixel electrode in contact with the drain electrode in the pixel area over the passivation layer.

In this case, the crystallization is characterized by performing alternating magnetic field crystallization, the alternating magnetic field crystallization is characterized in that it proceeds in a chamber having an atmosphere of 700 ℃ to 750 ℃. In addition, the alternating magnetic field crystallization, the alternating magnetic field generating device with respect to the substrate located in the chamber is in the form of a linear reciprocating motion horizontally and linearly up and down the substrate, for 1 to 60 seconds It is characterized by progress.

In addition, the source and drain electrodes spaced apart from the data line, the ohmic contact layer having the same shape below the source and drain electrodes, and the second silicon layer spaced apart from each other in a form completely covering the ends of the first silicon layer. The forming of the method may include forming a first photoresist pattern having a second thickness over the metal layer and a second photoresist pattern having a third thickness thinner than the second thickness; A metal layer exposed to the outside of the first and second photoresist patterns, impurities and a second pure amorphous silicon layer under the first and second photoresist patterns may be removed to form a source drain pattern in a connected state with the data line; Sequentially forming an impurity and a pure amorphous silicon pattern having the same shape; Performing ashing to remove the second photoresist pattern of the third thickness; Forming the source and drain electrodes spaced apart from each other by etching a central portion of the source drain pattern exposed by removing the second photoresist pattern; Forming the ohmic contact layers spaced apart from each other by removing the impurity amorphous pattern exposed between the source and drain electrodes; And forming the second silicon layers spaced apart from each other by removing the pure amorphous silicon pattern exposed between the ohmic contact layers.

The method may further include performing dry etching to cause the first silicon layer region exposed between the spaced apart second silicon layers to have a fourth thickness thinner than the first thickness, wherein the dry etching is performed. Is characterized in that it proceeds so that the difference between the first thickness and the fourth thickness is 200 kPa to 400 kPa, and after the dry etching, further comprising the step of performing a hydrogenation process to expose the plasma in a hydrogen (H ₂ ) atmosphere do.

The thin film transistor according to the present invention includes a gate electrode; A gate insulating film formed over the gate electrode; A semiconductor layer sequentially stacked on the gate insulating layer corresponding to the gate electrode, and including a first silicon layer of polysilicon, a second silicon layer of pure amorphous silicon spaced apart from each other, and an ohmic contact layer of impurity amorphous silicon spaced apart from each other and; Source and drain electrodes spaced apart from the ohmic contact layer; And a protective layer formed in contact with an end of the source and drain electrodes and an end of the ohmic contact layer.

In this case, the second silicon layer is formed to completely cover the end and the side of the first silicon layer located below the second silicon layer and the ohmic contact layer is formed so that the ends thereof vertically Is characteristic.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

As shown, in the case of the array substrate 101 for a liquid crystal display device according to the present invention, a gate electrode 105 and a gate wiring connected thereto are formed on the transparent insulating substrate 101. A gate insulating layer 108 is formed on the gate line and the gate electrode 105.

The first silicon layer 114 of polysilicon and the second silicon layer of pure amorphous silicon spaced apart from each other above the gate insulating film 108 are characterized in that pure amorphous silicon is crystallized by an alternating magnetic field. 119 and a semiconductor layer 130 having a triple layer structure formed of an ohmic contact layer 125 of impurity amorphous silicon formed to be spaced apart from each other.

In addition, the first silicon layer 114 is spaced apart from each other by covering the side surface of the semiconductor layer 130 of the triple layer structure on the ohmic contact layer 125 of the semiconductor layer 130 having the triple layer structure. Source and drain electrodes 144 and 146 are formed to be exposed, and the gate insulating layer 108 is connected to the source electrode 144 formed on the triple layer semiconductor layer 130 and the gate wiring (not shown). Intersect) to define the pixel region P, and a data line 142 is formed. In this case, a triple layer semiconductor layer including the gate electrode 105, the gate insulating layer 108, the first and second silicon layers 114 and 119, and the ohmic contact layer 125, and the source and drain electrodes 144. 146 forms a thin film transistor Tr that serves as a switching element.

In addition, a passivation layer 150 having a drain contact hole 153 exposing a part of the drain electrode 146 is exposed in the pixel region P over the source and drain electrodes 144 and 146 and the data line 142. The pixel electrode 160 is formed on the passivation layer 150 to contact the drain electrode 146 through the drain contact hole 153.

In the array substrate 101 for a liquid crystal display device having such a structure, in particular, the thin film transistor Tr having the first and second silicon layers 114 and 119 and the ohmic contact layer 125 is formed of the first silicon layer ( The pure amorphous silicon is crystallized to polysilicon through an alternating current self crystallization process in which 114) is exposed to an alternating magnetic field in a vacuum chamber having a specific temperature, thereby greatly improving its mobility characteristics.

In this case, the reason for forming the second silicon layer 119 of pure amorphous silicon formed on the crystallized first silicon layer 114 is to form a first silicon layer 114 of the polysilicon, Mobility is greatly improved, but since the leakage current increases at the boundary between the ohmic contact layer 125 containing impurities and the crystallized first silicon layer 114, the off current I _off also becomes large. This is to reduce the increase in current.

However, referring to the thin film transistor Tr including the semiconductor layer 130 having the triple layer structure including the first silicon layer 114 crystallized by the exposure to the alternating magnetic field described above, the source and drain electrodes 144, 146) The first silicon layer 114 crystallized from the polysilicon also has a structure in which each side covers the one side surface of the triple layer structure semiconductor layer 130, and the source and drain electrodes 144 and 146 through the side thereof. The second silicon layer 119 of pure amorphous silicon and the ohmic contact layer 125 thereon also contact the source and drain electrodes 144 and 146.

In this case, looking at the movement of the carrier in the thin film transistor, the movement between the source electrode 144 and the drain electrode 146 of the majority of the carrier, that is, the main flow is a path (1), that is, the gate electrode ( Through the ohmic contact layer 125a formed in the channel region ch formed in the first silicon layer 114 on the 105 and the region where the source and drain electrodes 144 and 146 and the gate electrode 105 overlap each other. Although a small amount is added, it is additionally a path other than a path, i.e., a portion other than the portion where the channel region ch, the gate electrode 105, and the source and drain electrodes 144 and 146 overlap. The carrier may be moved through the region connected to the source and drain electrodes 144 and 146 through the ohmic contact layer 125 formed in the region.

Further, as indicated by 3, both ends of the first silicon layer 114 made of alternating magnetic crystallized polysilicon are also crystallized from the source electrode 144 by contacting the source and drain electrodes 144 and 146. There is a possibility that another parasitic path through which the carrier moves to the drain electrode 146 through the first silicon layer 114 may be formed.

When the parasitic paths shown in (2) and (3) occur, it is not a problem when a large electric field of the additionally generated carrier is applied, but when a weak electric field is applied, it affects the main carrier movement. Finally, since the current control by the gate electrode 105 is not performed, there is a possibility of a problem of deteriorating the characteristics of the thin film transistor Tr. In particular, there is a possibility that the deterioration of characteristics due to an increase in leakage current in the gate-off state, that is, the sub-threshold region, is further increased.

Therefore, the liquid crystal display array substrate having the more advanced structure is proposed through the second embodiment by eliminating the elements that may be a problem of the above-described liquid crystal display array substrate according to the first embodiment of the present invention.

Second Embodiment

4 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

As shown, the array substrate for a liquid crystal display device according to the second embodiment of the present invention, as shown, the gate electrode 205 and the gate wiring connected thereto on the transparent insulating substrate 201 (not shown) The gate insulating layer 208 is formed on the gate line and the gate electrode 205.

In addition, a first silicon layer 214 is formed on the gate insulating layer 208, in which pure amorphous silicon is crystallized by an alternating magnetic field, and the first silicon layer 214 is formed thereon. A second silicon layer 220 of pure amorphous silicon is formed on the second silicon layer 220 to be spaced apart from each other in a form of completely covering the side surface of the first silicon layer 214 and exposing a central portion of the second silicon layer 220. The ohmic contact layer 225 of impurity amorphous silicon is formed to be spaced apart from each other and in the same form as the second silicon layer 220. In this case, the first and second silicon layers 214 and 220 and the ohmic contact layer 225 form a semiconductor layer 230 having a triple layer structure.

In addition, an upper portion of the ohmic contact layer 225 positioned on the uppermost layer of the semiconductor layer 230 having the above-described structure has the same shape as the ohmic contact layer 225 and is spaced apart from each other. Source and drain electrodes 244 and 246 exposing 214 are formed.

Accordingly, the source and drain electrodes 244 and 246 do not extend to the side surface of the semiconductor layer 230 having the triple layer structure, and the second silicon layer 220 and the ohmic of the semiconductor layer 230 having the triple layer structure are not extended. The source and drain electrodes 244 and 246 are configured to coincide with the ends of the contact layer 225, and thus, the ohmic contact layer disposed below the components of the semiconductor layer 230 having the triple layer structure. 225) only in contact with the feature is formed.

Due to this structural feature, the thin film transistor Tr including the gate electrode 205, the gate insulating layer 208, the semiconductor layer 230 having a triple layer structure, and the source and drain electrodes 244 and 246 are components. The main path through which the current flows, i.e., the carrier moves, is the source electrode 244 indicated by ④ / the ohmic contact layer 225 / first silicon layer 214a located in a direction perpendicular to the source electrode 244. The ohmic contact layer 225 / the drain electrode 246 located in a direction perpendicular to the channel region ch / drain electrode 246 formed therein, and the parasitic paths indicated in the first embodiment other than the main path. The most characteristic feature of the second embodiment is that paths are bent at both ends of the source and drain electrodes so as not to contact the side surfaces of the ohmic contact layer and the second and first silicon layers.

On the other hand, the gate insulating layer 208 is connected to the source electrode 244 of the thin film transistor Tr and intersects with the gate wiring (not shown) to define the pixel region P, and the data wiring 240 is formed. A protective layer 250 having a drain contact hole 253 exposing the drain electrode 246 is formed on the front surface of the thin film transistor Tr having the above configuration and the data line 240. The liquid crystal according to the second exemplary embodiment of the present invention is formed by contacting the drain electrode 246 through the drain contact hole 253 in the pixel region P and forming the pixel electrode 260 on the passivation layer 250. The array substrate 201 for display devices is completed.

Hereinafter, a method of manufacturing the array substrate for a liquid crystal display device according to the second embodiment will be described.

5A through 5H are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

First, as illustrated in FIG. 5A, a metal material, for example, a metal having a relatively high melting point, is deposited on a transparent insulating substrate 201 by using a sputtering device, and then patterned by depositing chromium (Cr) or molybdenum (Mo). The gate electrode 205 is connected to the gate electrode 205 to form a gate wiring (not shown) extending in one direction.

Subsequently, the substrate 201 on which the gate wiring and the gate electrode 205 are formed is moved to the chamber 290 of a chemical vapor deposition (CVD) apparatus, and then, depending on the material to be deposited. In order to form a kind of gas atmosphere, for example, to form a silicon nitride (SiNx) layer, a mixed gas atmosphere of SiH ₄ / N ₂ or a SiH ₄ / NH ₃ mixed gas is formed, and a silicon oxide (SiO ₂ ) layer is formed. In the case of forming a SiH ₄ / N ₂ O mixed gas atmosphere, a plasma is formed in the chamber 290 to form silicon oxide (SiO ₂ ) or the like on the substrate 201 where the gate electrode 205 is formed. A gate insulating film 208 of silicon nitride (SiNx) is formed over the entire surface.

Next, as shown in FIG. 5B, after the gate insulating film 208 is formed, the mixed gas atmosphere for forming the above-described gate insulating film 208 in the same chamber 290 is a mixed gas of SiH ₄ / H ₂ . After changing to an atmosphere, a plasma is formed in the chamber 290 to form a first pure amorphous silicon layer 212 having a first thickness t1 of about 1200 to 2000 mW over the gate insulating film 208.

Next, as shown in FIG. 5C, the substrate 201 having the first pure amorphous silicon layer 212 of FIG. 5B having the first thickness t1 is disposed in the chamber of the chemical vapor deposition apparatus (290 of FIG. 5B). ) Into the self crystallization process chamber 293.

The self-crystallization process chamber 293 may form a high temperature atmosphere of about 500 ° C. to 1000 ° C., and more specifically, the self crystallization process chamber 293 may be formed around a stage (not shown) on which the substrate 201 is placed. It is characterized by being able to form an alternating magnetic field up and down.

After placing the substrate 201 having the first pure amorphous silicon layer (212 of FIG. 5B) formed on a stage (not shown) in the self crystallization process chamber 293 having such a characteristic, the atmosphere in the chamber 293. Is heated to 700 ° C. to 750 ° C. and then an alternating magnetic field (AMF) is applied to the substrate 201 in this warmed atmosphere.

In this case, as shown in the drawing, the surface of the substrate 201 is exposed to the magnetic field for 1 to 60 seconds in such a manner that the AC magnetic field generator 295 positioned above and below the substrate 201 performs a linear reciprocating motion. desirable. That is, the first pure amorphous silicon layer (212 of FIG. 5B) in a scan form is exposed to the alternating magnetic field (AMF). In this process, the first pure amorphous silicon layer (212 of FIG. 5B) is crystallized to be changed to the polysilicon layer 213.

When explaining the principle of AC self-crystallization, the main energy source of crystallization is heat, and the AC magnetic field plays an auxiliary role. At this time, a current is induced inside the pure amorphous silicon layer by the alternating magnetic field, and the joule heat is generated by the induced internal current to accelerate the crystallization, and by applying the force to move the atoms by the alternating magnetic field It will promote crystallization.

The polysilicon layer 213 formed by the alternating current self crystallization process has a carrier mobility of 20 cm 2 / V · s to 30 cm 2 / V · s in the interior thereof, and 0.1 cm 2 / V · s to 1 cm 2 / It can be seen that it is several tens to several hundred times as compared to the pure amorphous silicon layer 212 of FIG. 5B having a mobility of about V · s.

The process of crystallizing by exposing to an alternating magnetic field (AMF) in such a high temperature atmosphere is called alternating magnetic field crystallization (AMFC).

Although the substrate 201 is exposed to a high temperature of about 700 ° C. to about 750 ° C. during the AMFC process, the substrate 201 may be deformed more precisely in the substrate 201, so that shrinkage may occur more precisely. Before the step of forming the gate electrode 205 and the gate wiring (not shown) shown in FIG. After the heat treatment of the substrate 201 in a high temperature atmosphere of about 700 ° C to 750 ° C, the AMFC process may be further performed. In this case, the heat treatment may be performed for 30 minutes to 60 minutes. It is preferable to proceed with adjustment.

Next, as shown in FIG. 5D, the first silicon layer 214 is formed in the switching region TrA by patterning by patterning the polysilicon layer (213 in FIG. 5C) formed by the AMFC process. .

Next, as shown in FIG. 5E, the substrate 201 having the first silicon layer 214 of polysilicon formed in the switching region TrA is moved back to a chamber (not shown) of chemical vapor deposition equipment. A second pure amorphous silicon layer 218 is formed on the front surface of the first silicon layer 214 by forming an atmosphere in a chamber (not shown) of the chemical vapor deposition apparatus in a mixed gas atmosphere of SiH ₄ / H ₂ and then forming a plasma. It is formed to have a second thickness of about 300 ~ 500Å.

Subsequently, after changing the atmosphere in the chamber (not shown) to the mixed gas atmosphere of SiH ₄ / PH ₃ / H _2, an impurity amorphous silicon layer 223 is formed on the second pure amorphous silicon layer 218 by forming a plasma. ) Is formed to have a third thickness of about 300 kPa to 500 kPa.

Next, the substrate 201 on which the impurity amorphous silicon layer 223 is formed is moved to a sputtering device (not shown), and then sputtering is performed to form a second metal material such as aluminum (Al), aluminum alloy (AlNd), The metal layer 230 is formed on the impurity amorphous silicon layer 223 by depositing a material selected from copper (Cu), copper alloy, molybdenum (Mo), and chromium (Cr).

 Thereafter, a photoresist is formed on the second metal layer 230 to form a photoresist layer (not shown), and a diffraction exposure or halftone exposure is performed using an exposure mask (not shown) including a semi-transmissive region. By developing the exposed photoresist layer (not shown), a first photoresist pattern 281a having a fourth thickness is formed to correspond to a portion where the source and drain electrodes are to be formed in the switching region TrA. The second photoresist pattern 281b having a fifth thickness thinner than the fourth thickness is formed to correspond to the central portion of the gate electrode 205, and at the same time, the data wiring is formed corresponding to the boundary of the pixel region P. A first photoresist pattern 281a of a fourth thickness is formed. In this case, in the first photoresist pattern 281a formed in the switching region TrA, an end other than a portion connected to the second photoresist pattern 281b is located outside both ends of the first silicon layer 214. The first and second photoresist patterns 281a and 281b are formed such that the first silicon layer 214 completely overlaps the first photoresist pattern 281a and the second photoresist pattern 281b. ) Is characteristic.

Next, as shown in FIG. 5F, the metal layer 230 of FIG. 5E and the impurity amorphous silicon layer 223 below it exposed to the outside of the first and second photoresist patterns 281a and 281b. And etching and removing the pure amorphous silicon layer 218 of FIG. 5E to form a data line 240 on the gate insulating layer 208 to define the pixel region P by crossing the gate line (not shown). At the same time, a source drain pattern 237 in a connected state, an impurity amorphous silicon pattern 224, and a pure amorphous silicon pattern 219 in a sequentially connected lower portion are formed in the switching region TrA.

In this case, the impurities and the pure amorphous silicon patterns 224 and 219 are coincident with both ends thereof. In particular, the pure amorphous silicon pattern 219 has the first silicon layer 214 disposed below the side thereof, as well as the upper surface thereof. It is characterized by being completely covered.

In addition, the first dummy pattern 226 of impurity amorphous silicon and the second dummy pattern 221 of pure amorphous silicon are sequentially formed under the data line 240 due to process characteristics.

Next, as illustrated in FIG. 5G, ashing is performed on the substrate 201 on which the data line 240 and the source drain pattern (237 of FIG. 5F) in the connected state are formed. By removing the 2 photoresist pattern 281b of FIG. 5F, the center portion of the source drain pattern 237 of FIG. 5F in the connected state is exposed.

Subsequently, the source and drain patterns 237 of FIG. 5F are etched and removed between the first photoresist pattern 281a to form source and drain electrodes 244 and 246 spaced apart from each other, and subsequently, the source and drain patterns 237 and 246. And an ohmic contact layer spaced apart from each other having the same shape as the source and drain electrodes 244 and 246 by performing dry etching to remove the impurity amorphous silicon pattern 224 of FIG. 5F exposed between the drain electrodes 244 and 246. 225, and the dry etching may be further performed to remove the pure amorphous silicon pattern 219 of FIG. 5F exposed between the ohmic contact layers 225 spaced apart from each other, thereby forming the same shape as the ohmic contact layer 225. A second silicon layer 220 is formed. In this case, the first silicon layer 214 is exposed between the second silicon layers 220 spaced apart from each other.

Subsequently, even after the second silicon layers 220 are formed to be spaced apart from each other, the dry etching is further performed for a predetermined time to etch a surface of the first silicon layer 214 exposed between the second silicon layers 220. The sixth thickness t6 of the first silicon layer 214a in the region exposed between the second silicon layers 220 is formed by the first silicon layer 214b in the region covered by the second silicon layer 220. It is to be formed to be thinner 200 ~ 400Å thinner than one thickness (t1).

That is, the first thickness t1 of the first silicon layer 214b in the region overlapping the second silicon layer 220 spaced apart from each other is 1200 kPa to 2000 kPa, and corresponds to the gate electrode 205. More specifically, the sixth thickness t of the first silicon layer 214a in the region exposed between the source and drain electrodes 244 and 246 may be about 800 kPa to about 1800 kPa.

In this case, the first silicon layer 214 formed in the switching region TrA, the second silicon layer 220 and the ohmic contact layer 225 spaced apart from each other on the upper portion of the semiconductor layer 230 The semiconductor layer 230 having the triple layer structure, the gate insulating layer 208 and the gate electrode 205 disposed under the triple layer structure, and the source and drain electrodes 244 and 246 disposed thereon are formed of a thin film transistor Tr. Will be achieved.

Next, as shown in FIG. 5H, stripping or ashing the first photoresist pattern (281a of FIG. 5G) remaining on the source and drain electrodes 244 and 246 and the data line 240. After removing the thin film transistor Tr, the substrate 201 is exposed to a chamber (not shown) of a plasma generator, for example, a chemical vapor deposition apparatus, and then a hydrogen (H ₂ ) gas atmosphere. The hydrogenation process is performed to expose the plasma for about 300 seconds to 600 seconds.

Next, a protective layer 250 is formed by depositing an inorganic insulating material or applying an organic insulating material on the entire surface of the source and drain electrodes 244 and 246 and the data line 240, and the protective layer 250 is formed. The drain process hole 253 exposing the drain electrode 246 is formed by patterning the mask process.

Thereafter, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited on the passivation layer 250 where the drain contact hole 253 is formed and patterned. The pixel electrode 260 in contact with the drain electrode 246 through the drain contact hole 253 can be formed to complete the array substrate 201 for a liquid crystal display device according to the second embodiment of the present invention. have.

In the array substrate for a liquid crystal display according to the present invention, a pure amorphous silicon layer is crystallized into a polysilicon layer through an AMFC process, and a thin film transistor is used as the semiconductor layer to prepare a thin film transistor with a semiconductor layer of a pure amorphous silicon layer. There is an effect of improving the mobility properties of several tens to several hundred times.

In addition, since the source and drain electrodes do not come into contact with the side surfaces of the ohmic contact layer disposed below, there is an effect of preventing the formation of parasitic paths.

Claims (18)

A substrate; A gate electrode and a gate wiring formed on the substrate; A gate insulating film formed over the gate electrode and the gate wiring; The semiconductor layer is sequentially stacked on the gate insulating layer to correspond to the gate electrode, and includes a first silicon layer of polysilicon, a second silicon layer of pure amorphous silicon spaced apart from each other, and an ohmic contact layer of impurity amorphous silicon spaced apart from each other. A layer; Source and drain electrodes spaced apart from the ohmic contact layer; A data line formed over the gate insulating layer and crossing the gate line to define a pixel area; A protective layer formed on a front surface of the source and drain electrodes and the data line and in contact with an end side of each of the source and drain low electrodes and the ohmic contact layer; A pixel electrode formed on the protective layer in contact with the drain electrode in the pixel region Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the second silicon layer is formed to completely cover an end portion and a side surface of the first silicon layer disposed below the second silicon layer. The method of claim 1, And the second silicon layer and the ohmic contact layer are formed so that their ends vertically coincide with each other. The method of claim 1, And the protective layer is formed with a drain contact hole exposing the drain electrode. The method of claim 1, And wherein the portion of the first silicon layer overlapping the source and drain electrodes has a first thickness, and the other regions have a second thickness that is thinner than the first thickness. The method of claim 5, wherein And the first thickness is 1200 kPa to 2000 kPa and the second thickness is 1000 kPa to 1800 kPa. Forming a gate electrode and a gate wiring on the substrate; Forming a gate insulating film over the gate electrode and the gate wiring; Forming a first pure amorphous silicon layer of a first thickness over said gate insulating film; Crystallizing the first pure amorphous silicon layer with a polysilicon layer; Patterning the polysilicon layer to form a first silicon layer; Sequentially forming a second pure amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer over the patterned first silicon layer; Patterning the metal layer, the impurities under it, and the second pure amorphous silicon layer to cross the gate wiring to define a pixel region, and source and drain electrodes spaced apart from each other, and the same shape under the source and drain electrodes. Forming a ohmic contact layer having a second silicon layer spaced apart from each other in a form completely covering an end of the first silicon layer; Forming a protective layer exposing the drain electrode over the data line and the source and drain electrodes; Forming a pixel electrode on the protective layer in contact with the drain electrode in the pixel region Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein Wherein said crystallization is performed by alternating magnetic field crystallization. The method of claim 8, The alternating magnetic field crystallization is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C. A method of manufacturing an array substrate for a liquid crystal display device. The method of claim 8, The alternating magnetic field crystallization may be performed such that an alternating magnetic field generator is linearly reciprocated horizontally and positioned above and below the substrate with respect to the substrate located in the chamber. Method of preparation. The method of claim 8, The alternating magnetic field crystallization is performed for 1 to 60 seconds. The method of claim 8, Source and drain electrodes spaced apart from the data line, an ohmic contact layer having the same shape as the lower portion of the source and drain electrodes, and a second silicon layer spaced apart from each other so as to completely cover the ends of the first silicon layer. The steps are Forming a first photoresist pattern having a second thickness over the metal layer and a second photoresist pattern having a third thickness thinner than the second thickness; A metal layer exposed to the outside of the first and second photoresist patterns, impurities and a second pure amorphous silicon layer under the first and second photoresist patterns may be removed to form a source drain pattern in a connected state with the data line; Sequentially forming an impurity and a pure amorphous silicon pattern having the same shape; Performing ashing to remove the second photoresist pattern of the third thickness; Forming the source and drain electrodes spaced apart from each other by etching a central portion of the source drain pattern exposed by removing the second photoresist pattern; Forming the ohmic contact layers spaced apart from each other by removing the impurity amorphous pattern exposed between the source and drain electrodes; Forming the second silicon layers spaced apart from each other by removing the pure amorphous silicon pattern exposed between the ohmic contact layers. Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 8, And performing dry etching on the first silicon layer region exposed between the second silicon layers spaced apart from each other so as to have a fourth thickness thinner than the first thickness. Method of preparation. The method of claim 13, And the dry etching is performed such that a difference between the first thickness and the fourth thickness is 200 kPa to 400 kPa. The method of claim 14, And performing a hydrogenation process of exposing the plasma to a hydrogen (H ₂ ) atmosphere after performing the dry etching. A gate electrode; A gate insulating film formed over the gate electrode; A semiconductor layer sequentially stacked on the gate insulating layer corresponding to the gate electrode, and including a first silicon layer of polysilicon, a second silicon layer of pure amorphous silicon spaced apart from each other, and an ohmic contact layer of impurity amorphous silicon spaced apart from each other and; Source and drain electrodes spaced apart from the ohmic contact layer; A protective layer formed in contact with an end of the source and drain electrodes and an end of the ohmic contact layer Thin film transistor comprising a. The method of claim 16, The second silicon layer is a thin film transistor, characterized in that formed to completely cover the end and the side of the first silicon layer located below. The method of claim 17, And the second silicon layer and the ohmic contact layer are formed so that their ends vertically coincide with each other.

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