KR20110028146A - Thin film transistor and method of fabricating thereof - Google Patents

Abstract

PURPOSE: A thin film transistor and a manufacturing method thereof are provided to use a hybrid structure that an amorphous silicon channel area and a silicon channel area coexist in an active layer, thereby obtaining high mobility and low off-current properties. CONSTITUTION: Gate electrodes(121a,121b) are arranged in parallel on a substrate(110). A gate insulating film(115a) is formed on a substrate with the gate electrodes. An active layer(124) is formed by amorphous silicon on the substrate. Source/drain electrodes(122,123) are electrically connected to source/drain areas of the active layer on a substrate with the active layer. Laser is irradiated from an offset area to crystallize a fixed area of the active layer.

Description

Thin film transistor and its manufacturing method {THIN FILM TRANSISTOR AND METHOD OF FABRICATING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a hybrid thin film transistor having an amorphous silicon channel region and a polycrystalline silicon channel region together in an active layer, and a method of manufacturing the same.

In today's information society, display is more important as a visual information transmission medium, and in order to gain a major position in the future, it is necessary to satisfy requirements such as low power consumption, thinness, light weight, and high definition. Liquid Crystal Display (LCD), the flagship product of Flat Panel Display (FPD), has not only the ability to satisfy these conditions of the display but also mass production. It has been established as a core component industry that can gradually replace the existing cathode ray tube (CRT).

In general, a liquid crystal display device is a display device in which data signals according to image information are individually supplied to pixels arranged in a matrix form so that a desired image can be displayed by controlling light transmittance of the pixels. .

To this end, the liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate. .

In this case, a thin film transistor (TFT) is generally used as a switching device of the liquid crystal display, and an amorphous silicon thin film or a polycrystalline silicon thin film is used as an active layer of the thin film transistor. use.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of mask processes in terms of productivity is required. It is required.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

FIG. 1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device. As described above, the liquid crystal display device is largely divided into a color filter substrate 5 and an array substrate 10, and the color filter substrate 5 and an array substrate ( It consists of a liquid crystal layer 40 formed between 10).

At this time, the color filter substrate 5 and the color filter (C) divided into a sub-color filter (7) for implementing the colors of Red (R), Green (G), Blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 40, and a transparent common electrode 8 that applies a voltage to the liquid crystal layer 40. )

In the array substrate 10, gate lines 16 and data lines 17 are formed on the substrate 10 to be vertically and horizontally defined to define the pixel region P. In this case, a thin film transistor T, which is a switching element, is formed in an intersection region of the gate line 16 and the data line 17, and a pixel electrode 18 is formed in each pixel region P.

The pixel region P is a sub pixel corresponding to one sub color filter 7 of the color filter substrate 5, and the color image is the three types of sub color filters 7 of red, green, and blue. ) In combination. That is, three subpixels of red, green, and blue are gathered to form one pixel, and the thin film transistor T is connected to the red, green, and blue subpixels, respectively.

Although not shown in detail, the thin film transistor T includes a gate electrode connected to the gate line 16, a source electrode and a drain electrode connected to the data line 17. In addition, the thin film transistor T is an active layer that forms a conductive channel between the source electrode and the drain electrode by an insulating film for insulating the gate electrode and the source / drain electrode and a gate voltage supplied to the gate electrode. Layer.

The active layer is formed of an amorphous silicon thin film or a polycrystalline silicon thin film as described above, and the polycrystalline silicon thin film transistor using the polycrystalline silicon thin film has a structure different from that of the amorphous silicon thin film transistor, so that the polycrystalline silicon thin film transistor and the amorphous silicon thin film Thin film transistors are generally manufactured through different manufacturing processes.

In general, thin film transistors are classified into a staggered structure and a coplanar structure according to the formation positions of the electrodes.

2 is a cross-sectional view illustrating an amorphous silicon thin film transistor having a general staggered structure, and FIG. 3 is a cross-sectional view showing a polycrystalline silicon thin film transistor having a general coplanar structure.

Referring to FIGS. 2 and 3, the staggered structure generally includes source / drain electrodes 22 ′ and 23 ′ and a gate electrode 21 ′ disposed on upper and lower sides of the insulating layer 15a, respectively. The coplanar structure has both the gate electrode 21 "and the source / drain electrodes 22", 23 "disposed above or below the insulating films 15a and 15b. As a structure, it is generally applied to CMOS (Complementary Metal Oxide Semiconductor) and polycrystalline silicon thin film transistor.

For reference, reference numerals 24 'and 24 "are active layers of thin film transistors, respectively, and are made of an amorphous silicon thin film and a polycrystalline silicon thin film, respectively, and reference numerals 10, 15c, 18, and 25n denote an array substrate, a protective film, a pixel electrode, and an ohmic, respectively. An ohmic contact layer is shown.

The polycrystalline silicon thin film transistors configured as described above have excellent mobility characteristics compared to the amorphous silicon thin film transistors, but require an additional crystallization process to form the polycrystalline silicon thin film, and use a manufacturing process different from the amorphous silicon thin film transistor. It is common to make.

That is, the polycrystalline silicon thin film transistor needs to further perform a crystallization process such as heat treatment after depositing an amorphous silicon thin film to obtain a polycrystalline silicon thin film. The crystallization process requires expensive equipment such as laser equipment and a long process time. In the case of forming a coplanar structure, a manufacturing process is complicated, such as requiring 6 to 8 mask processes.

In addition, the polycrystalline silicon thin film transistor has a higher on current characteristic than the amorphous silicon thin film transistor, but is due to a trap site or the like present in the grain together with the grain boundary of the polycrystalline silicon. Off current, that is, leakage current due to band-to-band tunneling, which is determined by the leakage current and the electric field size of the drain region, becomes a problem.

One of the solutions for solving such a problem is an LDD (Lightly Doped Drain) structure, but the problem is that the structure is complicated and the number of masks is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a thin film transistor having high mobility and low off-current characteristics by adopting a hybrid structure in which an amorphous silicon channel region and a polycrystalline silicon channel region are present in an active layer. The purpose is to.

Another object of the present invention is to fabricate the hybrid structure by a simple crystallization method within a range that does not modify the conventional stepped structure of the amorphous silicon thin film transistor manufacturing process, the manufacturing process is simplified and the cost is reduced thin film transistor and its It is to provide a manufacturing method.

Further objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the manufacturing method of the thin film transistor of the present invention comprises the steps of forming at least two gate electrodes configured in parallel to have a predetermined offset region on the substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer of amorphous silicon on the substrate on which the gate insulating film is formed; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer on the substrate on which the active layer is formed; And crystallizing a predetermined region of the active layer by irradiating a laser through the offset region from the rear surface of the substrate.

The thin film transistor of the present invention is formed on a substrate, two or more gate electrodes configured in parallel to have a predetermined offset region; A gate insulating film formed on the substrate on which the gate electrode is formed; An active layer formed on the substrate on which the gate insulating film is formed, the active layer including an amorphous silicon channel region and a polycrystalline silicon channel region; A source / drain electrode formed on the substrate on which the active layer is formed and electrically connected to a source / drain region of the active layer; A passivation layer formed on the substrate on which the source / drain electrode is formed and including a contact hole exposing a part of the drain electrode; And a pixel electrode electrically connected to the drain electrode through the contact hole.

As described above, the thin film transistor and the method of manufacturing the same according to the present invention have a high mobility (about 1 ~ 5cm ² / Vs) characteristics compared to the conventional amorphous silicon thin film transistor, while compared to the conventional polycrystalline silicon thin film transistor It provides the effect of ensuring the low off-current (about 10 ¹¹ ~ 10 ¹² A) characteristics.

In addition, the thin film transistor and its manufacturing method according to the present invention can be manufactured through four to five mask processes within the scope of not modifying the conventional manufacturing process of amorphous silicon thin film transistor of the staggered structure to reduce the manufacturing process and cost It provides an effect.

In addition, the thin film transistor and the method of manufacturing the same according to the present invention uses the back laser irradiation in the crystallization method, thereby providing an excellent productivity effect compared to the general polycrystalline silicon thin film transistor that requires laser crystallization on the entire surface of the substrate.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of a thin film transistor and a method for manufacturing the same according to the present invention.

4 is a cross-sectional view schematically illustrating a thin film transistor according to an exemplary embodiment of the present invention, and illustrates a thin film transistor having a hybrid structure in which an amorphous silicon channel region and a polycrystalline silicon channel region are present in an active layer.

As shown in the figure, the thin film transistor according to the embodiment of the present invention is largely the gate electrode 121a, 121b formed on the substrate 110, the gate insulating film 115a formed on the gate electrode 121a, 121b, the gate The active layer 124 formed on the insulating film 115a and the source / drain electrodes 122 and 123 electrically connected to the source / drain regions 124a and 124b of the active layer 124.

The thin film transistor according to the embodiment of the present invention may be formed through a protective layer 115b formed on the substrate 110 on which the source / drain electrodes 122 and 123 are formed and a contact hole formed in the protective layer 115b. And a pixel electrode 118 electrically connected to the drain electrode 123.

In this case, the source / drain electrodes 122 and 123 may be a source / drain region of the active layer 124 made of an amorphous silicon thin film through an ohmic contact layer 125n formed of an n + amorphous silicon thin film. 124a and 124b) to form an ohmic contact.

The thin film transistor according to the embodiment of the present invention forms two or more gate electrodes 121a and 121b in parallel to form a gate offset structure, while the channel region of the active layer 124 is formed in the gate region. And a polysilicon channel region 124c formed in the offset region and an amorphous silicon channel region 124c 'formed between the polycrystalline silicon channel region 124c and the source / drain regions 124a and 124b.

As described above, the thin film transistor according to the exemplary embodiment of the present invention adopts a hybrid structure of an amorphous silicon channel region composed of an amorphous silicon thin film and a polycrystalline silicon channel region composed of a polycrystalline silicon thin film as a channel region of an active layer, wherein the conventional staggered The hybrid structure can be fabricated by crystallizing a part of the active layer through back laser irradiation within the range of not deforming the fabrication process of the amorphous silicon thin film transistor of the structure, which will be described in detail by the following method of manufacturing the thin film transistor. .

5A through 5E are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor illustrated in FIG. 4.

As shown in FIG. 5A, predetermined gate electrodes 121a and 121b are formed on a substrate 110 made of a transparent insulating material such as glass.

The gate electrodes 121a and 121b are formed by depositing a first conductive layer on the entire surface of the substrate 110 and then selectively patterning the same through a photolithography process (first mask process). 121b) forms a gate offset structure by configuring two or more in parallel.

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), Low resistance opaque conductive materials such as molybdenum (Mo), titanium (Ti), platinum (platinum; Pt), tantalum (Ta), and the like can be used, and a multilayer structure in which two or more conductive materials are laminated It can also be formed.

Subsequently, as shown in FIG. 5B, a gate insulating film 115a, an amorphous silicon thin film, an n + amorphous silicon thin film, and a second conductive film are formed on the entire surface of the substrate 110 on which the gate electrodes 121a and 121b are formed. By selectively removing through a lithography process (second mask process), an active pattern 124 made of the amorphous silicon thin film is formed on the gate electrodes 121a and 121b of the substrate 110, while the second conductive film is formed. And the source / drain electrodes 122 and 123 electrically connected to the source / drain regions of the active pattern 124 through the ohmic contact layer 125n.

Here, the active pattern 124 and the source / drain electrodes 122 and 123 according to the embodiment of the present invention include a diffraction mask or a half-tone mask (hereinafter, referred to as a diffraction mask) including a half-tone mask. It will be formed at the same time in one mask process (second mask process), the second mask process will be described in detail below with reference to the drawings.

6A through 6F are cross-sectional views illustrating a second mask process in the thin film transistor illustrated in FIG. 5B.

As shown in FIG. 6A, the gate insulating layer 115a, the amorphous silicon thin film 120, the n + amorphous silicon thin film 125, and the second conductive layer may be formed on the entire surface of the substrate 110 on which the gate electrodes 121a and 121b are formed. 130).

In this case, the gate insulating layer 115a serves as a buffer layer for a crystallization process to be described later, and the second conductive layer 130 may be formed of aluminum, aluminum alloy, and tungsten to form a source electrode and a drain electrode. And low resistance opaque conductive materials such as copper, chromium, molybdenum and molybdenum alloys.

In this case, when the amorphous silicon thin film 120 is deposited, the dehydrogenated amorphous silicon thin film 120 may be deposited, and after the deposition of the amorphous silicon thin film 120, the dehydrogenation process may be performed.

And, as shown in Figure 6b, after forming a photosensitive film 170 made of a photosensitive material such as photoresist on the entire surface of the substrate 110, the photosensitive film through a diffraction mask 180 according to an embodiment of the present invention Light is selectively irradiated to 170.

In this case, the diffraction mask 180 is applied to the first transmission region (I) and the slit pattern that transmits all the irradiated light is applied to the second transmission region (II) and all the irradiated light to transmit only a part of the light and block some. The blocking region III is provided to block the light, and only the light passing through the diffraction mask 180 is irradiated onto the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 180 is developed, all light is blocked through the blocking region III and the second transmission region II, as shown in FIG. 6C. The first photoresist pattern 170a to the third photoresist pattern 170c having a predetermined thickness remain in a region where only a portion thereof is blocked or partially blocked, and the photoresist is completely removed in the first transmission region I through which all light is transmitted. The surface of the second conductive film 130 is exposed.

In this case, the first photoresist pattern 170a and the second photoresist pattern 170b formed in the blocking region III are formed thicker than the third photoresist pattern 170c formed through the second transmission region II. In addition, the photosensitive film is completely removed in a region where all the light is transmitted through the first transmission region I. This is because the photoresist of the positive type is used, and the present invention is not limited thereto. May be used.

Next, as shown in FIG. 6D, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second formed on the lower portion of the first photosensitive film pattern 170a to the third photosensitive film pattern 170c formed as described above are used as a mask. When the conductive layer is selectively removed, the active pattern 124 made of the amorphous silicon thin film is formed on the gate electrodes 121a and 121b of the substrate 110.

In this case, the n + amorphous silicon thin film pattern 125 ′ and the second conductive film formed of the n + amorphous silicon thin film and the second conductive film and patterned in the same shape as the active pattern 124, respectively, on the active pattern 124. The pattern 130 'is formed.

Subsequently, when an ashing process of removing a portion of the first photoresist pattern 170a to the third photoresist pattern 170c is performed, as illustrated in FIG. 6E, the second transmission region II is formed. The third photosensitive film pattern of is completely removed.

In this case, the first photoresist pattern and the second photoresist pattern correspond to the blocking region III by the fourth photoresist pattern 170a 'and the fifth photoresist pattern 170b' that have been removed by the thickness of the third photoresist pattern. Only the source electrode region and the drain electrode region remain.

6F, a portion of the n + amorphous silicon thin film pattern and the second conductive film pattern are removed using the remaining fourth photoresist pattern 170a ′ and the fifth photoresist pattern 170b ′ as masks. As a result, the source electrode 122 and the drain electrode 123 formed of the second conductive layer are formed on the substrate 110.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active pattern 124 and ohmic-contacting between the source / drain region of the active pattern 124 and the source / drain electrodes 122 and 123. 125n is formed.

As described above, in the exemplary embodiment of the present invention, the active pattern 124 and the source / drain electrodes 122 and 123 may be formed through one mask process by using a diffraction mask.

However, the present invention is not limited thereto, and the active pattern 124 and the source / drain electrodes 122 and 123 may be formed through two mask processes, respectively.

Next, as shown in FIG. 5C, a predetermined passivation layer 115b is formed on the entire surface of the substrate 110 on which the active pattern 124 and the source / drain electrodes 122 and 123 are formed, and then a photolithography process ( By selectively patterning using a third mask process), a contact hole 140 exposing a part of the drain electrode 123 is formed.

As shown in FIG. 5D, after forming the third conductive film on the entire surface of the substrate 110 on which the protective film 115b is formed, the third conductive film is selectively patterned using a photolithography process (fourth mask process). The pixel electrode 118 is formed of a conductive film and electrically connected to the drain electrode 123 through the contact hole 140.

In this case, the third conductive layer may be formed of a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrode 118. It is available.

Next, as shown in FIG. 5E, the thin film transistor having the pixel electrode 118 formed a predetermined region of the active layer 124 that is not covered by the gate electrodes 121a and 121b due to a gate offset. The laser is irradiated from the back of the transistor to proceed with crystallization. Thereafter, a predetermined annealing process may be performed.

In this case, the completed thin film transistor is a polysilicon channel region 124c crystallized by the laser irradiation to the active layer 124 and the amorphous silicon channel region 124c 'shielded by a laser by the gate electrodes 121a and 121b. As a result, the on-current and mobility (about 1 to 5 cm ² / Vs) are higher than that of the conventional amorphous silicon thin film transistor, and the off current (about 10 ¹¹ is higher than that of the conventional general polycrystalline silicon thin film transistor). -10 ¹² A) will be lowered.

In this case, although not shown in the drawing, a part of the active layer 124 shielded by the gate electrodes 121a and 121b and not crystallized is partially transferred by heat transfer from the crystallized polycrystalline silicon channel region 124c. Crystallization may occur.

7A to 7C are cross-sectional views sequentially illustrating a crystallization process of an active layer according to back laser irradiation, and FIG. 8 is a scanning electron microscope showing a part of the active layer crystallized by the crystallization process illustrated in FIGS. 7A to 7C. (Scanning Electron Microscope; SEM).

In this case, the width of the gate offset and other laser processing conditions will vary, but the active layer 124 irradiated with the laser from the back surface of the thin film transistor has a predetermined region melted by the laser irradiation, as shown in FIG. 7A. will be melted.

For reference, FIG. 7A illustrates, for example, a state in which amorphous silicon of the active layer 124 is melted by a width of Rm, and Ps represents an amorphous silicon region that remains in a solid state without being irradiated with a laser.

At this time, as shown in FIG. 7B, crystals grow from the lateral boundary of the amorphous silicon region Ps toward the center of the active layer 124 to form grains G having a relatively large size.

Thereafter, as shown in FIG. 7C, when the width Rm of the molten active layer 124 is larger than the size of the grain G grown in the center direction of the active layer 124, that is, twice the width. Fine grains Gn are formed at the center of the active layer 124 (see FIG. 8).

As described above, the thin film transistor according to the embodiment of the present invention can be manufactured through four to five mask processes within the scope of not modifying the conventional manufacturing process of the amorphous silicon thin film transistor of the staggered structure, thereby improving the manufacturing process and cost. Provides savings.

In addition, the thin film transistor according to the embodiment of the present invention uses the back laser irradiation in the crystallization method, thereby providing an effect of higher productivity than a general polycrystalline silicon thin film transistor that requires laser crystallization on the entire surface of the substrate.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

1 is an exploded perspective view schematically illustrating a structure of a general liquid crystal display device.

2 is a cross-sectional view showing an amorphous silicon thin film transistor having a general staggered structure.

3 is a cross-sectional view showing a polycrystalline silicon thin film transistor having a general coplanar structure.

4 is a schematic cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

5A through 5E are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor illustrated in FIG. 4.

6A to 6F are cross-sectional views illustrating a second mask process in the thin film transistor illustrated in FIG. 5B.

7A to 7C are cross-sectional views sequentially illustrating a crystallization process of an active layer according to back laser irradiation.

FIG. 8 is a scanning electron microscope (SEM) photograph showing a part of the active layer crystallized by the crystallization process shown in FIGS. 7A to 7C.

DESCRIPTION OF REFERENCE NUMERALS

118: pixel electrode 121a, 121b: gate electrode

122 source electrode 123 drain electrode

124: active layer 124c: polycrystalline silicon channel region

124c ': amorphous silicon channel region

Claims (10)

Forming at least two gate electrodes configured in parallel to have a predetermined offset region on the substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming an active layer of amorphous silicon on the substrate on which the gate insulating film is formed; Forming a source / drain electrode electrically connected to the source / drain regions of the active layer on the substrate on which the active layer is formed; And Irradiating a laser from the rear surface of the substrate through the offset region to crystallize a predetermined region of the active layer. The method of claim 1, Forming a protective film on an entire surface of the substrate on which the source / drain electrodes are formed; Removing a portion of the passivation layer to form a contact hole exposing a portion of the drain electrode; And And forming a pixel electrode electrically connected to the drain electrode through the contact hole. The method of claim 1, further comprising forming an ohmic contact layer formed of an n + amorphous silicon thin film on the substrate on which the active layer is formed, and ohmic-contacting a source / drain region of the active layer and the source / drain electrode. Method of manufacturing a thin film transistor, characterized in that it further comprises. The method of claim 1, wherein the active layer and the source / drain electrodes are formed through the same mask process. The method of claim 1, wherein the active layer includes a polycrystalline silicon channel region crystallized by the laser irradiation and an amorphous silicon channel region shielded by the gate electrode. 6. The method of claim 5, wherein a part of the active layer shielded by the gate electrode and not crystallized is partially crystallized by heat transfer from the crystallized polycrystalline silicon channel region. Two or more gate electrodes formed on the substrate and configured in parallel to have a predetermined offset region; A gate insulating film formed on the substrate on which the gate electrode is formed; An active layer formed on the substrate on which the gate insulating film is formed, the active layer including an amorphous silicon channel region and a polycrystalline silicon channel region; A source / drain electrode formed on the substrate on which the active layer is formed and electrically connected to a source / drain region of the active layer; A passivation layer formed on the substrate on which the source / drain electrode is formed and including a contact hole exposing a part of the drain electrode; And And a pixel electrode electrically connected to the drain electrode through the contact hole. 8. The semiconductor device of claim 7, further comprising an ohmic contact layer formed of an n + amorphous silicon thin film on the substrate on which the active layer is formed, and ohmic contact between a source / drain region of the active layer and the source / drain electrode. A thin film transistor, characterized in that. 8. The thin film transistor of claim 7, wherein the active layer includes a polycrystalline silicon channel region crystallized by back laser irradiation to the offset region and an amorphous silicon channel region shielded by the gate electrode. . 10. The thin film transistor of claim 9, wherein a part of the active layer shielded by the gate electrode and not crystallized is partially crystallized by heat transfer from the crystallized polycrystalline silicon channel region.

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