KR20080053698A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

An array substrate in an LCD(Liquid Crystal Display) and a method for manufacturing the same are provided to remarkably improve a mobility characteristic by performing AMFC(Alternating Magnetic Field Crystallization) for a pure amorphous silicon layer. An array substrate in an LCD comprises a substrate(201), a gate electrode(205), a gate insulating layer(208), a semiconductor layer(232), a source electrode, and a drain electrode. The gate electrode is formed on the substrate. The gate insulating layer is formed on the gate electrode. The semiconductor layer, laid on the gate insulating layer, consists of the first polysilicon layer(214) and an impure polysilicon layer(226). The first polysilicon layer comprises the first area(214a) having the first thickness and the second area(214b) having the second thickness. The impure polysilicon layer, laid on the first polysilicon layer, is composed of two areas isolated from each other. Also the array substrate comprises the second polysilicon layer(230). The second polysilicon layer, an ohmic contact layer, is laid on the impure polysilicon layer, and consists of two areas isolated from each other. The source electrode and the drain electrode are formed on the second polysilicon layer. The first polysilicon layer and the impure polysilicon layer are crystallized through AMFC.

Description

Array substrate for liquid crystal display device and method of fabricating the same

1 is an exploded perspective view of a general liquid crystal display device.

2 is a cross-sectional view of a portion including a thin film transistor in one pixel area of an array substrate of a conventional liquid crystal display device.

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention.

4A to 4G are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display device according to a first exemplary embodiment of the present invention.

5 is a photograph of a surface component of the array substrate for a liquid crystal display device according to the first embodiment.

6 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

7A to 7I are cross-sectional views illustrating manufacturing steps of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

201: substrate 205: gate electrode

208: gate insulating film 214: first polysilicon pattern

214a, 214b: first and second regions of the first polysilicon pattern

219: second silicon layer (of pure amorphous silicon)

226 impurity polysilicon pattern 230 second polysilicon pattern

232 semiconductor layer 293 self crystallization process chamber

295: alternating magnetic field generating device t1: first thickness (thickness of first region)

t2: thickness removed by primary dry etching

t4: fourth thickness (thickness of second region)

The present invention relates to a liquid crystal display device, and more particularly, to a structure of a thin film transistor formed in each pixel region of an array substrate for a liquid crystal display device and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, high technology value, and high added value.

Among the liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element that can control voltage on and off for each pixel, has the best resolution and video performance. It is attracting attention.

Referring to FIG. 1, which is an exploded perspective view of a general liquid crystal display device, a structure of a liquid crystal display device will be described. As illustrated, the array substrate 10 and the color filter substrate 20 are disposed with the liquid crystal layer 30 therebetween. In this case, the bottom substrate array substrate 10 is vertically intersected with the upper surface of the transparent substrate 12 to define a plurality of pixel regions P and a plurality of gate wirings 14 and data wirings 16. A thin film transistor T is provided at an intersection point of the two wires 14 and 16 and is connected one-to-one with the pixel electrode 18 provided in each pixel region P.

In addition, the upper color filter substrate 20 facing the array substrate may cover a non-display area such as the gate line 14, the data line 16, and the thin film transistor T on the rear surface of the transparent substrate 22. Grid-like black matrix 25 is formed so as to border each pixel region P, and the red, green, and blue color filter layers 26 are sequentially arranged to correspond to each pixel region P in the grid. ) Is formed, and a transparent common electrode 28 is provided over the entirety of the black matrix 25 and the red, green, and blue color filter layers 26.

Although not shown in the drawings, these two substrates 10 and 20 are sealed with a sealant or the like along the edges to prevent leakage of the liquid crystal layer 30 interposed therebetween. In the boundary portion of each substrate (10, 20) and the liquid crystal layer 30 is interposed upper and lower alignment layer that provides reliability in the molecular alignment direction of the liquid crystal, and at least one outer surface of each substrate (10, 20) A polarizing plate is provided.

In addition, a back-light is provided on the outer surface of the array substrate to supply light. The on / off signals of the thin film transistor T are sequentially scanned by the gate wiring 14. When the image signal of the data wiring 16 is transmitted to the pixel electrode 18 of the pixel region P applied and selected, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the light transmittance is changed. Branch images can be displayed.

In the liquid crystal display having the above structure, the most important component is a thin film transistor which is formed for each pixel region and is connected to the gate and data lines and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode. Can be.

The cross-sectional structure of the thin film transistor, which serves as such a switching element, will be described with reference to FIG.

2 is a cross-sectional view of a portion in which a thin film transistor is formed in an array substrate of a conventional liquid crystal display.

The gate electrode 60 is formed on the transparent insulating substrate 59, and the gate insulating layer 68 is formed on the entire surface of the gate electrode 60. The semiconductor layer 70 includes an active layer 70a made of pure amorphous silicon on the gate insulating layer, and an ohmic contact layer 70b made of amorphous silicon containing impurities in a form spaced apart from each other. ) Is formed.

In addition, the ohmic contact layer 70b formed to expose the active layer 70a below and spaced apart from each other is in contact with the ohmic contact layer 70b and is spaced apart from each other to correspond to the gate electrode 60. The source electrode 76 and the drain electrode 78 are formed while exposing the layer 70a.

The thin film transistor Tr includes the gate electrode 60, the gate insulating film 68, and the source and drain electrodes 76 and 78 spaced apart from each other, and are sequentially stacked on the substrate 59. To achieve.

A passivation layer 86 having a drain contact hole 80 exposing a part of the drain electrode 78 is formed on the front surface of the thin film transistor Tr having such a structure, and each passivation layer 86 is formed on the passivation layer 86. A pixel electrode 88 is formed in each pixel region P to contact the drain electrode 78 through the drain contact hole 80, and the gate electrode 60 is formed on the same layer on which the gate electrode 60 is formed. ) And a data line (not shown) connected to the source electrode 76 is further formed on the same layer on which the source and drain electrodes 76 and 78 are formed. )

However, in the case of a thin film transistor which is generally configured in a conventional array substrate for a liquid crystal display device, it can be seen that the semiconductor layer uses amorphous silicon. When the semiconductor layer is formed using the amorphous silicon, the amorphous silicon ( a-Si: H) has a weak Si-Si bond and dangling bond because of its disordered atomic arrangement, which is converted into a quasi-stable state when irradiating light or applying an electric field to be used as a thin film transistor device. Stability is a problem, and the electric field effect mobility is low as 0.1 ~ 1.0 cm 2 / V · s, so that the electrical characteristics are not good, it is also a problem to use as a drive circuit.

In order to solve the above problems, an object of the present invention is to provide an array substrate for a liquid crystal display device having a thin film transistor having excellent device performance and reliability by crystallizing amorphous silicon by a simple process and a method of manufacturing the same.

Furthermore, by significantly improving the mobility characteristics, it can be used as a driving circuit and can be driven without the attachment of an external driving circuit board, thereby reducing costs and increasing the integration of the driving device. Another aim is to make it compact.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object is a substrate; A gate electrode formed on the substrate; A gate insulating film formed over the gate electrode; A semiconductor layer comprising a first polysilicon layer having a first region having a first thickness sequentially stacked over the gate insulating film, a second region having a second thickness smaller than the first thickness, and an impurity polysilicon layer spaced apart from each other. and; The semiconductor layer may include a source and a drain electrode formed on and in contact with the ohmic contact layer, respectively.

In this case, the first polysilicon layer and the impurity polysilicon layer are crystallized by an alternating magnetic field crystallization method, further comprising a second polysilicon layer spaced apart from each other on the impurity polysilicon layer. Include.

The first region may overlap the gate electrode, wherein the protective layer is formed by exposing the drain electrode over the source and drain electrodes; A gate electrode formed on the protective layer and in contact with the exposed drain electrode, the gate wire being connected to the gate electrode; And a data line connected to the source electrode and crossing the gate line.

In addition, the first thickness is characterized in that 1200 ~ 2000Å, wherein the difference between the first thickness and the second thickness is characterized in that 200 ~ 400Å.

A method of manufacturing an array substrate for a liquid crystal display device according to a first aspect of the present invention includes forming a gate electrode on the substrate; Sequentially forming a gate insulating film, a first pure amorphous silicon pattern having a first thickness, an impurity amorphous silicon pattern spaced apart from each other, and a second pure amorphous silicon pattern spaced apart from each other over the gate electrode; By performing alternating magnetic field crystallization, the first pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the second pure amorphous silicon pattern are respectively converted into the first polysilicon pattern, the impurity polysilicon pattern, and the second polysilicon pattern. Crystallization; Forming source and drain electrodes that are in contact with the second polysilicon pattern and spaced apart from each other to expose the first polysilicon pattern; Forming a protective layer over the source and drain electrodes; Patterning the passivation layer to form a drain contact hole exposing the gate electrode; Forming a pixel electrode in contact with the drain electrode through the drain contact hole.

In this case, the method further includes etching and removing the first polysilicon pattern exposed to the outside of the source and drain electrodes by a second thickness, wherein the second thickness is 200 kPa to 400 kPa.

The forming of the first pure amorphous silicon pattern, the impurity amorphous silicon pattern spaced apart from each other, and the second pure amorphous silicon pattern spaced apart from each other may include forming a vacuum in a vacuum chamber of the chemical vapor deposition apparatus over the gate insulating film. Forming a first pure amorphous silicon layer, an impurity amorphous silicon layer, and a second pure amorphous silicon layer sequentially and sequentially without breakage; Forming a first photoresist pattern on the second pure amorphous silicon layer and a second photoresist pattern thinner than the first photoresist pattern; By removing the second pure amorphous silicon layer, the impurity amorphous silicon layer and the first pure amorphous silicon layer exposed to the outside of the first and second photoresist patterns, the first pure amorphous silicon pattern, the impurity amorphous silicon pattern and the second Forming a pure amorphous silicon pattern; Removing the second photoresist pattern to expose the second pure amorphous silicon pattern; The method may further include removing the second pure amorphous silicon pattern exposed to the outside of the first photoresist pattern and the impurity amorphous silicon pattern thereunder, wherein the impurity amorphous silicon pattern spaced apart from each other, The forming of the pure amorphous silicon pattern may further include etching the first pure amorphous silicon pattern exposed to the outside of the spaced apart impurity amorphous silicon pattern to have a third thickness thinner than the first thickness, At this time, the first thickness and the third thickness is characterized in that the difference between 100Å.

A method of manufacturing an array substrate for a liquid crystal display device according to a second aspect of the present invention includes forming a gate electrode on the substrate; Sequentially forming a gate insulating film and a first pure amorphous silicon pattern having a first thickness and an impurity amorphous silicon pattern spaced apart from each other on the gate electrode; Crystallizing the first pure amorphous silicon pattern and the impurity amorphous silicon pattern into a first polysilicon pattern and an impurity polysilicon pattern by performing alternating magnetic field crystallization; Forming source and drain electrodes contacting the impurity polysilicon pattern upwardly and spaced apart from each other to expose the first polysilicon pattern; Forming a protective layer over the source and drain electrodes; Patterning the protective layer to form a drain contact hole exposing the drain electrode; Forming a pixel electrode in contact with the drain electrode through the drain contact hole.

In this case, the method further includes etching and removing the first polysilicon pattern exposed to the outside of the source and drain electrodes by a second thickness, wherein the second thickness is 200 kPa to 400 kPa.

The forming of the impurity amorphous silicon pattern spaced apart from the first pure amorphous silicon pattern may be thinner than the first thickness by etching the first pure amorphous silicon pattern exposed to the outside of the spaced apart impurity amorphous silicon pattern. It further comprises the step of having a third thickness, wherein the first thickness and the third thickness is characterized in that the difference between 100Å.

In the manufacturing method according to the first and second aspects, the alternating magnetic field crystallization is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C., wherein the alternating magnetic field crystallization is performed. The AC magnetic field generating device is positioned above and below the substrate and linearly reciprocates with respect to the substrate located in the chamber.

In the manufacturing method according to the first and second aspects, the method may further include thermal annealing the substrate on which the protective layer is formed so that the second polysilicon pattern and the source and drain electrodes form ohmic contacts. In this case, the thermal annealing (thermal annealing) is characterized in that proceeds for 1 hour to 3 hours in 280 ℃ to 420 ℃ atmosphere.

In addition, in the manufacturing method according to the first and second aspects, after the step of etching and removing the first polysilicon pattern exposed to the outside of the source and drain electrodes by a second thickness, a hydrogenation process of exposing to a hydrogen plasma is performed. It further comprises a step, wherein the hydrogenation is characterized in that it proceeds from 300 seconds to 600 seconds.

In addition, in the manufacturing method according to the first and second features, before the gate electrode is formed, further comprising the step of heat-treating the substrate for 30 to 60 minutes in an atmosphere of 700 ℃ to 750 ℃, forming the gate electrode The method may further include forming a gate wiring connected to the gate electrode, and the forming of the source and drain electrodes may further include forming a data wiring connected to the source electrode and intersecting the gate wiring.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

3 is a cross-sectional view illustrating a pixel area including a thin film transistor of an array substrate for a liquid crystal display according to a first embodiment of the present invention. In this case, the driving thin film transistors constituting the driving circuit other than the pixel region are also the same as the structure of the thin film transistor (except the pixel electrode) formed in the pixel region, and thus the description thereof is omitted.

As shown, in the case of the array substrate 101 for a liquid crystal display device according to the present invention, a gate electrode 105 and a gate wiring connected thereto are formed on the transparent insulating substrate 101. A gate insulating layer 108 is formed on the gate line and the gate electrode 105.

In addition, the first silicon layer 114 and the second silicon layer 119 of pure amorphous silicon and the upper spaced apart from each other, characterized in that the pure amorphous silicon crystallized by an alternating magnetic field over the gate insulating film 108. The semiconductor layer 130 having a triple layer structure formed of an ohmic contact layer 125 of impurity amorphous silicon is formed.

In addition, source and drain electrodes 141 and 146 are spaced apart from each other on the ohmic contact layer 125 of the semiconductor layer 130 having the above structure, and the source electrode formed on the semiconductor layer 130 And a data line (not shown) formed over the gate insulating layer 108 to define a pixel area crossing the gate line (not shown). In this case, the gate electrode 105, the gate insulating layer 108, the first and second silicon layers 114 and 119, the ohmic contact layer 125, and the source and drain electrodes 141 and 146 may be thin film transistors Tr. To achieve.

In addition, a passivation layer 150 having a drain contact hole 153 exposing a part of the drain electrode 146 over the source and drain electrodes 141 and 146 and a data line (not shown) is formed. A pixel electrode 160 is formed on the layer 150 to contact the drain electrode 146 through the drain contact hole 153.

In the array substrate 101 for a liquid crystal display device having such a structure, in particular, the thin film transistor Tr having the first and second silicon layers 114 and 119 and the ohmic contact layer 125 is the first silicon layer 114. The pure amorphous silicon is crystallized into polysilicon through an alternating current self crystallization process in which a) is exposed to an alternating magnetic field in a vacuum chamber having a specific temperature, and the mobility characteristics are significantly improved.

In this case, the second silicon layer 119 of pure amorphous silicon formed on the crystallized first silicon layer 114 has a much higher mobility due to the polysilicon characteristic to further increase the off current I _off . This is caused by an increase in leakage current at the boundary between the ohmic contact layer 125 containing impurities and the crystallized first silicon layer 114. Therefore, in order to reduce the increase in leakage current, the second silicon layer 119 of pure amorphous silicon is formed.

A method of manufacturing an array substrate for a liquid crystal display device according to a first embodiment of the present invention having such a structure will be described.

4A through 4G are cross-sectional views illustrating manufacturing processes of one pixel area of an array substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

First, as shown in FIG. 4A, a metal material such as chromium (Cr) or molybdenum (Mo) is deposited on the transparent insulating substrate 101 by using a sputtering device, and then patterned, thereby forming the gate electrode 105 and the gate electrode 105. In connection with this, a gate wiring (not shown) extending in one direction is formed.

Subsequently, the substrate 101 on which the gate wiring (not shown) and the gate electrode 105 are formed is moved to the chamber 190 of a chemical vapor deposition (CVD) apparatus, and then, depending on the material to be deposited. In order to form a gas atmosphere of a kind and form a silicon nitride (SiNx) layer, for example, a mixed gas atmosphere of SiH ₄ / N ₂ or a SiH ₄ / NH ₃ mixed gas is formed, and a silicon oxide (SiO ₂ ) layer is formed. In the case of forming a SiH ₄ / N ₂ O mixed gas atmosphere, a plasma is formed in the chamber 190 to form silicon nitride (SiNx) or oxide on the substrate 101 on which the gate electrode 105 is formed. A gate insulating film 105 of silicon (SiO ₂ ) is formed over the entire surface.

Next, as shown in FIG. 4B, after the gate insulating film 108 is formed, a mixed gas of SiH ₄ / H ₂ in a mixed gas atmosphere for forming the aforementioned gate insulating film 108 in the same chamber 190. After changing to the atmosphere, a plasma is formed in the chamber 190 to form a first pure amorphous silicon layer 112 having a first thickness t1 of about 1200 to 2000 mW over the gate insulating film 108.

Next, as shown in FIG. 4C, the substrate 101 on which the first pure amorphous silicon layer (112 in FIG. 4C) of the first thickness t1 is formed is placed in the chamber of the chemical vapor deposition apparatus (190 in FIG. 4B). In the self-crystallization process chamber 193.

The self-crystallization process chamber 193 may form a high temperature atmosphere of about 500 ° C. to 1000 ° C., and more specifically, centers a stage (not shown) in which the substrate 101 is raised in the chamber 193. It is a feature that an alternating magnetic field can be formed above and below it.

After placing the substrate 101 on which the first pure amorphous silicon layer (112 of FIG. 4C) is formed on a stage (not shown) in the self-crystallization process chamber 193 having this characteristic, the atmosphere in the chamber 193 is Is heated to 700 ° C to 750 ° C and a magnetic field (AMF) perpendicular to the substrate 101 is applied for 1 to 60 seconds in this heated atmosphere.

In this case, it is preferable to expose the surface of the substrate 101 to the magnetic field AMF in such a manner that the AC magnetic field generating device 195 positioned above and below the substrate 101 performs a linear reciprocating motion. In other words, the first pure amorphous silicon layer 112 (in FIG. 4C) is exposed to an alternating magnetic field in a scan form. When the process proceeds, the first pure amorphous silicon layer 112 (in FIG. 4C) is crystallized to be changed to the polysilicon layer 113.

When explaining the principle of alternating current self-crystallization, the main energy source of the crystallization is heat, the alternating magnetic field plays an auxiliary role. At this time, a current is induced inside the pure amorphous silicon layer by the alternating magnetic field, and the joule heat is generated by the induced internal current to accelerate the crystallization, and by applying the force to move the atoms by the alternating magnetic field It will promote crystallization.

The polysilicon layer 113 formed by the self-crystallization process has a mobility of 20 cm 2 / V · s to 30 cm 2 / V · s, which is about 0.1 cm 2 / V · s to 1 cm 2 / V · s of movement. It can be seen that it is several tens to several hundred times as compared to the pure amorphous silicon layer (112 of FIG. 4C) having a degree.

The process of crystallizing by exposing to an alternating magnetic field (AMF) in such a high temperature atmosphere is called an alternating magnetic field crystallization (AMFC) process.

Since the substrate 101 is exposed to a high temperature of about 700 ° C. to 750 ° C. during the AMFC process, the substrate 101 may be deformed more precisely, so that shrinkage may occur. For example, the substrate 101 may have a temperature of 700 ° C. to 750 ° C. before the gate electrode 105 and the gate wiring (not shown) forming step shown in FIG. 4A. It is preferable to proceed with the AMFC process after further proceeding the heat treatment while varying the temperature for 30 to 60 minutes in a high temperature atmosphere.

Next, as shown in FIG. 4D, the substrate 101 having undergone the AMFC process is moved back into the chamber 190 of the chemical vapor deposition apparatus in the self-crystallization process chamber (193 of FIG. 4C), and then the chemical vapor phase The second pure amorphous silicon layer 118 is formed on the polysilicon layer 113 by forming a plasma after forming an atmosphere in the chamber 190 of the deposition apparatus in a mixed gas atmosphere of SiH ₄ / H ₂ .

Subsequently, after changing the atmosphere in the chamber 190 to the mixed gas atmosphere of SiH ₄ / PH ₃ / H ₂ , the plasma is formed to impurity amorphous silicon layer 123 over the second pure silicon layer 118. Form.

Next, as shown in FIG. 4E, a mask process is performed on the substrate 101 on which the impurity amorphous silicon layer 123 is formed, thereby forming the impurity amorphous silicon layer (123 of FIG. 4D) and the second pure amorphous material thereunder. The silicon layer 118 of FIG. 4D and the polysilicon layer 123 of FIG. 4D are simultaneously patterned to form the first silicon layer 114 of polysilicon, the second silicon layer 119 of pure amorphous silicon, and the second silicon. An ohmic contact layer 124 in a connected state of impurity amorphous silicon is formed over the layer.

Next, as shown in FIG. 4F, a source spaced apart from each other on the ohmic contact layer (124 of FIG. 4E) by depositing and patterning a second metal material over the ohmic contact layer (124 of FIG. 4E) in the connected state. Drain electrodes 141 and 146 and a data line (not shown) are formed on the gate insulating layer 108 to be connected to the source electrode 141 and cross the gate line (not shown).

Then, the ohmic contact layer exposed between the source and drain electrodes 141 and 146 by dry etching using the source and drain electrodes 141 and 146 spaced apart from each other as a mask (124 in FIG. 4E). By removing the N-type contact ohmic contact layer 125 is formed below the source and drain electrodes 141 and 146, respectively.

As shown in FIG. 4G, an inorganic insulating material such as silicon nitride (SiNx) or the like may be formed on the substrate 101 on which the ohmic contact layer 125 is spaced apart from the source and drain electrodes 141 and 146. By depositing and patterning silicon oxide (SiO ₂ ), a protective layer 150 having a drain contact hole 153 exposing a portion of the drain electrode 146 is formed.

The drain contact hole is then deposited by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the passivation layer 150 having the drain contact hole 153. By forming the pixel electrode 160 in contact with the drain electrode 146 through 153, the array substrate 101 for liquid crystal display device having excellent mobility characteristics according to the first embodiment of the present invention can be completed. .

However, in the case of the array substrate for a liquid crystal display device manufactured by the manufacturing method of the first embodiment described above, the first silicon layer of polysilicon and the second silicon layer of pure amorphous silicon are deposited discontinuously, that is, the chemical vapor deposition equipment After forming the first pure amorphous silicon layer in the chamber of the crystallization process, the crystallization of the pure amorphous silicon layer to a polysilicon layer by moving to a self-crystallization process chamber and AMFC to crystallize it, and then again chemical vapor deposition equipment The second pure amorphous silicon layer and the impurity amorphous silicon layer are successively formed by moving to the chamber of. Therefore, due to the discontinuous deposition, at the interface between the polysilicon layer and the second pure amorphous silicon layer, a natural oxide film is formed by contact with air during movement, and the natural oxide film contains contaminants in the air. Particularly, stress between these two layers is increased by the manufacturing process temperature difference, and the bonding force is rapidly lowered, so that excitation occurs. When the annealing process is performed to improve the interfacial properties, hydrogen penetrates into the space where the excitation occurs. As a result, as shown in FIG. 5, the surface of the protective layer is swollen.

Therefore, in the second embodiment of the present invention, a structure capable of preventing the deterioration of the interface characteristics and the surface part phenomenon caused by the method of manufacturing the array substrate for a liquid crystal display device including the polysilicon layer described in the first embodiment described above. And a preparation method.

Second Embodiment

6 is a cross-sectional view of one pixel area including one pixel electrode including a thin film transistor of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention. In this case, the thin film transistors forming the driving elements of the driving circuit unit are the same as those of the thin film transistors, which are switching elements formed in the pixel region, and thus are not shown in the drawings.

As shown, the array substrate 201 for a liquid crystal display device according to the second embodiment of the present invention is formed with a gate wiring (not shown) extending in one direction on the transparent insulating substrate 201, the gate wiring ( And a gate electrode 205 is formed in each pixel area.

In addition, a gate insulating film 208 is formed on the entire surface of the gate wiring (not shown) and the gate electrode 205, and all the layers are deposited on the gate insulating film 208 by the same process, The semiconductor layer 232 of the polysilicon of the triple layer structure which is crystallized by silicon is formed.

In this case, the semiconductor layer 232 is composed of a first polysilicon pattern 214, an impurity polysilicon pattern 226, and a second polysilicon pattern 230 from the bottom, and the first polysilicon pattern 214 is A first region 214a in contact with the gate insulating layer 208 and overlapping the source and drain electrodes 241 and 246 and having a first thickness t1 and the source and drain electrodes 241 and 246. The second region 214b has a fifth thickness t5 corresponding to the separation region, which is 200 mm to 400 mm thinner than the first thickness t1 and has a channel formed therein.

In addition, the impurity polysilicon pattern 226 is formed to be spaced apart from each other to correspond to the second region 214b of the first polysilicon pattern 214, and the second polysilicon pattern 230 is formed on the impurity. The polysilicon pattern 226 has the same shape and is spaced apart from each other. In this case, the second polysilicon pattern 230 is in contact with the source and drain electrodes 241 and 246 to form an ohmic contact. The reason for forming such an ohmic contact will be described later in the manufacturing method.

Next, source and drain electrodes 241 and 246 are formed on the triple layer semiconductor layer 232 to expose the second region 214b of the first polysilicon pattern 214 and are spaced apart from each other. The pixel region is connected to the source electrode 241 and crosses the gate line (not shown) on the gate insulating layer 208, and a data line (not shown) is formed.

In this case, the gate electrode 205, the gate insulating film 208, the triple layer semiconductor layer 232, and the source and drain electrodes 241 and 246 sequentially stacked on the substrate 201 may form a thin film transistor Tr. Is achieved.

On the other hand, although not shown in the drawing, the thin film transistor Tr having the above-described stacked structure is formed in the region where the driving circuit other than the pixel region is formed to form the driving element.

Next, a passivation layer 250 is formed on the thin film transistor Tr, and a drain contact hole 253 is formed in the passivation layer 250 for the thin film transistor Tr formed in the pixel area and operating as a switching element. The drain electrode 246 is exposed by a portion of the drain electrode 246, and the pixel electrode 260 is formed in contact with the drain electrode 246 exposed through the drain contact hole 253.

As a modification according to the second embodiment having such a structure, other components are the same as the above-described second embodiment, and the second polysilicon pattern is omitted so that the impurity polysilicon patterns spaced from each other are respectively source and drain. It may be formed in contact with the electrode. In this case, since the semiconductor layer has a double layer structure, it is structurally similar to an array substrate for a liquid crystal display device having a general amorphous silicon layer and an impurity amorphous silicon layer as a semiconductor layer, but in the modification of the second embodiment, the semiconductor layer is an AMFC process. It can be said that there is a difference in that all of them are crystallized into polysilicon.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to a second embodiment of the present invention having the above-described structure will be described. In this case, although not shown in the drawing, the driving circuit unit may have a thin film transistor for a driving device having the same stacked structure as the thin film transistor formed in the pixel region.

7A to 7I are cross-sectional views illustrating manufacturing steps of one pixel area of an array substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

First, as shown in FIG. 7A, the transparent insulating substrate 201 is heat treated at a temperature of 700 ° C. to 750 ° C. for 30 to 60 minutes with varying temperatures. This is to prevent the substrate 201 from being deformed due to high temperature during the AMFC process in the future. Of course, such an annealing process may be omitted since the AMFC process proceeds for a very short time.

Subsequently, a metal material having a relatively high melting point, such as chromium (Cr) or molybdenum (Mo), is deposited on the substrate 201 subjected to the heat treatment using a sputtering device, and then patterned to form the gate electrode 205 and the like. Connected to form a gate wiring (not shown) extending in one direction.

Next, as shown in FIG. 7B, after the substrate 101 on which the gate wiring (not shown) and the gate electrode 205 are formed is moved to the chamber 290 of a chemical vapor deposition (CVD) equipment, In order to form a different kind of gas atmosphere according to the material to be deposited, for example, to form a silicon nitride (SiNx) layer, a mixed gas atmosphere of SiH ₄ / N ₂ or a SiH ₄ / NH ₃ mixed gas is formed. In order to form a silicon oxide (SiO ₂ ) layer, after forming a SiH ₄ / N ₂ O mixed gas atmosphere, a plasma is formed in the chamber 290 on the substrate 201 where the gate electrode 205 is formed. A gate insulating film 208 of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed on the entire surface.

Next, after changing the mixed gas atmosphere in which the gate insulating film 208 is continuously formed in the same chamber 290 to a mixed gas atmosphere of SiH ₄ / H ₂ , plasma is formed in the chamber 290 to form the gate insulating film. A first pure amorphous silicon layer 212 having a first thickness t1 on the order of 1200 mW to 2000 mW is formed over the 208.

Thereafter, the mixed gas atmosphere in which the first pure amorphous silicon layer 212 is formed in the same chamber 290 is changed to the mixed gas quartile of SiH ₄ / PH ₃ / H ₂ , and then plasma is formed to form the first pure water. The impurity amorphous silicon layer 223 is formed on the amorphous silicon layer 212 to have a thickness of about 300 kPa to about 500 kPa, and the mixed gas atmosphere in the chamber 290 is changed to SiH ₄ / H _2, and then plasma is formed. As a result, the second pure amorphous silicon layer 227 is formed on the impurity amorphous silicon layer 223 to have a thickness of about 300 mW to about 500 mW.

In this case, the second pure amorphous silicon layer 227 may be omitted. The second pure amorphous silicon layer 227 undergoes a thermal annealing process due to the characteristics of the manufacturing method of the second embodiment of the present invention. At this time, the impurities in the impurity amorphous silicon 227 layer including the impurities diffuse into the first pure amorphous silicon layer 212 (more precisely, after the AMFC process, so that the first polysilicon pattern is formed). The impurity amorphous silicon layer 223 in order to minimize the effect on the portion where the channel is to be formed in the first pure amorphous silicon layer 212 (first polysilicon pattern) by diffusion of impurities by thermal annealing. The first pure amorphous silicon layer 212 is further formed by forming a second pure amorphous silicon layer 227 on the upper part of the second pure amorphous silicon layer 227 to diffuse impurities into the second pure amorphous silicon silicon layer 227 (the second polysilicon pattern). This is to minimize the diffusion of impurities into () the first polysilicon pattern. In this case, the second pure amorphous silicon layer 227 (the second polysilicon pattern) finally forms an ohmic contact layer by diffusion of the impurities. If this is omitted, the impurity amorphous silicon layer 223 (the impurity polysilicon pattern) finally contacts the source and drain electrodes to form an ohmic contact layer.

Meanwhile, in the second embodiment of the present invention, the first pure amorphous silicon layer 212, the impurity amorphous silicon layer 223, and the second pure amorphous silicon layer 227 are continuously the same chamber 290 without breaking the vacuum. By depositing in), it is possible to prevent a decrease in bonding strength due to discontinuous deposition accompanied with exposure to the atmosphere as in the first embodiment. Except for mixed gas atmosphere, since it is continuously deposited in the same chamber 290, other environments (especially deposition temperature) are the same or similar, so the temperature difference in manufacturing the thin film transistor (when only chemical vapor deposition is performed, it is 350 ° C to 450 ° C. When the self-crystallization is carried out, it is possible to prevent the lifting phenomenon due to the decrease in the bonding force caused by the difference in the interlayer stress characteristics according to 700 ℃ to 750 ℃).

Next, as shown in FIG. 7C, the second pure amorphous silicon layer (FIG. 7A) is applied by applying a photoresist onto the second procedure amorphous silicon layer (227 of FIG. 7B) and performing development after diffraction exposure or halftone exposure. A first photoresist pattern 281a is formed on a portion 227 of 7b except for a region where a channel is to be formed, and at the same time for the region where the channel should be formed. A second photoresist pattern (not shown) that is thinner than the photoresist pattern 281a is formed.

Thereafter, the second pure amorphous silicon layer 227 of FIG. 7B exposed to the outside of the first and second photoresist patterns 281a (not shown), the impurities and the first pure amorphous silicon layer 223 of FIG. 7B. By removing 212, a first pure amorphous silicon pattern 213, an impurity amorphous silicon pattern 224, and a second pure amorphous silicon pattern 228 having the same shape are formed in a region where the semiconductor layer is to be formed.

Subsequently, ashing is performed to remove the second photoresist pattern (not shown), thereby exposing the second pure amorphous silicon pattern 228 corresponding to a region where the channel is to be formed.

Next, as shown in FIG. 7D, the second pure amorphous silicon pattern 228 of FIG. 7C and a lower portion thereof exposed to the outside of the first photoresist pattern 281a by performing primary dry etching. By removing the impurity amorphous silicon pattern 224 of FIG. 7C, the second amorphous silicon pattern 229 and the impurity amorphous silicon pattern 225 are formed to expose the first amorphous silicon pattern 213 and to be spaced apart from each other. .

Subsequently, by performing the first dry etching for a predetermined time, the thickness t2 of about 100 μs is also removed with respect to the exposed first pure amorphous silicon pattern 213. This is to completely remove the impurity amorphous silicon pattern (224 of FIG. 7C) on the first pure amorphous silicon pattern 213 by performing excessive etching. If the dry etching process is performed to remove only the impurity amorphous silicon pattern 224 of FIG. 7C, the impurity amorphous silicon remains minutely corresponding to the region where the channel is to be formed. The characteristic annealing process of the present invention is to prevent the source of impurities in the impurity amorphous silicon (phosphorus (P) is diffused so that the semiconductor layer can not operate smoothly as a switching element).

Accordingly, the first pure amorphous silicon pattern 2113 may include a first region 213a having a first thickness t1 and a fourth thickness (t2) that is thinner than the first thickness t1 by a thickness t2. It is divided into a second region 213b having t4).

Next, as shown in FIG. 7E, the first photoresist pattern (281a in FIG. 7D) remaining on the second pure amorphous silicon pattern 229 spaced apart from each other by ashing or stripping is performed. Remove it completely.

Thereafter, the magnetic crystallization chamber 293 may apply an alternating magnetic field to the substrate 201 from which the first photoresist pattern 281a of FIG. 7D is removed in a direction perpendicular to the substrate 201 at a specific temperature range. After moving in, it is placed on a stage (not shown) in the self crystallization process chamber 293.

Thereafter, the atmosphere in the self-crystallization process chamber 293 is warmed to 700 ° C. to 750 ° C., and then an alternating magnetic field (AMF) perpendicular to the substrate 201 is applied for 1 second to 60 seconds in the heated atmosphere. do.

At this time, it is preferable to expose the surface of the substrate 201 to the alternating magnetic field in such a manner that the alternating magnetic field generator 295 located above and below the substrate 201 performs a linear reciprocating motion. That is, the AC magnetic field generating device 295 simultaneously moves up and down the substrate 201 in a form of scanning, and the first pure amorphous silicon pattern (213 in FIG. 7D) and the impurity amorphous silicon pattern (in FIG. 7D). 225 and a second order amorphous silicon pattern (229 in FIG. 7D) are exposed to an alternating magnetic field (AMF). When the AMFC process is performed, the first pure amorphous silicon pattern (213 in FIG. 7D), the impurity amorphous silicon pattern (225 in FIG. 7D), and the second pure amorphous silicon pattern (229 in FIG. 7D) are respectively the first poly. The silicon pattern 214, the impurity polysilicon pattern 226, and the second polysilicon pattern 230 are changed.

At this time, the AMFC process is performed in a high temperature atmosphere, and the first and second polysilicon patterns 214 in which impurities (typically phosphorus (P), which is a Group 5 element) in the impurity polysilicon pattern 225 are disposed above and below , 230, but diffused into the first and second polysilicon patterns 214 and 230 substantially except for the second region 214b in which the channel in the first polysilicon pattern 214 is to be formed. The first and second polysilicon patterns 214 and 230 of impurities are formed. However, the diffusion of impurities may not occur when the AMFC process is performed for a relatively short time. The pattern names in the semiconductor layer 232 at this stage may be the first and second polysilicon patterns 214 and 230. This is called.

Next, as shown in FIG. 7F, a metal material is deposited on the semiconductor layer 232 of the substrate 201 subjected to the AMFC process to form a metal layer (not shown), and subsequently a photoresist is applied onto the metal layer. The third photoresist pattern 282 is formed in correspondence with the portion where the source and drain electrodes are to be formed by exposing and developing the same. In this case, the third photoresist pattern 282 is formed to be removed from the spaced apart area between the second pure polysilicon pattern 230 (or the impurity polysilicon pattern 226).

Next, the metal layer (not shown) exposed to the outside of the third photoresist pattern 282 is removed by etching to remove the spaced apart region of the second polysilicon pattern 230 (or the impurity polysilicon pattern 226). Source and drain electrodes 241 and 246 which completely cover the semiconductor layer 232 and are spaced apart from each other, and are simultaneously connected to the source electrode 241 on the gate insulating layer 208 and the gate wiring (not shown). Data lines (not shown) defining pixel regions are formed to cross each other.

Thereafter, the second dry etching is performed to etch the second region 214b of the first polysilicon pattern exposed between the source and drain electrodes 241 and 246. In this case, the thickness t4 that is etched and removed by the dry etching is preferably 100 kPa to 300 kPa.

In this case, after forming the source and drain electrodes 241 and 246 in the state where the thickness t2 of about 100 mm is already removed from the surface in the process step shown in FIG. 7D and has the fourth thickness t4, the secondary The source and drain electrodes are further etched by a thickness t3 of 100 kPa to 300 kPa by dry etching, and are removed by a thickness t6 of about 200 kPa to 400 kPa as a whole by the first and second dry etching. The fifth thickness t5, which is the thickness of the second region 214b exposed to the outside of the 241 and 246, becomes the first first thickness t1, that is, 800 Å to 1800 든, reduced by 200 Å to 400 Å at 1200 Å to 2000 Å. .

In this case, the final thicknesses t1 and t5 of each of the first region 241a and the second region 214b of the first polysilicon pattern 214 are experimentally determined by the mobility of the thin film transistor Tr having such a structure. And the thicknesses t1 and t5 when the transfer curve characteristics show the best state, the thicknesses t1 and t5 of the first polysilicon pattern are also important points in the second embodiment of the present invention. .

Next, as shown in FIG. 7G, the substrate on which the first polysilicon pattern 214 has a first region 214a having a first thickness t1 and a second region 214b having a fifth thickness t5 is formed. The third photoresist pattern remaining on 201 (282 of FIG. 7F) is removed by ashing or stripping.

Subsequently, the substrate 201 from which the third photoresist pattern (282 of FIG. 7F) is removed is moved to a chamber of a plasma generator 297, for example, a chemical vapor deposition apparatus, and then placed in a plasma for about 300 to 600 seconds. The hydrogenation process is carried out to expose. This is to improve the interface characteristics at the interface between each of the polysilicon patterns 214, 226, and 230.

As shown in FIG. 7H, an entire surface is deposited by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the source and drain electrodes 141 and 146 on the hydrophobized substrate 201. A protective layer 250 is formed on the substrate.

Then, the substrate 201 on which the protective layer 250 is formed is moved to a heat treatment equipment 299 having a chamber capable of being heated to a temperature of 300 ° C. to 500 ° C., for example, a curing furnace, and then an atmosphere of 380 ° C. to 420 ° C. Thermal annealing is carried out for 1 to 3 hours at.

The reason for performing such thermal annealing is to heal a silicon internal state damaged on the surface by primary and secondary dry etching, to make a more stable state, and to make the polysilicon patterns 214, 226, This is to improve the interfacial properties by improving the interfacial property between the interfaces 230 and between the first polysilicon pattern 214 and the gate insulating film 208 to improve the transfer curve characteristics.

Further, the thermal annealing may be performed in the impurity polysilicon pattern 226 in the case of the second embodiment of the present invention, particularly in the case of the structure having the second polysilicon pattern 230 on the impurity polysilicon pattern 226. The second polysilicon pattern 230 in contact with the source and drain electrodes 241 and 246 may form an ohmic contact by diffusing impurities in a vertical direction.

As a modification, when the second polysilicon pattern 230 is not formed, the thermal annealing may be selectively performed or omitted, but when the second polysilicon pattern 230 is formed, the thermal annealing may be performed. Thermal annealing helps the second polysilicon pattern 230 in contact with the source and drain electrodes 241, 246 to make an ohmic contact.

Next, as illustrated in FIG. 7I, the drain contact hole 253 exposing the drain electrode 246 formed in the pixel region by patterning the protective layer 250 on the thermally annealed substrate 201. ).

In this case, the drain contact hole is not formed in the thin film transistor for the driving element formed in the region where the driving circuit is formed.

Thereafter, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited and patterned on the passivation layer 250 where the drain contact hole 253 is formed. By forming the pixel electrode 260 in contact with the drain electrode 246 through 253, the array substrate 201 for a liquid crystal display device according to the second embodiment of the present invention may be completed.

The array substrate for a liquid crystal display device according to the present invention has an effect of improving the mobility characteristics by several tens to several hundred times by AMFC treatment of a pure amorphous silicon layer.

Therefore, the thin film transistor having the AMFC-treated semiconductor layer can be used as a driving device as well as a switching device. Since the external driving circuit is not provided separately, the cost can be reduced and the integration of the driving device can be increased. As a result, the product can be made compact.

In addition, in the conventional method for manufacturing an array substrate for a liquid crystal display device using polysilicon, a 7-9 mask process is typically performed by doping or the like, but the product is completed as described above. In the case of an array substrate, polysilicon is used as a semiconductor layer and does not require a separate process such as doping, and thus the product can be completed by a 5 mask process, thereby reducing productivity.

In addition, since the semiconductor layers are all formed in one chamber while changing the mixed gas atmosphere, there are no discrete deposits between the interfaces, and thermal annealing further increases the interfacial properties in each of the semiconductor layers. And an array substrate for a liquid crystal display device of polysilicon having improved transfer curve characteristics.

Claims (28)

A substrate; A gate electrode formed on the substrate; A gate insulating film formed over the gate electrode; A semiconductor layer comprising a first polysilicon layer having a first region having a first thickness sequentially stacked over the gate insulating film, a second region having a second thickness smaller than the first thickness, and an impurity polysilicon layer spaced apart from each other. and; Source and drain electrodes formed on and in contact with the ohmic contact layer of the semiconductor layer, respectively Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the first polysilicon layer and the impurity polysilicon layer are crystallized by an alternating magnetic field crystallization method. The method of claim 1, And a second polysilicon layer spaced apart from each other on the impurity polysilicon layer. The method of claim 1, And the first region overlaps the gate electrode. The method according to claim 1 or 3, A protective layer formed by exposing the drain electrode over the source and drain electrodes; A pixel electrode formed in contact with the exposed drain electrode on the passivation layer Array substrate for a liquid crystal display device further comprising. The method of claim 5, wherein A gate wiring connected to the gate electrode and formed; A data line connected to the source electrode and crossing the gate line Array substrate for a liquid crystal display device further comprising. The method according to claim 1 or 3, And said first thickness is in the range of 1200 mW to 2000 mW. The method of claim 7, wherein And a difference between the first thickness and the second thickness is 200 mW to 400 mW. Forming a gate electrode on the substrate; Sequentially forming a gate insulating film, a first pure amorphous silicon pattern having a first thickness, an impurity amorphous silicon pattern spaced apart from each other, and a second pure amorphous silicon pattern spaced apart from each other over the gate electrode; By performing alternating magnetic field crystallization, the first pure amorphous silicon pattern, the impurity amorphous silicon pattern, and the second pure amorphous silicon pattern are respectively converted into the first polysilicon pattern, the impurity polysilicon pattern, and the second polysilicon pattern. Crystallization; Forming source and drain electrodes that are in contact with the second polysilicon pattern and spaced apart from each other to expose the first polysilicon pattern; Forming a protective layer over the source and drain electrodes; Patterning the passivation layer to form a drain contact hole exposing the gate electrode; Forming a pixel electrode in contact with the drain electrode through the drain contact hole Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 9, And etching the first polysilicon pattern exposed to the outside of the source and drain electrodes and removing the first polysilicon pattern by a second thickness. The method of claim 10, And said second thickness is in the range of 200 kV to 400 kV. The method of claim 9, Forming the first pure amorphous silicon pattern, the impurity amorphous silicon pattern spaced apart from each other, and the second pure amorphous silicon pattern spaced from each other, Forming a first pure amorphous silicon layer, an impurity amorphous silicon layer, and a second pure amorphous silicon layer sequentially in the vacuum chamber of the chemical vapor deposition apparatus over the gate insulating layer without breaking the vacuum; Forming a first photoresist pattern on the second pure amorphous silicon layer and a second photoresist pattern thinner than the first photoresist pattern; By removing the second pure amorphous silicon layer, the impurity amorphous silicon layer and the first pure amorphous silicon layer exposed to the outside of the first and second photoresist patterns, the first pure amorphous silicon pattern, the impurity amorphous silicon pattern and the second Forming a pure amorphous silicon pattern; Removing the second photoresist pattern to expose the second pure amorphous silicon pattern; Removing the second pure amorphous silicon pattern exposed to the outside of the first photoresist pattern and the impurity amorphous silicon pattern thereunder; Method of manufacturing an array substrate for a liquid crystal display device further comprising. The method of claim 12, Forming the impurity amorphous silicon pattern spaced apart from each other, and the second pure amorphous silicon pattern spaced from each other, Etching the first pure amorphous silicon pattern exposed to the outside of the impurity amorphous silicon pattern spaced apart from each other to have a third thickness thinner than the first thickness Method of manufacturing an array substrate for a liquid crystal display device further comprising. The method of claim 13, The first thickness and the third thickness is a manufacturing method of the array substrate for a liquid crystal display device characterized in that the difference by 100Å. Forming a gate electrode on the substrate; Sequentially forming a gate insulating film and a first pure amorphous silicon pattern having a first thickness and an impurity amorphous silicon pattern spaced apart from each other on the gate electrode; Crystallizing the first pure amorphous silicon pattern and the impurity amorphous silicon pattern into a first polysilicon pattern and an impurity polysilicon pattern by performing alternating magnetic field crystallization; Forming source and drain electrodes contacting the impurity polysilicon pattern upwardly and spaced apart from each other to expose the first polysilicon pattern; Forming a protective layer over the source and drain electrodes; Patterning the protective layer to form a drain contact hole exposing the drain electrode; Forming a pixel electrode in contact with the drain electrode through the drain contact hole Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 15, And removing the first polysilicon pattern exposed to the outside of the source and drain electrodes by etching a second thickness. The method of claim 16, And said second thickness is in the range of 200 kV to 400 kV. The method of claim 15, Forming an impurity amorphous silicon pattern spaced apart from the first pure amorphous silicon pattern, Etching the first pure amorphous silicon pattern exposed to the outside of the impurity amorphous silicon pattern spaced apart from each other to have a third thickness thinner than the first thickness Method of manufacturing an array substrate for a liquid crystal display device further comprising. The method of claim 18, The first thickness and the third thickness is a manufacturing method of the array substrate for a liquid crystal display device characterized in that the difference by 100Å. The method according to claim 9 or 15, The alternating magnetic field crystallization is performed in a chamber having an atmosphere of 700 ° C. to 750 ° C. A method of manufacturing an array substrate for a liquid crystal display device. The method of claim 20, The alternating magnetic field crystallization may be performed such that an alternating magnetic field generator is linearly reciprocated with the alternating magnetic field generating device positioned above and below the substrate positioned in the chamber. Way. The method of claim 20, The alternating magnetic field crystallization is performed for 1 to 60 seconds. The method according to claim 9 or 15, And thermally annealing the substrate on which the protective layer is formed to form the ohmic contact between the second polysilicon pattern and the source and drain electrodes. The method of claim 23, The thermal annealing (thermal annealing) is a method of manufacturing an array substrate for a liquid crystal display device, characterized in that for 1 to 3 hours in an atmosphere of 280 ℃ to 420 ℃. The method according to claim 10 or 16, And removing the first polysilicon pattern exposed to the outside of the source and drain electrodes by removing the second polysilicon pattern by a second thickness, and then performing a hydrogenation process to expose the hydrogen plasma to a hydrogen plasma. . The method of claim 25, The hydrogenation process is a manufacturing method of an array substrate for a liquid crystal display device, characterized in that 300 seconds to 600 seconds. The method according to claim 9 or 15, The method of manufacturing the array substrate for a liquid crystal display device further comprising the step of heat-treating the substrate for 30 to 60 minutes in the atmosphere of 700 ℃ to 750 ℃ before forming the gate electrode. The method according to claim 9 or 15, The forming of the gate electrode may further include forming a gate wiring connected to the gate electrode, and the forming of the source and drain electrodes may include forming a data wiring connected to the source electrode and crossing the gate wiring. A method of manufacturing an array substrate for a liquid crystal display further comprising the step of.

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