CN105161458B - The preparation method of TFT substrate - Google Patents
The preparation method of TFT substrate Download PDFInfo
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- CN105161458B CN105161458B CN201510504952.1A CN201510504952A CN105161458B CN 105161458 B CN105161458 B CN 105161458B CN 201510504952 A CN201510504952 A CN 201510504952A CN 105161458 B CN105161458 B CN 105161458B
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 75
- 150000002500 ions Chemical class 0.000 claims abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 239000012212 insulator Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- -1 boron ion Chemical class 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 149
- 238000010586 diagram Methods 0.000 description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 14
- 108091006146 Channels Proteins 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of preparation method of TFT substrate, it is lightly doped by carrying out p-type to polysilicon layer first, then polysilicon layer is lightly doped to p-type again and carries out patterned process, it can ensure to be lightly doped in processing procedure in p-type, p-type ion is not easy to be injected into the silicon oxide layer below polysilicon layer, damage to the silicon oxide layer is smaller, almost it can be ignored, compared with traditional procedure for producing, the preparation method of the present invention does not increase manufacturing process and operating time, the order of processing procedure is lightly doped with p-type only by the patterned process of adjustment polysilicon layer, it can make obtained TFT substrate that there is good combination property and excellent electrical performance.
Description
Technical field
The present invention relates to semiconductor fabrication process, more particularly to a kind of preparation method of TFT substrate.
Background technology
With the development of Display Technique, the plane such as liquid crystal display (Liquid Crystal Display, LCD) display dress
Put because having the advantages that high image quality, power saving, fuselage is thin and has a wide range of application, and be widely used in mobile phone, TV, individual number
The various consumption electronic products such as word assistant, digital camera, notebook computer, desktop computer, turn into the master in display device
Stream.
It is backlight liquid crystal display that liquid crystal display device on existing market is most of, it include liquid crystal display panel and
Backlight module (backlight module).The operation principle of liquid crystal display panel is put among the parallel glass substrate of two panels
Liquid crystal molecule is put, there are many tiny electric wires vertically and horizontally among two panels glass substrate, liquid crystal is controlled by whether being powered
Molecular changes direction, the light of backlight module is reflected into generation picture.
Usual liquid crystal display panel is by color membrane substrates (CF, Color Filter), thin film transistor base plate (TFT, Thin
Film Transistor), the liquid crystal (LC, Liquid Crystal) that is sandwiched between color membrane substrates and thin film transistor base plate and
Sealing glue frame (Sealant) forms, and its moulding process generally comprises：Leading portion array (Array) processing procedure (film, gold-tinted, etching and
Stripping), stage casing is into box (Cell) processing procedure (TFT substrate is bonded with CF substrates) and back segment module group assembling processing procedure (driving IC and printing
Press fit of circuit boards).Wherein, leading portion Array processing procedures mainly form TFT substrate, in order to control the motion of liquid crystal molecule；Stage casing
Cell processing procedures mainly add liquid crystal between TFT substrate and CF substrates；Back segment module group assembling processing procedure mainly drives IC pressings
With the integration of printed circuit board (PCB), and then drive liquid crystal molecule rotate, display image.
As shown in figs. 1-7, it is a kind of existing preparation method of TFT substrate, comprises the following steps：
Step 1, as shown in Figure 1, there is provided a substrate 100, a metal level is deposited on the substrate 100, using one of light
Scribe journey and patterned process is carried out to the metal level, obtain spaced first light shield layer 210, the second light shield layer 220；
Step 2, as shown in Fig. 2 being sequentially depositing on first light shield layer 210, the second light shield layer 220 and substrate 100
Silicon nitride layer 300 and silicon oxide layer 400；
Step 3, as shown in figure 3, an amorphous silicon layer is deposited on the silicon oxide layer 400, using quasi-molecule laser annealing
The amorphous silicon layer is converted into polysilicon layer 500 by processing procedure；
Step 4, as shown in figure 4, using one of lithographic process to the polysilicon layer 500 carry out patterned process, obtain
Correspond respectively to first light shield layer 210, the first active layer 510 of the second light shield layer 220, the second active layer 520；
Step 5, as shown in figure 5, to first active layer 510, the second active layer 520 carry out p-type ion implanting, formed
First p-type is lightly doped with active layer 610, the second p-type is lightly doped with active layer 620；
Step 6, as shown in fig. 6, first p-type is lightly doped with active layer 610, the second p-type is lightly doped with active layer 620,
And a photoresist layer 700 is coated with silicon oxide layer 400, the photoresist layer 700 is exposed using one of gold-tinted processing procedure, developed,
Two end regions that first p-type is lightly doped with active layer 610 are exposed, are mask with the photoresist layer 700, to the first P
The both ends that type is lightly doped with active layer 610 carry out ion implanting, as shown in fig. 7, after removing the photoresist layer 700, obtain being located at institute
State the first p-type and be lightly doped with the N-type heavily doped region 612 at the both ends of active layer 610 and the p-type between two N-type heavily doped regions 612
Channel region 614 is lightly doped.
The preparation method of above-mentioned TFT substrate, patterned process is carried out to polysilicon layer 500 first, obtains the first of island
After active layer 510, the second active layer 520, then p-type ion implanting is carried out to the first active layer 510 and the second active layer 520, its
Shortcoming is：After etching the first active layer 510 of island, the second active layer 520, the exposed of silicon oxide layer 400 can be caused,
Can be by p-type ion implanting to exposing in next silicon oxide layer 400, to its lattice structure during carrying out p-type ion implanting
Damage, while p-type is ion implanted in silicon oxide layer 400 and is introduced into carrier, and the electrology characteristic of component may be made
Into certain influence.
It is therefore desirable to provide a kind of preparation method of improved TFT substrate, to solve the problems, such as to run into conventional process.
The content of the invention
It is an object of the invention to provide a kind of preparation method of TFT substrate, it is ensured that is lightly doped in p-type in processing procedure, p-type
Ion is not easy to be injected into the silicon oxide layer below polysilicon layer, and the damage to the silicon oxide layer is smaller, makes obtained
TFT substrate has good combination property and excellent electrical performance.
To achieve the above object, the present invention provides a kind of preparation method of TFT substrate, comprises the following steps：
Step 1, a substrate is provided, a metal level is deposited on the substrate, using one of lithographic process to the metal
Layer carries out patterned process, obtains spaced first light shield layer, the second light shield layer；
Step 2, it is sequentially depositing silicon nitride layer and silicon oxide layer on first light shield layer, the second light shield layer and substrate；
Step 3, an amorphous silicon layer is deposited on the silicon oxide layer, turned the amorphous silicon layer using low temperature crystallization technique
Turn to polysilicon layer；
Step 4, p-type ion implanting is carried out to the polysilicon layer, form p-type and polysilicon layer is lightly doped；
Step 5, polysilicon layer progress patterned process is lightly doped to the p-type using one of lithographic process, is distinguished
Corresponding to first light shield layer, the first active layer of the second light shield layer, the second active layer；
Step 6, a photoresist layer is coated with first active layer, the second active layer and silicon oxide layer, using yellow together
Light processing procedure is exposed to the photoresist layer, developed, and exposes two end regions of first active layer, using the photoresist layer as
Mask, N-type ion implanting is carried out to the both ends of first active layer, after removing the photoresist layer, obtain being located at described first
The N-type heavily doped region at active layer both ends and the p-type lightly doped district between two N-type heavily doped regions；
Step 7, gate insulator is deposited on first active layer, the second active layer and silicon oxide layer, in the grid
A metal level is deposited on the insulating barrier of pole, patterned process is carried out to the metal level using one of lithographic process, it is right respectively to obtain
Should be in the first active layer, the first grid of the second active layer, second grid；
Step 8, using the first grid as mask, N-type is carried out to the both ends of the p-type lightly doped district of first active layer
Ion implanting, formed in the p-type lightly doped district positioned at the N-type lightly doped district at both ends and between two N-type lightly doped districts
P-type channel region is lightly doped；
Step 9, a photoresist layer is coated with the first grid, second grid and gate insulator, using one of gold-tinted
Processing procedure is exposed to the photoresist layer, developed, and exposes active corresponding to described second on second grid and gate insulator
The region of layer top, using the second grid as mask, p-type ion implanting is carried out to the both ends of second active layer, removed
After the photoresist layer, obtain positioned at the p-type heavily doped region at the second active layer both ends and between two p-type heavily doped regions
P-type channel region is lightly doped；
Step 10, interlayer insulating film, source and drain are sequentially formed on the first grid, second grid and gate insulator
Pole.
In the step 1, the substrate is glass substrate；First light shield layer, the material of the second light shield layer are molybdenum.
In the step 3, the low temperature crystallization technique is PRK annealing process.
Lithographic process in the step 5 includes applying photoresistance, exposure, development and dry ecthing procedure.
In the step 7, the material of the gate insulator is the combination of silicon nitride and silica.
The p-type ion of step 4 and step 9 injection is boron ion.
The N-type ion of step 6 and step 8 injection is phosphonium ion.
In first active layer, the N-type ion concentration range in the N-type heavily doped region is 1014~2 ×
1015ions/cm2, the N-type ion concentration range in the N-type lightly doped district is 1013~3 × 1013ions/cm2, the p-type is light
P-type ion concentration range in doped channel regions is 1012~5 × 1012ions/cm2。
In second active layer, the p-type ion concentration range in the p-type heavily doped region is 1014~2 ×
1015ions/cm2, the p-type ion concentration range that the p-type is lightly doped in channel region is 1012~5 × 1012ions/cm2。
Beneficial effects of the present invention：The present invention provides a kind of preparation method of TFT substrate, by entering first to polysilicon layer
Row p-type is lightly doped, and polysilicon layer is then lightly doped to p-type again and carries out patterned process, it is ensured that is lightly doped in p-type in processing procedure, P
Type ion is not easy to be injected into the silicon oxide layer below polysilicon layer, and the damage to the silicon oxide layer is smaller, almost may be used
To ignore, compared with traditional procedure for producing, preparation method of the invention does not increase manufacturing process and operating time,
The order of processing procedure is lightly doped with p-type only by the patterned process of adjustment polysilicon layer, you can there is obtained TFT substrate
Good combination property and excellent electrical performance.
Brief description of the drawings
In order to be further understood that the feature of the present invention and technology contents, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, be not used for being any limitation as the present invention.
In accompanying drawing,
Fig. 1 is a kind of schematic diagram of the preparation method step 1 of existing TFT substrate；
Fig. 2 is a kind of schematic diagram of the preparation method step 2 of existing TFT substrate；
Fig. 3 is a kind of schematic diagram of the preparation method step 3 of existing TFT substrate；
Fig. 4 is a kind of schematic diagram of the preparation method step 4 of existing TFT substrate；
Fig. 5 is a kind of schematic diagram of the preparation method step 5 of existing TFT substrate；
Fig. 6-7 is a kind of schematic diagram of the preparation method step 6 of existing TFT substrate；
Fig. 8 is the schematic diagram of the preparation method step 1 of the TFT substrate of the present invention；
Fig. 9 is the schematic diagram of the preparation method step 2 of the TFT substrate of the present invention；
Figure 10 is the schematic diagram of the preparation method step 3 of the TFT substrate of the present invention；
Figure 11 is the schematic diagram of the preparation method step 4 of the TFT substrate of the present invention；
Figure 12 is the schematic diagram of the preparation method step 5 of the TFT substrate of the present invention；
Figure 13-14 is the schematic diagram of the preparation method step 6 of the TFT substrate of the present invention；
Figure 15 is the schematic diagram of the preparation method step 7 of the TFT substrate of the present invention；
Figure 16 is the schematic diagram of the preparation method step 8 of the TFT substrate of the present invention；
Figure 17-18 is the schematic diagram of the preparation method step 9 of the TFT substrate of the present invention.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
The present invention provides a kind of preparation method of TFT substrate, comprises the following steps：
Step 1, as shown in Figure 8, there is provided a substrate 10, a metal level is deposited on the substrate 10, using one of photoetching
Processing procedure carries out patterned process to the metal level, obtains spaced first light shield layer 21, the second light shield layer 22.
Specifically, the substrate 10 is glass substrate, first light shield layer 21, the material of the second light shield layer 22 are molybdenum
(Mo)。
Step 2, as shown in figure 9, being sequentially depositing nitrogen on first light shield layer 21, the second light shield layer 22 and substrate 10
SiClx layer 30 and silicon oxide layer 40.
Step 3, as shown in Figure 10, deposit an amorphous silicon layer on the silicon oxide layer 40, using low temperature crystallization technique will
The amorphous silicon layer is converted into polysilicon layer 50.
Specifically, the low temperature crystallization technique is PRK annealing process.
Step 4, as shown in figure 11, to the polysilicon layer 50 carry out p-type ion implanting, formed p-type polysilicon is lightly doped
Layer 60.
Compared with prior art, the present invention have adjusted the p-type of polysilicon layer 50 and the suitable of processing procedure and patterned process be lightly doped
Sequence, the p-type of polysilicon layer 50 is lightly doped before processing procedure is placed in patterned process, so as to ensure to be lightly doped in processing procedure in p-type, P
Type ion is not easy to be injected into the silicon oxide layer 40 of the lower section of polysilicon layer 50, and the damage to the silicon oxide layer 40 is smaller,
Almost it can be ignored so that TFT substrate produced by the present invention has good combination property and excellent electrical performance.
Step 5, as shown in figure 12, polysilicon layer 60 is lightly doped to the p-type using one of lithographic process and patterned
Processing, obtains corresponding respectively to first light shield layer 21, the first active layer 61 of the second light shield layer 22, the second active layer 62.
Specifically, the lithographic process includes applying photoresistance, exposure, development and dry ecthing procedure.
Step 6, as shown in figure 13, be coated with one on first active layer 61, the second active layer 62 and silicon oxide layer 40
Photoresist layer 70, the photoresist layer 70 is exposed using one of gold-tinted processing procedure, developed, exposes first active layer 61
Two end regions, it is mask with the photoresist layer 70, N-type ion implanting, such as Figure 14 is carried out to the both ends of first active layer 61
It is shown, after removing the photoresist layer 70, obtain positioned at the N-type heavily doped region 611 at the both ends of the first active layer 61 and positioned at two
P-type lightly doped district 613 between N-type heavily doped region 611.
Step 7, as shown in figure 15, deposit grid on first active layer 61, the second active layer 62 and silicon oxide layer 40
Pole insulating barrier 80, a metal level is deposited on the gate insulator 80, the metal level is carried out using one of lithographic process
Patterned process, obtain corresponding respectively to the first active layer 61, the first grid 91 of the second active layer 62, second grid 92.
Specifically, the material of the gate insulator 80 is the combination of silicon nitride and silica.
Step 8, as shown in figure 16, be mask with the first grid 91, the p-type of first active layer 61 be lightly doped
The both ends in area 613 carry out N-type ion implanting, and the N-type lightly doped district positioned at both ends is formed in the p-type lightly doped district 613
615 and the p-type between two N-type lightly doped districts 615 channel region 617 is lightly doped.
Specifically, the N-type ion that the step 6 and step 8 are injected is phosphonium ion.
Specifically, in first active layer 61, the N-type ion concentration range in the N-type heavily doped region 611 is 1014
~2 × 1015ions/cm2, the N-type ion concentration range in the N-type lightly doped district 615 is 1013~3 × 1013ions/cm2,
The p-type ion concentration range that the p-type is lightly doped in channel region 617 is 1012~5 × 1012ions/cm2。
Step 9, as shown in figure 17, be coated with a light on the first grid 91, second grid 92 and gate insulator 80
Resistance layer 110, the photoresist layer 110 is exposed using one of gold-tinted processing procedure, developed, second grid 92 is exposed and grid is exhausted
Correspond to the region of the top of the second active layer 62 in edge layer 80, be mask with the second grid 92, have to described second
The both ends of active layer 62 carry out p-type ion implanting, as shown in figure 18, after removing the photoresist layer 110, obtain having positioned at described second
Channel region 623 is lightly doped in the p-type heavily doped region 621 at the both ends of active layer 62 and the p-type between two p-type heavily doped regions 621.
Specifically, the p-type ion that the step 4 and step 9 are injected is boron ion.
Specifically, in second active layer 62, the p-type ion concentration range in the p-type heavily doped region 621 is 1014
~2 × 1015ions/cm2, the p-type ion concentration range that the p-type is lightly doped in channel region 623 is 1012~5 × 1012ions/
cm2。
Step 10, sequentially form layer insulation on the first grid 91, second grid 92 and gate insulator 80
Layer, source-drain electrode, obtain the TFT substrate of the present invention.
In summary, the present invention provides a kind of preparation method of TFT substrate, and it is light to carry out p-type to polysilicon layer by first
Doping, polysilicon layer is then lightly doped to p-type again and carries out patterned process, it is ensured that is lightly doped in p-type in processing procedure, p-type ion
It is not easy to be injected into the silicon oxide layer below polysilicon layer, the damage to the silicon oxide layer is smaller, can almost ignore
Disregard, compared with traditional procedure for producing, preparation method of the invention does not increase manufacturing process and operating time, Jin Jintong
The order of processing procedure is lightly doped with p-type for the patterned process for crossing adjustment polysilicon layer, you can obtained TFT substrate is had well
Combination property and excellent electrical performance.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the appended right of the present invention
It is required that protection domain.
Claims (7)
1. a kind of preparation method of TFT substrate, it is characterised in that comprise the following steps：
Step 1, a substrate (10) is provided, a metal level is deposited on the substrate (10), using one of lithographic process to described
Metal level carries out patterned process, obtains spaced first light shield layer (21), the second light shield layer (22)；
Step 2, it is sequentially depositing silicon nitride layer on first light shield layer (21), the second light shield layer (22) and substrate (10)
(30) with silicon oxide layer (40)；
Step 3, an amorphous silicon layer is deposited on the silicon oxide layer (40), turned the amorphous silicon layer using low temperature crystallization technique
Turn to polysilicon layer (50)；
Step 4, p-type ion implanting is carried out to the polysilicon layer (50), form p-type and polysilicon layer (60) is lightly doped；
Step 5, polysilicon layer (60) progress patterned process is lightly doped to the p-type using one of lithographic process, is distinguished
Corresponding to first light shield layer (21), the first active layer (61) of the second light shield layer (22), the second active layer (62)；
Step 6, it is coated with a photoresist layer on first active layer (61), the second active layer (62) and silicon oxide layer (40)
(70), the photoresist layer (70) is exposed using one of gold-tinted processing procedure, developed, only exposes first active layer (61)
Two end regions, with the photoresist layer (70) for mask, N-type ion implanting is carried out to the both ends of first active layer (61),
After removing the photoresist layer (70), obtain being located at the N-type heavily doped region (611) at the first active layer (61) both ends and be located at
P-type lightly doped district (613) between two N-type heavily doped regions (611)；
Step 7, deposit gate insulator on first active layer (61), the second active layer (62) and silicon oxide layer (40)
(80) metal level, is deposited on the gate insulator (80), pattern is carried out to the metal level using one of lithographic process
Change is handled, and obtains corresponding respectively to first grid (91), the second grid of the first active layer (61), the second active layer (62)
(92)；
Step 8, with the first grid (91) for mask, to the two of the p-type lightly doped district (613) of first active layer (61)
End carries out N-type ion implanting, and N-type lightly doped district (615) and position positioned at both ends are formed on the p-type lightly doped district (613)
Channel region (617) is lightly doped in p-type between two N-type lightly doped districts (615)；
Step 9, it is coated with a photoresist layer on the first grid (91), second grid (92) and gate insulator (80)
(110), the photoresist layer (110) is exposed using one of gold-tinted processing procedure, developed, only exposes second grid (92) and grid
The region corresponded on pole insulating barrier (80) above second active layer (62), it is right with the second grid (92) for mask
The both ends of second active layer (62) carry out p-type ion implanting, after removing the photoresist layer (110), obtain positioned at described the
Ditch is lightly doped in the p-type heavily doped region (621) at two active layers (62) both ends and the p-type between two p-type heavily doped regions (621)
Road area (623)；
Step 10, sequentially form layer insulation on the first grid (91), second grid (92) and gate insulator (80)
Layer, source-drain electrode；
In first active layer (61), the N-type ion concentration range in the N-type heavily doped region (611) is 1014~2 ×
1015ions/cm2, the N-type ion concentration range in the N-type lightly doped district (615) is 1013~3 × 1013ions/cm2, it is described
The p-type ion concentration range that p-type is lightly doped in channel region (617) is 1012~5 × 1012ions/cm2；
In second active layer (62), the p-type ion concentration range in the p-type heavily doped region (621) is 1014~2 ×
1015ions/cm2, the p-type ion concentration range that the p-type is lightly doped in channel region (623) is 1012~5 × 1012ions/cm2。
2. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that in the step 1, the substrate (10)
For glass substrate；First light shield layer (21), the material of the second light shield layer (22) are molybdenum.
3. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that in the step 3, the low temperature crystallization
Technique is PRK annealing process.
4. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the lithographic process in the step 5 includes
Apply photoresistance, exposure, development and dry ecthing procedure.
5. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that in the step 7, the gate insulator
The material of layer (80) is the combination of silicon nitride and silica.
6. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the p-type of step 4 and step 9 injection
Ion is boron ion.
7. the preparation method of TFT substrate as claimed in claim 1, it is characterised in that the N-type of step 6 and step 8 injection
Ion is phosphonium ion.
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| US9780002B1 (en) * | 2016-06-06 | 2017-10-03 | Globalfoundries Inc. | Threshold voltage and well implantation method for semiconductor devices |
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| CN104465509A (en) * | 2013-09-18 | 2015-03-25 | 昆山国显光电有限公司 | OLED display device array substrate and preparation method thereof |
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