CN208738249U - Display panel - Google Patents
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- CN208738249U CN208738249U CN201821398328.3U CN201821398328U CN208738249U CN 208738249 U CN208738249 U CN 208738249U CN 201821398328 U CN201821398328 U CN 201821398328U CN 208738249 U CN208738249 U CN 208738249U
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Abstract
The utility model provides a kind of display panel, includes: a substrate, a grid, a gate insulating layer, a polysilicon layer, an interlayer dielectric layer and a first electrode pattern layer.The grid is set on the substrate.The gate insulating layer is located on the grid and the substrate.The polysilicon layer is set on the gate insulating layer, wherein the polysilicon layer includes source region, a drain region and the active area being located between the source area and the drain region.The interlayer dielectric layer is located on the gate insulating layer and the polysilicon layer, and there is the interlayer dielectric layer source electrode perforation to perforate with a drain electrode, the exposure source area and the drain electrode perforation exposure drain region wherein the source electrode is perforated.The first electrode pattern layer is located on the interlayer dielectric layer.
Description
Technical field
The utility model relates to a kind of display panel, and the display of photomask number can be reduced in particular to one kind
Panel.
Background technique
With the development of display technology, the planes such as liquid crystal display (Liquid Crystal Display, LCD) display dress
It sets because having many advantages, such as that high image quality, power saving, fuselage is thin and has a wide range of application, and is widely used in mobile phone, TV, a number
The various consumer electrical products such as word assistant, digital camera, laptop, desktop computer, become the master in display device
Stream.
For example, use low temperature polycrystalline silicon (LTPS) as the liquid crystal display of active area, due to low temperature polycrystalline silicon have compared with
High carrier mobility, therefore transistor can be made to obtain higher switching current ratio.Therefore in the charging current condition met the requirements
Under, the size of each pixel transistor can carry out downsizing, and then increase the transparent area of each pixel, to improve panel opening
Rate improves panel bright spot and high-resolution, and reduces panel power consumption.Therefore, low temperature polycrystalline silicon (LTPS) liquid crystal display can
Obtain preferable visual experience.
However, due to each pixel transistor size towards miniaturization direction develop, thus make photomask equipment at
The growth of this generation index.
Therefore, it is necessary to a kind of display panel is provided, to solve the problems of prior art.
Utility model content
In view of this, the present invention provides a kind of display panels, to solve to use photomask present in the prior art
Number is excessive, and then the problem of increase manufacturing cost.
The one of the utility model is designed to provide a kind of display panel, by the way that grid is flat as light shield layer, omission
Smooth layer and lower electrode (bottom ITO；BITO) layer is as pixel electrode, to reduce used in manufacture display panel
Photomask number, and then reduce manufacturing cost.
For the foregoing purpose for reaching the utility model, the utility model provides a kind of display panel, wherein the display surface
Plate includes: a substrate, a grid, a gate insulating layer, a polysilicon layer, an interlayer dielectric layer and a first electrode pattern layer.
The grid is set on the substrate.The gate insulating layer is located on the grid and the substrate.The polysilicon layer is set
On the gate insulating layer, wherein the polysilicon layer is comprising source region, a drain region and is located at the source area and institute
State the active area between drain region.The interlayer dielectric layer is located on the gate insulating layer and the polysilicon layer, described
There is interlayer dielectric layer source electrode perforation to perforate with a drain electrode, the exposure source area and the drain electrode wherein the source electrode is perforated
The perforation exposure drain region.The first electrode pattern layer is located on the interlayer dielectric layer.
In an embodiment of the utility model, the display panel further includes an electric material pattern layer, is located at described
In first electrode pattern layer and in the perforation of the source electrode of the interlayer dielectric layer and drain electrode perforation, wherein the electrical property material
Material pattern layer includes: a Source contact layer and a drain contact layer.The Source contact layer is electrically connected by source electrode perforation
Connect the source area.The drain contact layer is electrically connected the drain region by drain electrode perforation.
In an embodiment of the utility model, the electric material pattern layer further includes a contact electrode layer, Yi Jisuo
Stating display panel includes a passivation pattern layer, and the passivation pattern layer is located at the Source contact layer and the drain contact layer
On, wherein the passivation pattern layer exposure contact electrode layer.
In an embodiment of the utility model, the display panel also includes a second electrode pattern layer, is located at described
On passivation pattern layer and the contact electrode layer.
In an embodiment of the utility model, the second electrode pattern layer is a common electrode.
In an embodiment of the utility model, the polysilicon layer is arranged by one first gray level mask technique, with
And the first electrode pattern layer and the interlayer dielectric layer are arranged by one second gray level mask technique.
In an embodiment of the utility model, the substrate is a underlay substrate.
In an embodiment of the utility model, the substrate includes that a flexible base board, a transparent substrates or one are flexible
Transparent substrates.
In an embodiment of the utility model, the interlayer dielectric layer includes silicon nitride layer and silicon oxide layer.
In an embodiment of the utility model, the first electrode pattern layer is a pixel electrode.
The display panel of the utility model embodiment compared with prior art, by using grid as light shield layer, omission
Flatness layer and lower electrode (bottom ITO；BITO) layer is as pixel electrode, to reduce used in manufacture display panel
Photomask number, and then reduce manufacturing cost.
For the above content of the utility model can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's attached drawing
Formula is described in detail below:
Detailed description of the invention
Fig. 1 is the flow diagram of the manufacturing method of the display panel of an embodiment of the present invention.
Fig. 2A to 2K is the section signal of each step of the manufacturing method of the display panel of an embodiment of the present invention
Figure.
Fig. 3 A to 3G is the first gray level mask technique of the manufacturing method of the display panel of an embodiment of the present invention
The diagrammatic cross-section of each step.
Fig. 4 A to 4D is the second gray level mask technique of the manufacturing method of the display panel of an embodiment of the present invention
The diagrammatic cross-section of each step.
Specific embodiment
The explanation of following embodiment is to can be used to the specific of implementation to illustrate the utility model with reference to additional schema
Embodiment.Furthermore the direction term that the utility model is previously mentioned, for example, above and below, top, bottom, front, rear, left and right, inside and outside, side
Face, surrounding, center, level, transverse direction, vertically, longitudinally, axial direction, radial direction, top layer or lowest level etc., be only with reference to annexed drawings
Direction.Therefore, the direction term used is to illustrate and understand the utility model, rather than to limit the utility model.
First it is noted that the production method of display panel in the prior art, such as need sequentially through nine light
Mask step makes following each component, includes: light shield layer (light shielding layer；LS layer), production polycrystalline
Silicon layer (poly crystal silicon layer；Poly layer), production grid layer (GE layer) and carrier mix (N+&N-), production interlayer dielectric layer (ILD layer), production source drain contact layer (SD layer), production flatness layer (PLN
Layer), lower electrode layer (bottom ITO is made；BITO) as common electrode, production passivation layer (PV layer) and production
Upper electrode layer (top ITO；TITO) it is used as pixel electrode.Compared to the production method of above-mentioned display panel, the utility model
The production method of the display panel of embodiment can reduce used photomask number, therefore can reduce manufacturing cost.
It please refers to shown in Fig. 1 and Fig. 2A to 2K, the manufacturing method 10 of the display panel of an embodiment of the present invention is main
Include step 11 to 18: a substrate (step 11) is provided；Form a grid (step 12) on the substrate；It is exhausted to form a grid
Edge layer (step 13) on the grid and the substrate；Form a polysilicon layer (step 14) on the gate insulating layer；
To the polysilicon layer carry out one first gray level mask technique, with formed source region, the drain region of the polysilicon layer with
An and active area (step 15) of the position between the source area and the drain region；An interlayer dielectric layer is formed in the grid
(step 16) on insulating layer and the polysilicon layer；Form a first electrode layer (step 17) on the interlayer dielectric layer；With
And one second gray level mask technique is carried out to the first electrode layer and the interlayer dielectric layer, wherein including: described in patterning
First electrode layer is to form a first electrode pattern layer；And source electrode perforation is formed in the interlayer dielectric layer and is worn with a drain electrode
Hole, the exposure source area and the drain electrode perforation exposure drain region (step 18) wherein the source electrode is perforated.This is practical
It is novel will in hereafter one by one be described in detail the above-mentioned each component of embodiment detail structure, assembled relation and its operation principles.
Please with reference to Fig. 1 and Fig. 2A, the manufacturing method 10 of the display panel of an embodiment of the present invention is step first
Rapid 11: a substrate 21 is provided.In this step 11, the substrate 11 be, for example, a underlay substrate, can be used for carrying the grid,
The gate insulating layer, the polysilicon layer, the interlayer dielectric layer and the first electrode pattern layer.In one embodiment,
The substrate 11 is, for example, a flexible base board, a transparent substrates or a soft light substrate.
Please with reference to Fig. 1 and Fig. 2 B, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 12: forming a grid 22 on the substrate 21.In this step 12, the grid 22 is, for example, to pass through lithography step
To be formed on the substrate.In other words, it is needed in this step 12 using one of photomask technique.It is to be noted that the grid
Pole 22 can also be used as light shield layer, for blocking the active area for the polysilicon layer being subsequently formed.In one embodiment, step 12
Be by way of making bottom-gate so that the grid layer 22 is alternatively arranged as light shield layer other than the function as grid,
And then reduce the number for using photomask.
Please with reference to Fig. 1 and Fig. 2 C, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 13: forming a gate insulating layer 23 on the grid 22 and the substrate 21.In this step 13, such as can be by partly leading
The gate insulating layer 23 is deposited on the grid 22 and the substrate 21 by common materials or production method in body technology
On.
Please with reference to Fig. 1 and Fig. 2 D, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 14: forming a polysilicon layer 24 on the gate insulating layer 23.In this step 14, the formation side of the polysilicon layer 24
Formula is, for example, that an amorphous silicon layer (not being painted) is first formed on the gate insulating layer 23, is carried out later to the amorphous silicon layer
One laser annealing step, so that the amorphous silicon layer forms the polysilicon layer 24.
Please with reference to Fig. 1 and Fig. 2 E, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 15: one first gray level mask technique being carried out to the polysilicon layer 24, to form the source region of the polysilicon layer 24
241, the active area 243 of a drain region 242 and position between the source area 241 and the drain region 242.In this step
In 15, the first gray level mask technique is for example, selected from by a halftoning photomask technique and a gray tone photomask technique institute
One group of composition.In one embodiment, the first gray level mask technique is, for example, for carrying out to the polysilicon layer 24
One lithography step, and then the photoresist layer of different-thickness is formed on the polysilicon layer 24.It therefore, can be by using difference
Etching parameter to expose the source area 241 and the drain region 242, and then to the source area 241 and the drain electrode
Area 242 carries out carrier doping.
For example, A to 3G referring to figure 3..Fig. 3 A is by the first gray level mask technique, so that the polysilicon
Layer 24 forms schematic diagram of the photoresist layer 30 of different-thickness on the polysilicon layer 24 when carrying out a lithography technique.
From Fig. 3 A it is found that the part that the polysilicon layer 24 exposes can be by etching step 301, to pattern the polysilicon layer
24.Fig. 3 B is the schematic diagram for stripping photoresist step 302 for the first time, by different etching parameters, by scheduled source area 241
It exposes and goes out with drain region 242, in order to carry out 303 (as shown in Figure 3 C) of heavily loaded son doping.Fig. 3 D is to strip photoresist for the second time
The schematic diagram of step 304, by different etching parameters, can expose again the polysilicon layer 24 other parts 24A and
24B, in order to carry out being lightly loaded sub- doping 305 (as shown in FIGURE 3 E) and then improve the effect of thin film transistor (TFT).Fig. 3 F is third time
The schematic diagram for stripping photoresist step 306 can be removed all photoresists by different etching parameters, and be exposed described more
Crystal silicon layer remainder 24C (i.e. active region 243, as electronics electricity hole transmitting channel), in order to remainder 24C into
Row carrier adulterated for 307 (as shown in Figure 3 G).
Please with reference to Fig. 1 and Fig. 2 F, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 16: forming an interlayer dielectric layer 25 on the gate insulating layer 23 and the polysilicon layer 24.In this step 16, such as
The interlayer dielectric layer 25 can be deposited on the gate insulating layer 23 by common materials in semiconductor technology or production method
And on the polysilicon layer 24.In one embodiment, the interlayer dielectric layer 25 is for example comprising silicon nitride layer 251 and silicon oxide layer
252 multilayer material.
Please with reference to Fig. 1 and Fig. 2 G, the manufacturing method 10 of the display panel of an embodiment of the present invention is followed by step
Rapid 17: forming a first electrode layer 26 on the interlayer dielectric layer 25.In this step 17, the material of the first electrode layer 26
Matter is, for example, tin indium oxide (ITO), and the first electrode layer 26 can be used as a lower electrode layer (bottom ITO；BITO).
Please with reference to Fig. 1 and Fig. 2 H, the manufacturing method 10 of the display panel of an embodiment of the present invention is finally step
Rapid 18: one second gray level mask technique being carried out to the first electrode layer 26 and the interlayer dielectric layer 25, wherein including: pattern
Change the first electrode layer 26 to form a first electrode pattern layer 261；And a source electrode is formed in the interlayer dielectric layer 25
Perforate the drain electrode perforation 25B of 25A and one, the 25B wherein source electrode perforation 25A exposure source area 241 and the drain electrode are perforated
Exposure 242 (the step 18) of drain region.In this step 18, the second gray level mask technique is for example, selected from by half color
Dim a group composed by masking process and a gray tone photomask technique.In one embodiment, second gray level mask
Technique is, for example, for carrying out a lithography step, and then formation to the first electrode layer 26 and the interlayer dielectric layer 25
The photoresist layer of different-thickness is in the first electrode layer 26 and the interlayer dielectric layer 25.
For example, A to 4D referring to figure 4..Fig. 4 A is by the second gray level mask technique, so that first electricity
Pole layer and the interlayer dielectric layer form the photoresist layer 40 of different-thickness in first electricity when carrying out a lithography technique
Schematic diagram on pole layer 26 and the interlayer dielectric layer 25.From Fig. 4 A it is found that the part that the first electrode layer 26 exposes can
By etching step 401, to form the source electrode perforation 25A and drain electrode perforation 25B.Fig. 4 B is to strip photoresist layer for the first time
The schematic diagram of 40 step 402 patterns the first electrode layer 26 by the step 403 of different etching parameters, to be formed
One first electrode pattern layer 261 (as shown in Figure 4 C), wherein the first electrode pattern layer 261 can be used as a pixel electrode.Figure
4D is the schematic diagram for stripping the step 404 of photoresist layer 40 for the second time, can be complete by the photoresist layer 40 by different etching parameters
Portion's removal.
From the foregoing, it will be observed that institute can be formed using photomask technique (the second gray level mask technique)
It states first electrode pattern layer 261 and forms the source electrode perforation 25A and drain electrode perforation in the interlayer dielectric layer 25
25B, therefore the number of photomask capable of reducing using.
In one embodiment, I, the utility model embodiment also may include step referring to figure 2.: form an electric material figure
Pattern layer 27 is in the first electrode pattern layer 261 and the source electrode of the interlayer dielectric layer 25 is perforated to drain described in 25A and be worn
In the 25B of hole, wherein the electric material pattern layer 27 includes a Source contact layer 271 and a drain contact layer 272 and described
Source contact layer 271 is electrically connected the source area 241 by source electrode perforation 25A, and the drain contact layer 272 passes through institute
It states drain electrode perforation 25B and is electrically connected the drain region 242.In an example, the electric material pattern layer 27 is, for example, to pass through
Lithography step be formed in the first electrode pattern layer 261 and the source electrode of the interlayer dielectric layer 25 perforation
In 25A and drain electrode perforation 25B.In other words, the formation of the electric material pattern layer 27 need to use one of photomask technique.
In one embodiment, J, the electric material pattern layer 27 further include a contact electrode layer 273 referring to figure 2., with
And the manufacturing method 10 of the display panel of the utility model embodiment also includes step: forming a passivation pattern layer 28 in the source
On pole contact layer 271 and the drain contact layer 272, wherein the passivation pattern layer 28 exposure contact electrode layer 273.?
In one example, the passivation pattern layer 28 is, for example, by lithography step to be formed in the Source contact layer 271 and institute
It states on drain contact layer 272.In other words, the formation of the passivation pattern layer 28 need to use one of photomask technique.
In one embodiment, K, the manufacturing method 10 of the display panel of the utility model embodiment can also wrap referring to figure 2.
Containing step: forming a second electrode pattern layer 29 on the passivation pattern layer 28 and the contact electrode layer 273.Described second
The material of electrode pattern layer 29 is, for example, tin indium oxide (ITO), and the second electrode pattern layer 29 can be used as a top electrode
Layer (Top ITO；TITO).In an example, the second electrode pattern layer 29 is, for example, by lithography step to be formed
On the passivation pattern layer 28 and the contact electrode layer 273, wherein to can be used as one public for the second electrode pattern layer 29
Electrode.In other words, the formation of the second electrode pattern layer 29 need to use one of photomask technique.
In one embodiment, the system of flatness layer is not included in the manufacturing method 10 of the display panel of the utility model embodiment
Make, therefore the number of photomask capable of reducing using.
From the foregoing, it will be observed that the manufacturing method 10 of the display panel of the utility model embodiment can be by using two gray level masks
Technique manufactures used photomask number when display panel to reduce.In addition, the display panel of the utility model embodiment
Manufacturing method can also be by way of making bottom-gate, so that the grid layer is alternatively arranged as other than the function as grid
Light shield layer, and then reduce the number for using photomask.In addition, the manufacturing method of the display panel of the utility model embodiment may be used also
By not making flatness layer, therefore the number of photomask capable of reducing using.Therefore, if display panel in compared to the prior art
Production method (nine photomask steps), the display panel of the utility model embodiment can pass through six photomask steps
It is fabricated into upper electrode layer.
K referring to figure 2., the utility model embodiment more propose a kind of display panel 20, include: a substrate 21, a grid
22, a gate insulating layer 23, a polysilicon layer 24, an interlayer dielectric layer 25 and a first electrode pattern layer 261.The grid 22
It is located on the substrate 21.The gate insulating layer 23 is located on the grid 22 and the substrate 21.The polysilicon layer 24
It is located on the gate insulating layer 23, wherein the polysilicon layer 24 includes source region 241, a drain region 242 and is located at institute
State the active area 243 between source area 241 and the drain region 242.The interlayer dielectric layer 25 is located at the gate insulator
On layer 23 and the polysilicon layer 24, the interlayer dielectric layer 25 has the source electrode drain electrode perforation 25B of perforation 25A and one, wherein
The source electrode perforation 25A exposure source area 241 and the drain electrode perforation 25B exposure drain region 242.First electricity
Pole figure pattern layer 26 is located on the interlayer dielectric layer 25.
In an embodiment of the utility model, the display panel further includes an electric material pattern layer 27, is located at institute
State in first electrode pattern layer 261 and the source electrode of the interlayer dielectric layer 25 perforation 25A and the drain electrode perforate 25B in,
Wherein the electric material pattern layer 27 includes: a Source contact layer 271 and a drain contact layer 272.The Source contact layer
271 are electrically connected the source area 241 by source electrode perforation 25A.The drain contact layer 272 is perforated by the drain electrode
25B is electrically connected the drain region 242.
In an embodiment of the utility model, the electric material pattern layer 27 further includes a contact electrode layer 273, with
And the display panel 20 includes a passivation pattern layer 28, the passivation pattern layer 28 is located at the Source contact layer 271
And on the drain contact layer 272, wherein the passivation pattern layer 28 exposure contact electrode layer 273.
In an embodiment of the utility model, the display panel also includes a second electrode pattern layer 29, is located at institute
It states on passivation pattern layer 28 and the contact electrode layer 273.
In an embodiment of the utility model, the polysilicon layer 24 is arranged by one first gray level mask technique,
And the first electrode pattern layer 261 with the interlayer dielectric layer 25 is arranged by one second gray level mask technique.
In an embodiment of the utility model, the display panel 20 can pass through the display of above-mentioned the utility model embodiment
The manufacturing method 10 of panel obtains, therefore relevant embodiment is not repeated to describe with example.
The utility model is described by above-mentioned related embodiment, however above-described embodiment is only to implement the utility model
Example.It must be noted that, it has been disclosed that embodiment be not limiting as the scope of the utility model.On the contrary, being contained in right
The modification of the spirit and scope of claim and impartial setting are included in the scope of the utility model.
Claims (10)
1. a kind of display panel, it is characterised in that: the display panel includes:
One substrate；
One grid, if on the substrate；
One gate insulating layer is located on the grid and the substrate；
One polysilicon layer, if on the gate insulating layer, wherein the polysilicon layer includes source region, a drain region and sets
An active area between the source area and the drain region；
One interlayer dielectric layer is located on the gate insulating layer and the polysilicon layer, and the interlayer dielectric layer has a source electrode
Perforation is perforated with a drain electrode, the exposure source area and the drain electrode perforation exposure drain region wherein the source electrode is perforated；
And
One first electrode pattern layer, is located on the interlayer dielectric layer.
2. display panel as described in claim 1, it is characterised in that: the display panel further includes an electric material pattern
Layer, be located in the first electrode pattern layer and the source electrode of the interlayer dielectric layer perforation with the drain electrode perforate in,
Described in electric material pattern layer include:
One Source contact layer is electrically connected the source area by source electrode perforation；And
One drain contact layer is electrically connected the drain region by drain electrode perforation.
3. display panel as claimed in claim 2, it is characterised in that: the electric material pattern layer further includes electrode contact
Layer and the display panel include a passivation pattern layer, and the passivation pattern layer is located at the Source contact layer and the leakage
On the contact layer of pole, wherein the passivation pattern layer exposure contact electrode layer.
4. display panel as claimed in claim 3, it is characterised in that: the display panel also includes a second electrode pattern
Layer, is located on the passivation pattern layer and the contact electrode layer.
5. display panel as claimed in claim 4, it is characterised in that: the second electrode pattern layer is a common electrode.
6. display panel as described in claim 1, it is characterised in that: the polysilicon layer is by one first gray level mask work
Skill setting and the first electrode pattern layer and the interlayer dielectric layer are arranged by one second gray level mask technique.
7. display panel as described in claim 1, it is characterised in that: the substrate is a underlay substrate.
8. display panel as described in claim 1, it is characterised in that: the substrate includes a flexible base board, a transparent substrates
An or soft light substrate.
9. display panel as described in claim 1, it is characterised in that: the interlayer dielectric layer includes silicon nitride layer and silica
Layer.
10. display panel as described in claim 1, it is characterised in that: the first electrode pattern layer is a pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821398328.3U CN208738249U (en) | 2018-08-28 | 2018-08-28 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821398328.3U CN208738249U (en) | 2018-08-28 | 2018-08-28 | Display panel |
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| Publication Number | Publication Date |
|---|---|
| CN208738249U true CN208738249U (en) | 2019-04-12 |
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ID=66032680
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| CN201821398328.3U Active CN208738249U (en) | 2018-08-28 | 2018-08-28 | Display panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020042258A1 (en) * | 2018-08-28 | 2020-03-05 | 武汉华星光电技术有限公司 | Display panel and manufacturing method therefor |
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2018
- 2018-08-28 CN CN201821398328.3U patent/CN208738249U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020042258A1 (en) * | 2018-08-28 | 2020-03-05 | 武汉华星光电技术有限公司 | Display panel and manufacturing method therefor |
| US11521993B2 (en) | 2018-08-28 | 2022-12-06 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel and method of manufacturing the same |
| CN108831895B (en) * | 2018-08-28 | 2023-10-13 | 武汉华星光电技术有限公司 | Display panel and manufacturing method thereof |
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