CN105161458A - Manufacturing method for TFT (thin film transistor) substrate - Google Patents
Manufacturing method for TFT (thin film transistor) substrate Download PDFInfo
- Publication number
- CN105161458A CN105161458A CN201510504952.1A CN201510504952A CN105161458A CN 105161458 A CN105161458 A CN 105161458A CN 201510504952 A CN201510504952 A CN 201510504952A CN 105161458 A CN105161458 A CN 105161458A
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- active layer
- type light
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000010409 thin film Substances 0.000 title abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 110
- 230000008569 process Effects 0.000 claims abstract description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 188
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- -1 boron ion Chemical class 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 238000010422 painting Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 15
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000008859 change Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method for a TFT (thin film transistor) substrate. Firstly, a P-type light-doping processing is performed on a polycrystalline silicon layer; then, the P-type light-doped polycrystalline silicon layer is subjected to patterned processing; in the P-type light-doping processing, the condition that P-type ions are difficult to be implanted into a silicon oxide layer below the polycrystalline silicon layer can be ensured, so that the damage on the silicon oxide layer is relatively low and the damage almost can be ignored; compared with the conventional production process, the manufacturing method provided by the invention dose not increase the technological process and the operation time, instead, the manufacturing method, by only adjusting the sequences of the pattered processing of the polycrystalline silicon layer and the P-type light-doping processing, enables the manufactured TFT substrate to be good in the comprehensive performance and excellent in the electrical property.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of TFT substrate.
Background technology
Along with the development of Display Technique, liquid crystal display (LiquidCrystalDisplay, etc. LCD) flat display apparatus is because having the advantages such as the thin and applied range of high image quality, power saving, fuselage, and be widely used in the various consumption electronic products such as mobile phone, TV, personal digital assistant, digital camera, notebook computer, desktop computer, become the main flow in display unit.
Liquid crystal indicator major part on existing market is backlight liquid crystal display, and it comprises display panels and backlight module (backlightmodule).The operation principle of display panels places liquid crystal molecule in the middle of the glass substrate that two panels is parallel, there is the tiny electric wire of many vertical and levels in the middle of two panels glass substrate, change direction by whether being energized to control liquid crystal molecule, the light refraction of backlight module is out produced picture.
Usual display panels is by color membrane substrates (CF, ColorFilter), thin film transistor base plate (TFT, ThinFilmTransistor), be sandwiched in the liquid crystal (LC between color membrane substrates and thin film transistor base plate, LiquidCrystal) and fluid sealant frame (Sealant) composition, its moulding process generally comprises: leading portion array (Array) processing procedure (film, gold-tinted, etching and stripping), stage casing becomes box (Cell) processing procedure (TFT substrate and CF baseplate-laminating) and back segment module group assembling processing procedure (drive IC and printed circuit board (PCB) pressing).Wherein, leading portion Array processing procedure mainly forms TFT substrate, so that control the motion of liquid crystal molecule; Stage casing Cell processing procedure mainly adds liquid crystal between TFT substrate and CF substrate; The integration of back segment module group assembling processing procedure mainly drive IC pressing and printed circuit board (PCB), and then drive liquid crystal molecule to rotate, display image.
As shown in figs. 1-7, be the manufacture method of existing a kind of TFT substrate, comprise the following steps:
Step 1, as shown in Figure 1, provide a substrate 100, described substrate 100 deposits a metal level, adopts one lithographic process to carry out patterned process to described metal level, obtain spaced first light shield layer 210, second light shield layer 220;
Step 2, as shown in Figure 2, deposited silicon nitride layer 300 and silicon oxide layer 400 successively on described first light shield layer 210, second light shield layer 220 and substrate 100;
Step 3, as shown in Figure 3, described silicon oxide layer 400 deposits an amorphous silicon layer, adopt quasi-molecule laser annealing processing procedure that described amorphous silicon layer is converted into polysilicon layer 500;
Step 4, as shown in Figure 4, adopt one lithographic process to carry out patterned process to described polysilicon layer 500, obtain the first active layer 510, second active layer 520 corresponding respectively to described first light shield layer 210, second light shield layer 220;
Step 5, as shown in Figure 5, P type ion implantation is carried out to described first active layer 510, second active layer 520, form P type light dope active layer the 610, a 2nd P type light dope active layer 620;
Step 6, as shown in Figure 6, at a described P type light dope active layer 610, 2nd P type light dope active layer 620, and silicon oxide layer 400 is coated with a photoresist layer 700, one gold-tinted processing procedure is adopted to expose described photoresist layer 700, development, expose two end regions of a described P type light dope active layer 610, with described photoresist layer 700 for mask, ion implantation is carried out to the two ends of a described P type light dope active layer 610, as shown in Figure 7, after removing described photoresist layer 700, obtain the N-type heavily doped region 612 being positioned at described P type light dope active layer 610 two ends, and the P type light dope channel region 614 between two N-type heavily doped regions 612.
The manufacture method of above-mentioned TFT substrate, first patterned process is carried out to polysilicon layer 500, obtain the first active layer 510 of island, after second active layer 520, again to the first active layer 510, and second active layer 520 carry out P type ion implantation, its shortcoming is: the first active layer 510 etching island, after second active layer 520, the exposed of silicon oxide layer 400 can be caused, can by P type ion implantation in exposed silicon oxide layer 400 out in the process of carrying out P type ion implantation, its lattice structure is damaged, charge carrier will be introduced in P type implanted ions to silicon oxide layer 400 simultaneously, may affect to the electrology characteristic of components and parts.
Therefore the manufacture method of the TFT substrate that a kind of improvement is provided is necessary, to solve the problem run in conventional process.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of TFT substrate, can ensure in P type light dope processing procedure, P type ion is not easy to be injected in the silicon oxide layer below polysilicon layer, less to the damage of described silicon oxide layer, make the TFT substrate obtained have good combination property and excellent electrical performance.
For achieving the above object, the invention provides a kind of manufacture method of TFT substrate, comprise the following steps:
Step 1, provide a substrate, deposit a metal level on the substrate, adopt one lithographic process to carry out patterned process to described metal level, obtain spaced first light shield layer, the second light shield layer;
Step 2, on described first light shield layer, the second light shield layer and substrate deposited silicon nitride layer and silicon oxide layer successively;
Step 3, on described silicon oxide layer, deposit an amorphous silicon layer, adopt low temperature crystallization technique that described amorphous silicon layer is converted into polysilicon layer;
Step 4, P type ion implantation is carried out to described polysilicon layer, form P type light dope polysilicon layer;
Step 5, adopt one lithographic process to carry out patterned process to described P type light dope polysilicon layer, obtain corresponding respectively to described first light shield layer, the first active layer of the second light shield layer, the second active layer;
Step 6, on described first active layer, the second active layer and silicon oxide layer, be coated with a photoresist layer, one gold-tinted processing procedure is adopted to expose described photoresist layer, develop, expose two end regions of described first active layer, with described photoresist layer for mask, N-type ion implantation is carried out to the two ends of described first active layer, after removing described photoresist layer, obtain in the N-type heavily doped region at described first active layer two ends and the P type light doping section between two N-type heavily doped regions;
Step 7, on described first active layer, the second active layer and silicon oxide layer deposition of gate insulating barrier, described gate insulator deposits a metal level, adopt one lithographic process to carry out patterned process to described metal level, obtain corresponding respectively to the first active layer, the first grid of the second active layer, second grid;
Step 8, with described first grid for mask, N-type ion implantation is carried out to the two ends of the P type light doping section of described first active layer, described P type light doping section is formed in the N-type light doping section at two ends and the P type light dope channel region between two N-type light doping sections;
Step 9, on described first grid, second grid and gate insulator, be coated with a photoresist layer, one gold-tinted processing procedure is adopted to expose described photoresist layer, develop, expose on second grid and gate insulator corresponding to the region above described second active layer, with described second grid for mask, P type ion implantation is carried out to the two ends of described second active layer, after removing described photoresist layer, obtain in the P type heavily doped region at described second active layer two ends and the P type light dope channel region between two P type heavily doped regions;
Step 10, on described first grid, second grid and gate insulator, form interlayer insulating film, source-drain electrode successively.
In described step 1, described substrate is glass substrate; The material of described first light shield layer, the second light shield layer is molybdenum.
In described step 3, described low temperature crystallization technique is excimer laser annealing process.
Lithographic process in described step 5 comprises painting photoresistance, exposure, development and dry ecthing procedure.
In described step 7, the material of described gate insulator is the combination of silicon nitride and silica.
The P type ion that described step 4 and step 9 are injected is boron ion.
The N-type ion that described step 6 and step 8 are injected is phosphonium ion.
In described first active layer, the N-type ion concentration range in described N-type heavily doped region is 10
14~ 2 × 10
15ions/cm
2, the N-type ion concentration range in described N-type light doping section is 10
13~ 3 × 10
13ions/cm
2, the P type ion concentration range in described P type light dope channel region is 10
12~ 5 × 10
12ions/cm
2.
In described second active layer, the P type ion concentration range in described P type heavily doped region is 10
14~ 2 × 10
15ions/cm
2, the P type ion concentration range in described P type light dope channel region is 10
12~ 5 × 10
12ions/cm
2.
Beneficial effect of the present invention: the manufacture method that the invention provides a kind of TFT substrate, by first carrying out P type light dope to polysilicon layer, and then patterned process is carried out to P type light dope polysilicon layer, can ensure in P type light dope processing procedure, P type ion is not easy to be injected in the silicon oxide layer below polysilicon layer, less to the damage of described silicon oxide layer, be close to negligible, compared with traditional procedure for producing, manufacture method of the present invention does not increase manufacturing process and operating time, only by the adjustment patterned process of polysilicon layer and the order of P type light dope processing procedure, the TFT substrate obtained can be made to have good combination property and excellent electrical performance.
Accompanying drawing explanation
In order to further understand feature of the present invention and technology contents, refer to following detailed description for the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used for being limited the present invention.
In accompanying drawing,
Fig. 1 is the schematic diagram of the manufacture method step 1 of existing a kind of TFT substrate;
Fig. 2 is the schematic diagram of the manufacture method step 2 of existing a kind of TFT substrate;
Fig. 3 is the schematic diagram of the manufacture method step 3 of existing a kind of TFT substrate;
Fig. 4 is the schematic diagram of the manufacture method step 4 of existing a kind of TFT substrate;
Fig. 5 is the schematic diagram of the manufacture method step 5 of existing a kind of TFT substrate;
Fig. 6-7 is the schematic diagram of the manufacture method step 6 of existing a kind of TFT substrate;
Fig. 8 is the schematic diagram of the manufacture method step 1 of TFT substrate of the present invention;
Fig. 9 is the schematic diagram of the manufacture method step 2 of TFT substrate of the present invention;
Figure 10 is the schematic diagram of the manufacture method step 3 of TFT substrate of the present invention;
Figure 11 is the schematic diagram of the manufacture method step 4 of TFT substrate of the present invention;
Figure 12 is the schematic diagram of the manufacture method step 5 of TFT substrate of the present invention;
Figure 13-14 is the schematic diagram of the manufacture method step 6 of TFT substrate of the present invention;
Figure 15 is the schematic diagram of the manufacture method step 7 of TFT substrate of the present invention;
Figure 16 is the schematic diagram of the manufacture method step 8 of TFT substrate of the present invention;
Figure 17-18 is the schematic diagram of the manufacture method step 9 of TFT substrate of the present invention.
Embodiment
For further setting forth the technological means and effect thereof that the present invention takes, be described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
The invention provides a kind of manufacture method of TFT substrate, comprise the following steps:
Step 1, as shown in Figure 8, provide a substrate 10, described substrate 10 deposits a metal level, adopts one lithographic process to carry out patterned process to described metal level, obtain spaced first light shield layer 21, second light shield layer 22.
Concrete, described substrate 10 is glass substrate, and the material of described first light shield layer 21, second light shield layer 22 is molybdenum (Mo).
Step 2, as shown in Figure 9, deposited silicon nitride layer 30 and silicon oxide layer 40 successively on described first light shield layer 21, second light shield layer 22 and substrate 10.
Step 3, as shown in Figure 10, described silicon oxide layer 40 deposits an amorphous silicon layer, adopt low temperature crystallization technique that described amorphous silicon layer is converted into polysilicon layer 50.
Concrete, described low temperature crystallization technique is excimer laser annealing process.
Step 4, as shown in figure 11, P type ion implantation is carried out to described polysilicon layer 50, form P type light dope polysilicon layer 60.
Compared with prior art, the present invention have adjusted the P type light dope processing procedure of polysilicon layer 50 and the order of patterned process, before the P type light dope processing procedure of polysilicon layer 50 is placed in patterned process, thus ensure in P type light dope processing procedure, P type ion is not easy to be injected in the silicon oxide layer 40 below polysilicon layer 50, less to the damage of described silicon oxide layer 40, be close to negligible, the TFT substrate that the present invention is obtained has good combination property and excellent electrical performance.
Step 5, as shown in figure 12, adopt one lithographic process to carry out patterned process to described P type light dope polysilicon layer 60, obtain the first active layer 61, second active layer 62 corresponding respectively to described first light shield layer 21, second light shield layer 22.
Concrete, described lithographic process comprises painting photoresistance, exposure, development and dry ecthing procedure.
Step 6, as shown in figure 13, described first active layer 61, second active layer 62 and silicon oxide layer 40 are coated with a photoresist layer 70, one gold-tinted processing procedure is adopted to expose described photoresist layer 70, develop, expose two end regions of described first active layer 61, with described photoresist layer 70 for mask, N-type ion implantation is carried out to the two ends of described first active layer 61, as shown in figure 14, after removing described photoresist layer 70, obtain in the described N-type heavily doped region 611 at the first active layer 61 two ends and the P type light doping section 613 between two N-type heavily doped regions 611.
Step 7, as shown in figure 15, deposition of gate insulating barrier 80 on described first active layer 61, second active layer 62 and silicon oxide layer 40, described gate insulator 80 deposits a metal level, adopt one lithographic process to carry out patterned process to described metal level, obtain the first grid 91, the second grid 92 that correspond respectively to the first active layer 61, second active layer 62.
Concrete, the material of described gate insulator 80 is the combination of silicon nitride and silica.
Step 8, as shown in figure 16, with described first grid 91 for mask, N-type ion implantation is carried out to the two ends of the P type light doping section 613 of described first active layer 61, described P type light doping section 613 is formed in the N-type light doping section 615 at two ends and the P type light dope channel region 617 between two N-type light doping sections 615.
Concrete, the N-type ion that described step 6 and step 8 are injected is phosphonium ion.
Concrete, in described first active layer 61, the N-type ion concentration range in described N-type heavily doped region 611 is 10
14~ 2 × 10
15ions/cm
2, the N-type ion concentration range in described N-type light doping section 615 is 10
13~ 3 × 10
13ions/cm
2, the P type ion concentration range in described P type light dope channel region 617 is 10
12~ 5 × 10
12ions/cm
2.
Step 9, as shown in figure 17, at described first grid 91, second grid 92, and gate insulator 80 is coated with a photoresist layer 110, one gold-tinted processing procedure is adopted to expose described photoresist layer 110, development, expose on second grid 92 and gate insulator 80 corresponding to the region above described second active layer 62, with described second grid 92 for mask, P type ion implantation is carried out to the two ends of described second active layer 62, as shown in figure 18, after removing described photoresist layer 110, obtain the P type heavily doped region 621 being positioned at described second active layer 62 two ends, and the P type light dope channel region 623 between two P type heavily doped regions 621.
Concrete, the P type ion that described step 4 and step 9 are injected is boron ion.
Concrete, in described second active layer 62, the P type ion concentration range in described P type heavily doped region 621 is 10
14~ 2 × 10
15ions/cm
2, the P type ion concentration range in described P type light dope channel region 623 is 10
12~ 5 × 10
12ions/cm
2.
Step 10, on described first grid 91, second grid 92 and gate insulator 80, form interlayer insulating film, source-drain electrode successively, obtain TFT substrate of the present invention.
In sum, the invention provides a kind of manufacture method of TFT substrate, by first carrying out P type light dope to polysilicon layer, and then patterned process is carried out to P type light dope polysilicon layer, can ensure in P type light dope processing procedure, P type ion is not easy to be injected in the silicon oxide layer below polysilicon layer, less to the damage of described silicon oxide layer, be close to negligible, compared with traditional procedure for producing, manufacture method of the present invention does not increase manufacturing process and operating time, only by the adjustment patterned process of polysilicon layer and the order of P type light dope processing procedure, the TFT substrate obtained can be made to have good combination property and excellent electrical performance.
The above; for the person of ordinary skill of the art; can make other various corresponding change and distortion according to technical scheme of the present invention and technical conceive, and all these change and be out of shape the protection range that all should belong to the accompanying claim of the present invention.
Claims (9)
1. a manufacture method for TFT substrate, is characterized in that, comprises the following steps:
Step 1, provide a substrate (10), at upper deposition one metal level of described substrate (10), adopt one lithographic process to carry out patterned process to described metal level, obtain spaced first light shield layer (21), the second light shield layer (22);
Step 2, on described first light shield layer (21), the second light shield layer (22) and substrate (10) deposited silicon nitride layer (30) and silicon oxide layer (40) successively;
Step 3, at upper deposition one amorphous silicon layer of described silicon oxide layer (40), adopt low temperature crystallization technique that described amorphous silicon layer is converted into polysilicon layer (50);
Step 4, P type ion implantation is carried out to described polysilicon layer (50), form P type light dope polysilicon layer (60);
Step 5, adopt one lithographic process to carry out patterned process to described P type light dope polysilicon layer (60), obtain corresponding respectively to described first light shield layer (21), first active layer (61) of the second light shield layer (22), the second active layer (62);
Step 6, described first active layer (61), second active layer (62), and upper coating one photoresist layer (70) of silicon oxide layer (40), one gold-tinted processing procedure is adopted to expose described photoresist layer (70), development, expose two end regions of described first active layer (61), with described photoresist layer (70) for mask, N-type ion implantation is carried out to the two ends of described first active layer (61), after removing described photoresist layer (70), obtain the N-type heavily doped region (611) being positioned at described first active layer (61) two ends, and the P type light doping section (613) be positioned between two N-type heavily doped regions (611),
Step 7, at the upper deposition of gate insulating barrier (80) of described first active layer (61), the second active layer (62) and silicon oxide layer (40), at upper deposition one metal level of described gate insulator (80), adopt one lithographic process to carry out patterned process to described metal level, obtain corresponding respectively to the first active layer (61), the first grid (91) of the second active layer (62), second grid (92);
Step 8, with described first grid (91) for mask, N-type ion implantation is carried out to the two ends of the P type light doping section (613) of described first active layer (61), above forms the N-type light doping section (615) being positioned at two ends and the P type light dope channel region (617) be positioned between two N-type light doping sections (615) described P type light doping section (613);
Step 9, in described first grid (91), second grid (92), and upper coating one photoresist layer (110) of gate insulator (80), one gold-tinted processing procedure is adopted to expose described photoresist layer (110), development, expose second grid (92) and the upper region corresponding to described second active layer (62) top of gate insulator (80), with described second grid (92) for mask, P type ion implantation is carried out to the two ends of described second active layer (62), after removing described photoresist layer (110), obtain the P type heavily doped region (621) being positioned at described second active layer (62) two ends, and the P type light dope channel region (623) be positioned between two P type heavily doped regions (621),
Step 10, on described first grid (91), second grid (92) and gate insulator (80), form interlayer insulating film, source-drain electrode successively.
2. the manufacture method of TFT substrate as claimed in claim 1, it is characterized in that, in described step 1, described substrate (10) is glass substrate; The material of described first light shield layer (21), the second light shield layer (22) is molybdenum.
3. the manufacture method of TFT substrate as claimed in claim 1, it is characterized in that, in described step 3, described low temperature crystallization technique is excimer laser annealing process.
4. the manufacture method of TFT substrate as claimed in claim 1, is characterized in that, the lithographic process in described step 5 comprises painting photoresistance, exposure, development and dry ecthing procedure.
5. the manufacture method of TFT substrate as claimed in claim 1, it is characterized in that, in described step 7, the material of described gate insulator (80) is the combination of silicon nitride and silica.
6. the manufacture method of TFT substrate as claimed in claim 1, is characterized in that, the P type ion that described step 4 and step 9 are injected is boron ion.
7. the manufacture method of TFT substrate as claimed in claim 1, is characterized in that, the N-type ion that described step 6 and step 8 are injected is phosphonium ion.
8. the manufacture method of TFT substrate as claimed in claim 1, it is characterized in that, in described first active layer (61), the N-type ion concentration range in described N-type heavily doped region (611) is 10
14~ 2 × 10
15ions/cm
2, the N-type ion concentration range in described N-type light doping section (615) is 10
13~ 3 × 10
13ions/cm
2, the P type ion concentration range in described P type light dope channel region (617) is 10
12~ 5 × 10
12ions/cm
2.
9. the manufacture method of TFT substrate as claimed in claim 1, it is characterized in that, in described second active layer (62), the P type ion concentration range in described P type heavily doped region (621) is 10
14~ 2 × 10
15ions/cm
2, the P type ion concentration range in described P type light dope channel region (623) is 10
12~ 5 × 10
12ions/cm
2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510504952.1A CN105161458B (en) | 2015-08-17 | 2015-08-17 | The preparation method of TFT substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510504952.1A CN105161458B (en) | 2015-08-17 | 2015-08-17 | The preparation method of TFT substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105161458A true CN105161458A (en) | 2015-12-16 |
| CN105161458B CN105161458B (en) | 2018-01-30 |
Family
ID=54802273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510504952.1A Active CN105161458B (en) | 2015-08-17 | 2015-08-17 | The preparation method of TFT substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105161458B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
| CN107464746A (en) * | 2016-06-06 | 2017-12-12 | 格罗方德半导体公司 | Threshold voltage and well method for implantation for semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010038485A1 (en) * | 2000-04-19 | 2001-11-08 | Yukiya Hirabayashi | Electro-optical device, manufacturing method for manufacturing electro-optical device, and electronic equipment |
| KR100667080B1 (en) * | 2005-11-02 | 2007-01-11 | 삼성에스디아이 주식회사 | Fabricating method of cmos thin film transistor |
| CN101789434A (en) * | 2009-01-22 | 2010-07-28 | 统宝光电股份有限公司 | Image display system and manufacturing method thereof |
| CN104465509A (en) * | 2013-09-18 | 2015-03-25 | 昆山国显光电有限公司 | OLED display device array substrate and preparation method thereof |
-
2015
- 2015-08-17 CN CN201510504952.1A patent/CN105161458B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010038485A1 (en) * | 2000-04-19 | 2001-11-08 | Yukiya Hirabayashi | Electro-optical device, manufacturing method for manufacturing electro-optical device, and electronic equipment |
| KR100667080B1 (en) * | 2005-11-02 | 2007-01-11 | 삼성에스디아이 주식회사 | Fabricating method of cmos thin film transistor |
| CN101789434A (en) * | 2009-01-22 | 2010-07-28 | 统宝光电股份有限公司 | Image display system and manufacturing method thereof |
| CN104465509A (en) * | 2013-09-18 | 2015-03-25 | 昆山国显光电有限公司 | OLED display device array substrate and preparation method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470197A (en) * | 2016-01-28 | 2016-04-06 | 武汉华星光电技术有限公司 | Production method of low temperature poly silicon array substrate |
| WO2017128565A1 (en) * | 2016-01-28 | 2017-08-03 | 武汉华星光电技术有限公司 | Manufacturing method for low-temperature polysilicon array substrate |
| CN105470197B (en) * | 2016-01-28 | 2018-03-06 | 武汉华星光电技术有限公司 | The preparation method of low temperature polycrystalline silicon array base palte |
| GB2560685A (en) * | 2016-01-28 | 2018-09-19 | Wuhan China Star Optoelectronics Technology Co Ltd | Manufacturing method for low-temperature polysilicon array substrate |
| GB2560685B (en) * | 2016-01-28 | 2021-03-17 | Wuhan China Star Optoelectronics Technology Co Ltd | Manufacture method of low temperature poly-silicon array substrate |
| CN107464746A (en) * | 2016-06-06 | 2017-12-12 | 格罗方德半导体公司 | Threshold voltage and well method for implantation for semiconductor device |
| CN107464746B (en) * | 2016-06-06 | 2020-10-13 | 格罗方德半导体公司 | Threshold voltage and well implant method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105161458B (en) | 2018-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105552027B (en) | The production method and array substrate of array substrate | |
| CN105470197A (en) | Production method of low temperature poly silicon array substrate | |
| CN105489552B (en) | The production method of LTPS array substrates | |
| CN105097675A (en) | Array substrate and preparation method thereof | |
| CN105390451A (en) | Manufacture method of low-temperature polysilicon TFT substrate | |
| CN105702623B (en) | The production method of tft array substrate | |
| CN104766859A (en) | Manufacturing method and structure of TFT substrate | |
| CN105655359A (en) | Method for manufacturing TFT (thin-film transistor) substrates | |
| CN104900712A (en) | TFT substrate structure manufacturing method and TFT substrate structure thereof | |
| CN108447822A (en) | The production method of LTPS TFT substrates | |
| CN110148600A (en) | Array substrate and preparation method | |
| CN105470195A (en) | Fabrication method of thin film transistor (TFT) substrate | |
| CN105679705B (en) | The production method of array substrate | |
| CN105789120A (en) | Manufacturing method of TFT (Thin Film Transistor) substrate and TFT substrate | |
| US20210408063A1 (en) | Array substrate and method of manufacturing same | |
| CN105679772B (en) | The production method and low temperature polycrystalline silicon TFT substrate of low temperature polycrystalline silicon TFT substrate | |
| CN108598086B (en) | Manufacturing method of TFT array substrate and TFT array substrate | |
| CN104934439A (en) | Manufacture method and structure of TFT substrate | |
| CN1259731C (en) | Method for producing low-temperature polysilicon thin film transistor | |
| CN105161458A (en) | Manufacturing method for TFT (thin film transistor) substrate | |
| CN104716092A (en) | Manufacturing method of array substrate and manufacturing device | |
| CN105514123B (en) | The preparation method of LTPS array base paltes | |
| CN105355593A (en) | TFT substrate manufacturing method and TFT substrate | |
| CN107910378B (en) | LTPS thin film transistor, array substrate, manufacturing method of LTPS thin film transistor and array substrate, and display device | |
| CN208738249U (en) | Display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |