CN105514123B - The preparation method of LTPS array base paltes - Google Patents
The preparation method of LTPS array base paltes Download PDFInfo
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- CN105514123B CN105514123B CN201610060805.4A CN201610060805A CN105514123B CN 105514123 B CN105514123 B CN 105514123B CN 201610060805 A CN201610060805 A CN 201610060805A CN 105514123 B CN105514123 B CN 105514123B
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- 238000000034 method Methods 0.000 claims abstract description 89
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- 238000012545 processing Methods 0.000 claims abstract description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 23
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- 150000004706 metal oxides Chemical class 0.000 claims abstract description 22
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- 238000004140 cleaning Methods 0.000 claims abstract description 9
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- 239000010410 layer Substances 0.000 claims description 182
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- 239000007789 gas Substances 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 21
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- 239000011229 interlayer Substances 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
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- 229910052801 chlorine Inorganic materials 0.000 claims description 6
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- 238000002425 crystallisation Methods 0.000 claims description 6
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical group FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
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- -1 boron ion Chemical class 0.000 description 3
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- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of preparation method of LTPS array base paltes, the relative position of cushion and light shield layer is exchanged, and the material of light shield layer is replaced by the good metal oxide of heat-insulating property from conventional metal molybdenum, crystallinity during so as to improve amorphous silicon layer, be advantageous to improve the electron mobility of TFT devices；Reduce by manufacturing process for cleaning lithographic process together with, so as to reduce the production cost of 1 light shield, and reduce the processing time of LTPS array base paltes, it is cost-saved, lift production capacity.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of preparation method of LTPS array base paltes.
Background technology
With the development of Display Technique, the plane such as liquid crystal display (Liquid Crystal Display, LCD) display dress
Put because having the advantages that high image quality, power saving, fuselage is thin and has a wide range of application, and be widely used in mobile phone, TV, individual number
The various consumption electronic products such as word assistant, digital camera, notebook computer, desktop computer, turn into the master in display device
Stream.
It is backlight liquid crystal display that liquid crystal display device on existing market is most of, it include liquid crystal display panel and
Backlight module (backlight module).The operation principle of liquid crystal display panel is put among the parallel glass substrate of two panels
Liquid crystal molecule is put, there are many tiny electric wires vertically and horizontally among two panels glass substrate, liquid crystal is controlled by whether being powered
Molecular changes direction, the light of backlight module is reflected into generation picture.
Usual liquid crystal display panel is by color film (CF, Color Filter) substrate, thin film transistor (TFT) (TFT, Thin Film
Transistor) substrate, the liquid crystal (LC, Liquid Crystal) that is sandwiched between color membrane substrates and thin film transistor base plate and close
Sealing frame (Sealant) forms, and its moulding process generally comprises：Leading portion array (Array) processing procedure (film, gold-tinted, etching and stripping
Film), stage casing is into box (Cell) processing procedure (TFT substrate is bonded with CF substrates) and back segment module group assembling processing procedure (driving IC and printing electricity
Road plate pressing).Wherein, leading portion Array processing procedures mainly form TFT substrate, in order to control the motion of liquid crystal molecule；Stage casing
Cell processing procedures mainly add liquid crystal between TFT substrate and CF substrates；Back segment module group assembling processing procedure mainly drives IC pressings
With the integration of printed circuit board (PCB), and then drive liquid crystal molecule rotate, display image.
Low temperature polycrystalline silicon (Low Temperature Poly Silicon, LTPS) is widely used in medium and small electronic product
A kind of lcd technology.The electron mobility of traditional amorphous silicon material about 0.5-1.0cm2/ V.S, and low temperature polycrystalline silicon
Electron mobility up to 30-300cm2/V.S.Therefore, low-temperature polysilicon liquid crystal on silicon displays has high-res, reaction speed
Hurry up, high aperture many advantages, such as.
In the manufacture of current LTPS array base paltes, especially traditional CMOS (CMOS complementary metal-oxide-semiconductor)
Need, by 12-14 exposure manufacture process, also just to need 12-14 roads light shield accordingly in the processing procedure of array base palte.But in panel
In the board cost of factory, due to the cost highest of exposure machine, it is meant that panel factory can not possibly engross exposure in order to cost-effective
Light device, therefore the production capacity of exposure machine also just governs the product quantity of major panel manufacturing plant.Therefore, it is possible to save exposure time
Number, that is, light shield usage quantity is reduced, be the prefered method of the cost-effective lifting production capacity of each panel factory.
As shown in figure 1, the structural representation of the part film layer for traditional LTPS array base paltes, the LTPS array base paltes
Light shield layer 200 including glass substrate 100, on glass substrate 100, located at the light shield layer 200 and glass substrate 100
On cushion 300, the active layer 400 on the cushion 300, on the active layer 400 and cushion 300
Gate insulator 500 and the grid 600 on the gate insulator 500.From light shield layer in the LTPS array base paltes
The Making programme of 200 to the film layer structure of grid 600 is as follows：
Step 1, glass substrate 100 is cleaned first, using physical gas-phase deposite method (PVD) in the glass base
A metal level is formed on plate 100, processing is patterned to the metal level using one of lithographic process, obtains light shield layer 200,
The material of the light shield layer 200 is generally metal molybdenum (Mo)；
Step 2, cushion 300 is formed on the light shield layer 200 and glass substrate 100；
Step 3, an amorphous silicon layer formed on the cushion 300 using chemical gaseous phase depositing process (CVD), using standard
The amorphous silicon layer is converted into polysilicon layer by molecular laser method for annealing, and the polysilicon layer is entered using one of lithographic process
Row graphical treatment, active layer 400 is obtained, channel doping is carried out to the active layer 400 and NMOS is adulterated；
Step 4, grid formed on the active layer 400 and cushion 300 using chemical gaseous phase depositing process (CVD)
Insulating barrier 500；
Step 5, a metal level formed on the gate insulator 500 using physical gas-phase deposite method (PVD), used
One of lithographic process is patterned processing to the metal level, obtains grid 600；
Above-mentioned steps 1 to step 5 (from light shield layer 200 to the processing procedure of grid 600) uses 3 lithographic process altogether, therefore needs
Want 3 light shields, cost of manufacture is higher.In addition to step 1 is cleaned to glass substrate 100, the step 2, step 3,
Step 4, the processing procedure of step 5 are both needed to clean the substrate that a upper link is completed before, altogether 5 cleaning processes, cleaning time
Number is more, so as to increase processing time, reduces production capacity, therefore, it is necessary to a kind of preparation method of LTPS array base paltes is provided,
To solve the technical problem.
The content of the invention
It is cost-saved it is an object of the invention to provide a kind of preparation method of LTPS array base paltes, reduce light shield number
Amount and processing time, production capacity is improved, and lift the electric property of TFT devices.
To achieve the above object, the present invention provides a kind of preparation method of LTPS array base paltes, comprises the following steps：
Step 1, a substrate is provided, sequentially form cushion, metal oxide layer and amorphous silicon layer on the substrate；
Step 2, the amorphous silicon layer is converted into by polysilicon layer using low temperature crystallization technique；
Step 3, processing is patterned to the polysilicon layer using one of lithographic process, obtains active layer, and to institute
State active layer and carry out channel doping and NMOS doping；
Step 4, form insulating barrier on the active layer and metal oxide layer；
Step 5, form the first metal layer on the insulating barrier；
Step 6, a photoresist layer is coated with the first metal layer, after exposing, develop to it using a light shield, using 3
Road dry ecthing procedure is etched to the first metal layer, insulating barrier and metal oxide layer successively, obtains consistency from top to bottom
The light shield layer that grid aligns with gate insulator and with the active layer, and the width of the grid and gate insulator is small
In the active layer and the width of light shield layer, remaining photoresist layer is peeled off afterwards.
In the step 6, the first metal layer is etched using first of dry ecthing procedure, grid is obtained, adopts
Etching gas is the mixed gas or the mixed gas of sulfur hexafluoride and oxygen of chlorine and oxygen；
The insulating barrier is etched using second dry ecthing procedure, obtains gate insulator, the etching gas of use
Body is carbon tetrafluoride and the mixed gas or sulfur hexafluoride of oxygen and the mixed gas of oxygen；
The metal oxide layer is etched using the 3rd dry ecthing procedure, obtains light shield layer, the etching of use
Gas is the mixed gas or boron chloride gas of chlorine and sulfur hexafluoride.
In the step 1, the cushion is formed by chemical gaseous phase depositing process；Pass through physical gas-phase deposite method shape
Into the metal oxide layer；The amorphous silicon layer is formed by chemical gaseous phase depositing process；In the step 4, pass through chemistry
CVD method forms the insulating barrier；In the step 5, first metal is formed by physical gas-phase deposite method
Layer.
The material of the metal oxide layer is aluminum oxide.
In the step 2, the low temperature crystallization technique is quasi-molecule laser annealing method.
In the step 1, before cushion is formed, using deionized water or the deionized water for adding cleaning agent to base
Plate is cleaned；
In the step 2, before low temperature crystallized to amorphous silicon layer progress, the step 1 is obtained using hydrofluoric acid
To substrate cleaned；
In the step 4, before the insulating barrier is formed, the substrate obtained using hydrofluoric acid to the step 3 is carried out
Cleaning；
In the step 5, before the first metal layer is formed, using deionized water or the deionized water of addition cleaning agent
The substrate obtained to the step 4 cleans.
In the step 3, the processing procedure of the channel doping is：P-type is carried out to whole active layer to be lightly doped, or only to institute
The intermediate region progress p-type for stating active layer is lightly doped；The processing procedure of NMOS doping is：N is carried out to the both ends of the active layer
Type heavy doping, while the raceway groove both sides progress N-type of the active layer is lightly doped.
Also comprise the following steps：
Step 7, interlayer insulating film is formed on the grid, active layer and cushion, using one of lithographic process to institute
State interlayer insulating film and be patterned processing, obtain corresponding respectively to two vias above the both sides of the active layer；
Step 8, the depositing second metal layer on the interlayer insulating film, using one of lithographic process to second metal
Layer is patterned processing, obtains source electrode and drain electrode, the source electrode is with drain electrode respectively via the two of two vias and the active layer
Side is in contact.
In the step 7, the interlayer insulating film is formed by chemical gaseous phase depositing process；In the step 8, pass through thing
Physical vapor deposition method forms the second metal layer.
The cushion, insulating barrier and interlayer insulating film are for silicon oxide layer, silicon nitride layer or by silicon oxide layer and nitrogen
SiClx stacking plus the composite bed formed；The first metal layer and the material of second metal layer are one kind in molybdenum, titanium, aluminium, copper
Or a variety of heap stack combination.
Beneficial effects of the present invention：The preparation method of a kind of LTPS array base paltes provided by the invention, with prior art phase
Than the relative position of cushion and light shield layer being exchanged, and the material of light shield layer is replaced by into insulation from conventional metal molybdenum
Metal oxide of good performance, crystallinity during so as to improve amorphous silicon layer, be advantageous to improve the electronics of TFT devices
Mobility；Reduce by manufacturing process for cleaning lithographic process together with, so as to reduce the production cost of 1 light shield, and reduce LTPS
The processing time of array base palte, it is cost-effective, lift production capacity.
In order to be further understood that the feature of the present invention and technology contents, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, be not used for being any limitation as the present invention.
Brief description of the drawings
Below in conjunction with the accompanying drawings, by the way that the embodiment of the present invention is described in detail, technical scheme will be made
And other beneficial effects are apparent.
In accompanying drawing,
Fig. 1 is the structural representation of the part film layer of traditional LTPS array base paltes；
Fig. 2 is the schematic diagram of the step 1 of the preparation method of the LTPS array base paltes of the present invention；
Fig. 3 is the schematic diagram of the step 2 of the preparation method of the LTPS array base paltes of the present invention；
Fig. 4 is the schematic diagram of the step 3 of the preparation method of the LTPS array base paltes of the present invention；
Fig. 5 is the schematic diagram of the step 4 of the preparation method of the LTPS array base paltes of the present invention；
Fig. 6 is the schematic diagram of the step 5 of the preparation method of the LTPS array base paltes of the present invention；
Fig. 7-9 is the schematic diagram of the step 6 of the preparation method of the LTPS array base paltes of the present invention；
Figure 10 is the schematic diagram of the step 7 of the preparation method of the LTPS array base paltes of the present invention；
Figure 11-12 is the schematic diagram of the step 8 of the preparation method of the LTPS array base paltes of the present invention.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Fig. 2-12 are referred to, the present invention provides a kind of preparation method of LTPS array base paltes, comprised the following steps：
Step 1, as shown in Figure 2, there is provided a substrate 10, sequentially formed on the substrate 10 cushion 30, metal oxidation
Nitride layer 33 and non-crystalline silicon (a-Si) layer 34.
Specifically, in the step 1, the cushion 30 is formed by chemical gaseous phase depositing process (CVD)；Pass through physics
CVD method (PVD) forms the metal oxide layer 33；The amorphous is formed by chemical gaseous phase depositing process (CVD)
Silicon (a-Si) layer 34.
Specifically, the substrate 10 is glass substrate；The cushion 30 is silica (SiOx) layer, silicon nitride (SiNx)
Layer or the composite bed formed is superimposed with silicon nitride layer by silicon oxide layer.
Specifically, in the step 1, before cushion 30 is formed, using deionized water or going for cleaning agent is added
Ionized water cleans to substrate 10, and to remove surface contaminant, the cleaning agent can be surfactant.
The metal oxide layer 33 is used to form light shield layer in follow-up lithographic process.
In the selection of the material of the metal oxide layer 33, from the point of view of heat insulation effect, it is preferred to use insulation
Aluminum oxide (the Al of better performances2O3)。
Step 2, as shown in figure 3, the amorphous silicon layer 34 is converted into polysilicon (poly-Si) using low temperature crystallization technique
Layer 35.
Specifically, in the step 2, the low temperature crystallization technique is quasi-molecule laser annealing method (Excimer Laser
Annealing,ELA)。
When carrying out Crystallizing treatment to the amorphous silicon layer 34 using quasi-molecule laser annealing method, due to amorphous silicon layer 34
Lower section is provided with the metal oxide layer 33 with good thermal insulation property, therefore can improve crystallinity when a-Si is crystallized, favorably
In the electron mobility (Mobility) for improving TFT devices.
Specifically, being oxidized easily because non-crystalline silicon is exposed in air, oxide layer is generated, therefore in the step 2,
The amorphous silicon layer 34 is carried out it is low temperature crystallized before, it is also necessary to the substrate obtained using hydrofluoric acid (HF) to the step 1 is entered
Row cleaning, to remove the oxide layer on the surface of the non-crystalline silicon (a-Si) layer 34.
Step 3, as shown in figure 4, being patterned processing using polysilicon layer 35 described in one of lithographic process, obtain active
Layer 40, and channel doping and NMOS doping are carried out to the active layer 40.
Specifically, in the step 3, the processing procedure of the channel doping is：P-type is carried out to whole active layer 40 to be lightly doped,
Or only the intermediate region progress p-type of the active layer 40 is lightly doped；The processing procedure of NMOS doping is：To the active layer
40 both ends carry out N-type heavy doping, while the raceway groove both sides progress N-type of the active layer 40 is lightly doped.
Specifically, the ion that incorporation is lightly doped in the p-type is boron ion or gallium ion.
Specifically, the ion that incorporation is lightly doped in the N-type heavy doping and N-type is phosphonium ion or arsenic ion.
Step 4, as shown in figure 5, on the active layer 40 and metal oxide layer 33 formed insulating barrier 50.
Specifically, the step 4 forms the insulating barrier 50 by chemical gaseous phase depositing process (CVD).
Specifically, the insulating barrier 50 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer and nitrogen
SiClx stacking plus the composite bed formed.
Specifically, being equally oxidized easily because polysilicon is exposed in air, oxide layer, therefore the step 4 are generated
In, before the insulating barrier 50 is formed, the substrate for needing also exist for obtaining the step 3 using hydrofluoric acid (HF) is carried out clearly
Wash, to remove the oxide layer on the surface of active layer 40.
Step 5, as shown in fig. 6, on the insulating barrier 50 formed the first metal layer 53.
Specifically, in the step 5, the first metal layer 53 is formed by physical gas-phase deposite method (PVD).
Specifically, the material of the first metal layer 53 be molybdenum (Mo), titanium (Ti), aluminium (Al), one kind in copper (Cu) or
A variety of heap stack combinations.
Specifically, in the step 5, before the first metal layer 53 is formed, using deionized water or addition cleaning agent
The substrate that is obtained to the step 4 of deionized water clean, to remove surface contaminant, the cleaning agent can be surface
Activating agent.
Step 6, as Figure 7-9, a photoresist layer 55 is coated with the first metal layer 53, it is exposed using a light shield
After light, development, the first metal layer 53, insulating barrier 50 and metal oxide layer 33 are entered successively using 3 dry ecthing procedures
Row etching, obtains the light shield layer 70 that the grid 60 of consistency from top to bottom aligns with gate insulator 57 and with the active layer 40, and
The width of the grid 60 and gate insulator 57 is less than the width of the active layer 40 and light shield layer 70, peels off afterwards remaining
Photoresist layer 55.
Specifically, being etched using first of dry ecthing procedure to the first metal layer 53, grid 60 is obtained, is used
Etching gas be chlorine (Cl2) and oxygen (O2) mixed gas or sulfur hexafluoride (SF6) and oxygen (O2) gaseous mixture
Body；
The insulating barrier 50 is etched using second dry ecthing procedure, obtains gate insulator 57, the erosion of use
Quarter, gas was carbon tetrafluoride (CF4) and oxygen (O2) mixed gas or sulfur hexafluoride (SF6) and oxygen (O2) gaseous mixture
Body；
The metal oxide layer 33 is etched using the 3rd dry ecthing procedure, obtains light shield layer 70, use
Etching gas is chlorine (Cl2) and sulfur hexafluoride (SF6) mixed gas or boron chloride (BCl3) gas.
Specifically, in above-mentioned 3 dry ecthing procedure, by adjusting gas component and ratio in etching gas, reduce
Influence to active layer 40, so as to avoid causing to damage to active layer 40 in etching process.
Above-mentioned steps 1 to step 6, form on the substrate 10 the cushion 20 set gradually from top to bottom, light shield layer 70,
Active layer 40, gate insulator 57 and grid 60, it (is respectively that step 3 and step 6) and 4 times are clear to employ 2 optical cover process altogether
Processing procedure is washed, compared with the processing procedure of the LTPS array base paltes shown in Fig. 1, the relative position of cushion 20 and light shield layer 70 is exchanged,
And the material of the light shield layer 70 is replaced by good metal oxide (such as oxygen of heat-insulating property from conventional metal molybdenum (Mo)
Change aluminium), so as to improve crystallinity when amorphous silicon layer 34 crystallizes, be advantageous to improve the electron mobility of TFT devices
(Mobility)；Manufacturing process for cleaning lithographic process (including light blockage coating, exposure imaging and light together with is also reduced simultaneously
Processing procedure is peeled off in resistance), so as to reduce the production cost of 1 light shield, and reduce the processing time (Tact of LTPS array base paltes
Time), it is cost-saved, lift production capacity.
Specifically, the preparation method of the LTPS array base paltes can also comprise the following steps：
Step 7, as shown in Figure 10, the formation interlayer insulating film 80 on the grid 60, active layer 40 and cushion 20,
Processing is patterned to the interlayer insulating film 80 using one of lithographic process, obtains corresponding respectively to the active layer 40
Two vias 81 above both sides.
Specifically, the step 7 forms the interlayer insulating film 80 by chemical gaseous phase depositing process (CVD).
Specifically, the interlayer insulating film 80 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite bed formed is superimposed with silicon nitride layer.
Step 8, as depicted in figs. 11-12, the depositing second metal layer 90 on the interlayer insulating film 80, using one of photoetching
Processing procedure is patterned processing to the second metal layer 90, obtains 92 points of source electrode 91 and drain electrode 92, the source electrode 91 and drain electrode
It is not in contact via two vias 81 with the both sides of the active layer 40.
Specifically, in the step 8, the second metal layer 90 is formed by physical gas-phase deposite method (PVD).
Specifically, the material of the second metal layer 90 be molybdenum (Mo), titanium (Ti), aluminium (Al), one kind in copper (Cu) or
A variety of heap stack combinations.
In summary, the preparation method of a kind of LTPS array base paltes provided by the invention, compared with prior art, will be buffered
The relative position of layer and light shield layer is exchanged, and the material of the light shield layer is replaced by into heat insulating ability from conventional metal molybdenum (Mo)
Can good metal oxide (such as aluminum oxide), crystallinity during so as to improve amorphous silicon layer, be advantageous to improve TFT devices
The electron mobility (Mobility) of part；Reduce a manufacturing process for cleaning with together with lithographic process (including light blockage coating, exposure show
Shadow and photoresistance peel off processing procedure), so as to reduce the production cost of 1 light shield, and reduce the processing time of LTPS array base paltes
(Tact time), it is cost-saved, lift production capacity.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the claims in the present invention
Protection domain.
Claims (9)
1. a kind of preparation method of LTPS array base paltes, it is characterised in that comprise the following steps：
Step 1, provide a substrate (10), sequentially formed on the substrate (10) cushion (30), metal oxide layer (33),
And amorphous silicon layer (34)；The material of the metal oxide layer (33) is aluminum oxide；
Step 2, the amorphous silicon layer (34) is converted into by polysilicon layer (35) using low temperature crystallization technique；
Step 3, processing is patterned to the polysilicon layer (35) using one of lithographic process, obtains active layer (40), and
Channel doping is carried out to the active layer (40), and N-type heavy doping is carried out to the both ends of the active layer (40), while to institute
The raceway groove both sides progress N-type for stating active layer (40) is lightly doped；
Step 4, form insulating barrier (50) on the active layer (40) and metal oxide layer (33)；
Step 5, the first metal layer (53) is formed on the insulating barrier (50)；
Step 6, a photoresist layer (55) is coated with the first metal layer (53), after exposing, develop to it using a light shield, adopted
The first metal layer (53), insulating barrier (50) and metal oxide layer (33) are lost successively with 3 dry ecthing procedures
Carve, obtain the grid (60) and gate insulator (57) and the light shield layer to be alignd with the active layer (40) of consistency from top to bottom
(70), and the width of the grid (60) and gate insulator (57) is less than the width of the active layer (40) and light shield layer (70)
Degree, peels off remaining photoresist layer (55) afterwards.
2. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that in the step 6, using first
Road dry ecthing procedure is etched to the first metal layer (53), obtains grid (60), the etching gas used for chlorine with
The mixed gas or sulfur hexafluoride of oxygen and the mixed gas of oxygen；
The insulating barrier (50) is etched using second dry ecthing procedure, obtains gate insulator (57), the erosion of use
It is carbon tetrafluoride and the mixed gas or sulfur hexafluoride of oxygen and the mixed gas of oxygen to carve gas；
The metal oxide layer (33) is etched using the 3rd dry ecthing procedure, obtains light shield layer (70), use
Etching gas is the mixed gas or boron chloride gas of chlorine and sulfur hexafluoride.
3. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that in the step 1, pass through chemistry
CVD method forms the cushion (30)；The metal oxide layer (33) is formed by physical gas-phase deposite method；
The amorphous silicon layer (34) is formed by chemical gaseous phase depositing process；In the step 4, formed by chemical gaseous phase depositing process
The insulating barrier (50)；In the step 5, the first metal layer (53) is formed by physical gas-phase deposite method.
4. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that in the step 2, the low temperature
Crystallization processes are quasi-molecule laser annealing method.
5. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that slow being formed in the step 1
Rush before layer (30), substrate (10) is cleaned using deionized water or the deionized water for adding cleaning agent；
In the step 2, before low temperature crystallized to the amorphous silicon layer (34) progress, the step 1 is obtained using hydrofluoric acid
To substrate cleaned；
In the step 4, before the insulating barrier (50) is formed, the substrate obtained using hydrofluoric acid to the step 3 is carried out
Cleaning；
In the step 5, before the first metal layer (53) is formed, using deionized water or the deionized water of addition cleaning agent
The substrate obtained to the step 4 cleans.
6. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that in the step 3, the raceway groove
The processing procedure of doping is：P-type is carried out to whole active layer (40) to be lightly doped, or only the intermediate region of the active layer (40) is entered
Row p-type is lightly doped.
7. the preparation method of LTPS array base paltes as claimed in claim 1, it is characterised in that also comprise the following steps：
Step 7, interlayer insulating film (80) is formed on the grid (60), active layer (40) and cushion (20), using together
Lithographic process is patterned processing to the interlayer insulating film (80), obtains corresponding respectively to the both sides of the active layer (40)
Two vias (81) of top；
Step 8, the depositing second metal layer (90) on the interlayer insulating film (80), using one of lithographic process to described second
Metal level (90) is patterned processing, obtains source electrode (91) and drain electrode (92), and the source electrode (91) passes through respectively with drain electrode (92)
It is in contact by two vias (81) with the both sides of the active layer (40).
8. the preparation method of LTPS array base paltes as claimed in claim 7, it is characterised in that in the step 7, pass through chemistry
CVD method forms the interlayer insulating film (80)；In the step 8, described is formed by physical gas-phase deposite method
Two metal levels (90).
9. the preparation method of LTPS array base paltes as claimed in claim 7, it is characterised in that the cushion (30), insulation
Layer (50) and interlayer insulating film (80) are silicon oxide layer, silicon nitride layer or are superimposed what is formed by silicon oxide layer with silicon nitride layer
Composite bed；The material of the first metal layer (53) and second metal layer (90) is one or more in molybdenum, titanium, aluminium, copper
Heap stack combination.
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| CN105097666A (en) * | 2015-06-15 | 2015-11-25 | 深圳市华星光电技术有限公司 | Fabrication method for low-temperature poly-silicon thin film transistor (TFT) substrate and low-temperature poly-silicon TFT substrate |
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