CN105514123A - Manufacturing method of LTPS array substrate - Google Patents
Manufacturing method of LTPS array substrate Download PDFInfo
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- CN105514123A CN105514123A CN201610060805.4A CN201610060805A CN105514123A CN 105514123 A CN105514123 A CN 105514123A CN 201610060805 A CN201610060805 A CN 201610060805A CN 105514123 A CN105514123 A CN 105514123A
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- array base
- base palte
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- ltps array
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 121
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000002425 crystallisation Methods 0.000 claims abstract description 10
- 230000008025 crystallization Effects 0.000 claims abstract description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 9
- 239000011733 molybdenum Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 172
- 239000011248 coating agent Substances 0.000 claims description 28
- 238000000576 coating method Methods 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 17
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 15
- 239000003595 mist Substances 0.000 claims description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 14
- 239000007792 gaseous phase Substances 0.000 claims description 14
- 239000012212 insulator Substances 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- 239000012071 phase Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 9
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 9
- 239000000460 chlorine Substances 0.000 claims description 8
- 239000012459 cleaning agent Substances 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 abstract description 6
- 230000003139 buffering effect Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000004321 preservation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 13
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000004094 surface-active agent Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method of an LTPS array substrate. Relative positions of a buffering layer and a light shielding layer are interchanged, a material of the light shielding layer is changed into metal oxide good in heat preservation performance from common metal molybdenum, and therefore the crystallization degree of an amorphous silicon layer is improved during crystallization, and the electron mobility of a TFT device is improved easily; one time of cleaning process and one photoetching process are reduced, and therefore production cost of one photomask is reduced, the manufacturing time of the LTPS array substrate is reduced, cost can be saved, and productivity is improved.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of manufacture method of LTPS array base palte.
Background technology
Along with the development of Display Technique, liquid crystal display (LiquidCrystalDisplay, etc. LCD) flat display apparatus is because having the advantages such as the thin and applied range of high image quality, power saving, fuselage, and be widely used in the various consumption electronic products such as mobile phone, TV, personal digital assistant, digital camera, notebook computer, desktop computer, become the main flow in display unit.
Liquid crystal indicator major part on existing market is backlight liquid crystal display, and it comprises display panels and backlight module (backlightmodule).The operation principle of display panels places liquid crystal molecule in the middle of the glass substrate that two panels is parallel, there is the tiny electric wire of many vertical and levels in the middle of two panels glass substrate, change direction by whether being energized to control liquid crystal molecule, the light refraction of backlight module is out produced picture.
Usual display panels is by color film (CF, ColorFilter) substrate, thin-film transistor (TFT, ThinFilmTransistor) substrate, be sandwiched in the liquid crystal (LC between color membrane substrates and thin film transistor base plate, LiquidCrystal) and fluid sealant frame (Sealant) composition, its moulding process generally comprises: leading portion array (Array) processing procedure (film, gold-tinted, etching and stripping), stage casing becomes box (Cell) processing procedure (TFT substrate and CF baseplate-laminating) and back segment module group assembling processing procedure (drive IC and printed circuit board (PCB) pressing).Wherein, leading portion Array processing procedure mainly forms TFT substrate, so that control the motion of liquid crystal molecule; Stage casing Cell processing procedure mainly adds liquid crystal between TFT substrate and CF substrate; The integration of back segment module group assembling processing procedure mainly drive IC pressing and printed circuit board (PCB), and then drive liquid crystal molecule to rotate, display image.
Low temperature polycrystalline silicon (LowTemperaturePolySilicon, LTPS) is a kind of lcd technology be widely used in medium and small electronic product.The electron mobility of traditional amorphous silicon material is about 0.5-1.0cm
2/ V.S, and the electron mobility of low temperature polycrystalline silicon can reach 30-300cm
2/ V.S.Therefore, low-temperature polysilicon liquid crystal on silicon displays has the plurality of advantages such as high-res, reaction speed are fast, high aperture.
In the manufacture of current LTPS array base palte, need through 12-14 exposure manufacture process in the processing procedure of especially traditional CMOS (CMOS (Complementary Metal Oxide Semiconductor)) array base palte, also just need 12-14 road light shield accordingly.But in the board cost of panel factory, because the cost of exposure machine is the highest, mean that exposure sources can not be engrossed in order to cost-saving by panel factory, therefore the production capacity of exposure machine also just governs the product quantity of each large panel manufacturing plant.Therefore, it is possible to saving exposure frequency, namely reduce light shield usage quantity, the prefered method of the cost-saving lifting production capacity of Shi Ge panel factory.
As shown in Figure 1, for the structural representation of the part rete of traditional LTPS array base palte, described LTPS array base palte comprises glass substrate 100, the light shield layer 200 be located on glass substrate 100, the resilient coating 300 be located on described light shield layer 200 and glass substrate 100, the active layer 400 be located on described resilient coating 300, the grid 600 being located at the gate insulator 500 on described active layer 400 and resilient coating 300 and being located on described gate insulator 500.Making programme from light shield layer 200 to the film layer structure of grid 600 in described LTPS array base palte is as follows:
Step 1, first glass substrate 100 to be cleaned, physical gas-phase deposite method (PVD) is adopted to form a metal level on described glass substrate 100, one lithographic process is adopted to carry out graphical treatment to described metal level, obtain light shield layer 200, the material of described light shield layer 200 is generally metal molybdenum (Mo);
Step 2, on described light shield layer 200 and glass substrate 100, form resilient coating 300;
Step 3, employing chemical gaseous phase depositing process (CVD) form an amorphous silicon layer on described resilient coating 300, adopt quasi-molecule laser annealing method that described amorphous silicon layer is converted into polysilicon layer, one lithographic process is adopted to carry out graphical treatment to described polysilicon layer, obtain active layer 400, channel doping and NMOS doping are carried out to described active layer 400;
Step 4, employing chemical gaseous phase depositing process (CVD) form gate insulator 500 on described active layer 400 and resilient coating 300;
Step 5, employing physical gas-phase deposite method (PVD) form a metal level on described gate insulator 500, adopt one lithographic process to carry out graphical treatment to described metal level, obtain grid 600;
Above-mentioned steps 1 to step 5 (from light shield layer 200 to the processing procedure of grid 600) adopts 3 road lithographic process altogether, and therefore need 3 road light shields, cost of manufacture is higher.Except step 1 pair glass substrate 100 cleans, all needed before the processing procedure of described step 2, step 3, step 4, step 5 on the substrate that completes of a link clean, amount to 5 cleaning processes, wash number is more, thus can processing time be increased, reduce production capacity, therefore, be necessary the manufacture method that a kind of LTPS array base palte is provided, to solve this technical problem.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of LTPS array base palte, cost-saved, reduce light shield quantity and processing time, improve production capacity, and promote the electric property of TFT device.
For achieving the above object, the invention provides a kind of manufacture method of LTPS array base palte, comprise the steps:
Step 1, provide a substrate, form resilient coating, metal oxide layer and amorphous silicon layer successively on the substrate;
Described amorphous silicon layer is converted into polysilicon layer by step 2, employing low temperature crystallization technique;
Step 3, adopt one lithographic process to carry out graphical treatment to described polysilicon layer, obtain active layer, and channel doping and NMOS doping are carried out to described active layer;
Step 4, on described active layer and metal oxide layer, form insulating barrier;
Step 5, on described insulating barrier, form the first metal layer;
Step 6, on described the first metal layer, be coated with a photoresist layer, adopt a light shield to after its exposure, development, 3 road dry ecthing procedures are adopted to etch described the first metal layer, insulating barrier and metal oxide layer successively, the grid obtaining consistency from top to bottom and gate insulator and the light shield layer alignd with described active layer, and the width of described grid and gate insulator is less than the width of described active layer and light shield layer, peel off remaining photoresist layer afterwards.
In described step 6, adopt first dry ecthing procedure to etch described the first metal layer, obtain grid, the etching gas of employing is the mist of chlorine and oxygen or the mist of sulphur hexafluoride and oxygen;
Adopt second dry ecthing procedure to etch described insulating barrier, obtain gate insulator, the etching gas of employing is the mist of carbon tetrafluoride and oxygen or the mist of sulphur hexafluoride and oxygen;
Adopt the 3rd road dry ecthing procedure to etch described metal oxide layer, obtain light shield layer, the etching gas of employing is mist or the boron chloride gas of chlorine and sulphur hexafluoride.
In described step 1, form described resilient coating by chemical gaseous phase depositing process; Described metal oxide layer is formed by physical gas-phase deposite method; Described amorphous silicon layer is formed by chemical gaseous phase depositing process; In described step 4, form described insulating barrier by chemical gaseous phase depositing process; In described step 5, form described the first metal layer by physical gas-phase deposite method.
The material of described metal oxide layer is aluminium oxide.
In described step 2, described low temperature crystallization technique is excimer laser annealing method.
In described step 1, before formation resilient coating, the deionized water of deionized water or interpolation cleaning agent is adopted to clean substrate;
In described step 2, described amorphous silicon layer is carried out low temperature crystallized before, adopt hydrofluoric acid the substrate that described step 1 obtains is cleaned;
In described step 4, before the described insulating barrier of formation, hydrofluoric acid is adopted to clean the substrate that described step 3 obtains;
In described step 5, before formation the first metal layer, the deionized water of deionized water or interpolation cleaning agent is adopted to clean the substrate that described step 4 obtains.
In described step 3, the processing procedure of described channel doping is: carry out P type light dope to whole active layer, or only carries out P type light dope to the zone line of described active layer; The processing procedure of described NMOS doping is: carry out N-type heavy doping to the two ends of described active layer, carry out N-type light dope simultaneously to the raceway groove both sides of described active layer.
Also comprise the steps:
Step 7, on described grid, active layer and resilient coating, form interlayer insulating film, adopt one lithographic process to carry out graphical treatment to described interlayer insulating film, obtain two via holes corresponded respectively to above the both sides of described active layer;
Step 8, on described interlayer insulating film depositing second metal layer, adopt one lithographic process to carry out graphical treatment to described second metal level, obtain source electrode and drain electrode, described source electrode with drain electrode contact via the both sides of two via holes with described active layer respectively.
In described step 7, form described interlayer insulating film by chemical gaseous phase depositing process; In described step 8, form described second metal level by physical gas-phase deposite method.
Described resilient coating, insulating barrier and interlayer insulating film are silicon oxide layer, silicon nitride layer or superpose the composite bed formed with silicon nitride layer by silicon oxide layer; The material of described the first metal layer and the second metal level is one or more the heap stack combination in molybdenum, titanium, aluminium, copper.
Beneficial effect of the present invention: the manufacture method of a kind of LTPS array base palte provided by the invention, compared with prior art, the relative position of resilient coating and light shield layer is exchanged, and the material of light shield layer is replaced by the good metal oxide of heat-insulating property from conventional metal molybdenum, thus degree of crystallinity when improve amorphous silicon layer, be conducive to the electron mobility improving TFT device; Reduce manufacturing process for cleaning with together with lithographic process, thus reduce the production cost of 1 road light shield, and reduce the processing time of LTPS array base palte, cost-saving, promote production capacity.
In order to further understand feature of the present invention and technology contents, refer to following detailed description for the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used for being limited the present invention.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, by the specific embodiment of the present invention describe in detail, will make technical scheme of the present invention and other beneficial effect apparent.
In accompanying drawing,
Fig. 1 is the structural representation of the part rete of traditional LTPS array base palte;
Fig. 2 is the schematic diagram of the step 1 of the manufacture method of LTPS array base palte of the present invention;
Fig. 3 is the schematic diagram of the step 2 of the manufacture method of LTPS array base palte of the present invention;
Fig. 4 is the schematic diagram of the step 3 of the manufacture method of LTPS array base palte of the present invention;
Fig. 5 is the schematic diagram of the step 4 of the manufacture method of LTPS array base palte of the present invention;
Fig. 6 is the schematic diagram of the step 5 of the manufacture method of LTPS array base palte of the present invention;
Fig. 7-9 is the schematic diagram of the step 6 of the manufacture method of LTPS array base palte of the present invention;
Figure 10 is the schematic diagram of the step 7 of the manufacture method of LTPS array base palte of the present invention;
Figure 11-12 is the schematic diagram of the step 8 of the manufacture method of LTPS array base palte of the present invention.
Embodiment
For further setting forth the technological means and effect thereof that the present invention takes, be described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
Refer to Fig. 2-12, the invention provides a kind of manufacture method of LTPS array base palte, comprise the steps:
Step 1, as shown in Figure 2, provide a substrate 10, described substrate 10 is formed resilient coating 30, metal oxide layer 33 and amorphous silicon (a-Si) layer 34 successively.
Concrete, in described step 1, form described resilient coating 30 by chemical gaseous phase depositing process (CVD); Described metal oxide layer 33 is formed by physical gas-phase deposite method (PVD); Described amorphous silicon (a-Si) layer 34 is formed by chemical gaseous phase depositing process (CVD).
Concrete, described substrate 10 is glass substrate; Described resilient coating 30 is silica (SiO
x) layer, silicon nitride (SiN
x) layer or superpose the composite bed formed with silicon nitride layer by silicon oxide layer.
Concrete, in described step 1, before formation resilient coating 30, adopt the deionized water of deionized water or interpolation cleaning agent to clean substrate 10, to remove surface contaminant, described cleaning agent can be surfactant.
Described metal oxide layer 33 for forming light shield layer in follow-up lithographic process.
In the selection of the material of described metal oxide layer 33, consider from the angle of heat insulation effect, preferably adopt the good aluminium oxide (Al of heat-insulating property
2o
3).
Step 2, as shown in Figure 3, adopts low temperature crystallization technique that described amorphous silicon layer 34 is converted into polysilicon (poly-Si) layer 35.
Concrete, in described step 2, described low temperature crystallization technique is excimer laser annealing method (ExcimerLaserAnnealing, ELA).
When adopting quasi-molecule laser annealing method to carry out Crystallizing treatment to described amorphous silicon layer 34, below due to amorphous silicon layer 34 is provided with the metal oxide layer 33 with good thermal insulation property, therefore can improve degree of crystallinity during a-Si crystallization, be conducive to the electron mobility (Mobility) improving TFT device.
Concrete, because amorphous silicon is exposed in air easily oxidized, generate oxide layer, therefore in described step 2, described amorphous silicon layer 34 is carried out low temperature crystallized before, also need to adopt hydrofluoric acid (HF) to clean the substrate that described step 1 obtains, to remove the oxide layer on described amorphous silicon (a-Si) layer 34 surface.
Step 3, as shown in Figure 4, adopt polysilicon layer 35 described in one lithographic process to carry out graphical treatment, obtain active layer 40, and channel doping and NMOS doping are carried out to described active layer 40.
Concrete, in described step 3, the processing procedure of described channel doping is: carry out P type light dope to whole active layer 40, or only carry out P type light dope to the zone line of described active layer 40; The processing procedure of described NMOS doping is: carry out N-type heavy doping to the two ends of described active layer 40, carry out N-type light dope simultaneously to the raceway groove both sides of described active layer 40.
Concrete, the ion that described P type light dope mixes is boron ion or gallium ion.
Concrete, the ion that described N-type heavy doping and N-type light dope mix is phosphonium ion or arsenic ion.
Step 4, as shown in Figure 5, described active layer 40 and metal oxide layer 33 form insulating barrier 50.
Concrete, described step 4 forms described insulating barrier 50 by chemical gaseous phase depositing process (CVD).
Concrete, described insulating barrier 50 is silica (SiO
x) layer, silicon nitride (SiN
x) layer or superpose the composite bed formed with silicon nitride layer by silicon oxide layer.
Concrete, because polysilicon is exposed in air equally easily oxidized, generate oxide layer, therefore in described step 4, before the described insulating barrier 50 of formation, need equally to adopt hydrofluoric acid (HF) to clean the substrate that described step 3 obtains, to remove the oxide layer on described active layer 40 surface.
Step 5, as shown in Figure 6, described insulating barrier 50 forms the first metal layer 53.
Concrete, in described step 5, form described the first metal layer 53 by physical gas-phase deposite method (PVD).
Concrete, the material of described the first metal layer 53 is one or more the heap stack combination in molybdenum (Mo), titanium (Ti), aluminium (Al), copper (Cu).
Concrete, in described step 5, before formation the first metal layer 53, adopt the deionized water of deionized water or interpolation cleaning agent to clean the substrate that described step 4 obtains, to remove surface contaminant, described cleaning agent can be surfactant.
Step 6, as Figure 7-9, described the first metal layer 53 is coated with a photoresist layer 55, adopt a light shield to after its exposure, development, 3 road dry ecthing procedures are adopted to etch described the first metal layer 53, insulating barrier 50 and metal oxide layer 33 successively, the grid 60 obtaining consistency from top to bottom and gate insulator 57 and the light shield layer 70 alignd with described active layer 40, and described grid 60 and the width of gate insulator 57 are less than described active layer 40 and the width of light shield layer 70, peel off remaining photoresist layer 55 afterwards.
Concrete, adopt first dry ecthing procedure to etch described the first metal layer 53, obtain grid 60, the etching gas of employing is chlorine (Cl
2) and oxygen (O
2) mist or sulphur hexafluoride (SF
6) and oxygen (O
2) mist;
Adopt second dry ecthing procedure to etch described insulating barrier 50, obtain gate insulator 57, the etching gas of employing is carbon tetrafluoride (CF
4) and oxygen (O
2) mist or sulphur hexafluoride (SF
6) and oxygen (O
2) mist;
Adopt the 3rd road dry ecthing procedure to etch described metal oxide layer 33, obtain light shield layer 70, the etching gas of employing is chlorine (Cl
2) and sulphur hexafluoride (SF
6) mist or boron chloride (BCl
3) gas.
Concrete, in above-mentioned 3 road dry ecthing procedures, by the gas component in adjustment etching gas and ratio, reduce the impact on active layer 40, thus avoid causing damage to active layer 40 in etching process.
Above-mentioned steps 1 to step 6, define the resilient coating 20 set gradually from top to bottom on the substrate 10, light shield layer 70, active layer 40, gate insulator 57, and grid 60, have employed 2 road optical cover process (being respectively step 3 and step 6) and 4 manufacturing process for cleaning altogether, compared with the processing procedure of the LTPS array base palte shown in Fig. 1, the relative position of resilient coating 20 with light shield layer 70 is exchanged, and the material of described light shield layer 70 is replaced by the good metal oxide of heat-insulating property (as aluminium oxide) from conventional metal molybdenum (Mo), thus degree of crystallinity when improve amorphous silicon layer 34 crystallization, be conducive to the electron mobility (Mobility) improving TFT device, also reduce simultaneously manufacturing process for cleaning with together with lithographic process (comprise light blockage coating, exposure imaging and photoresistance and peel off processing procedure), thus reduce the production cost of 1 road light shield, and reduce the processing time (Tacttime) of LTPS array base palte, cost-saved, promote production capacity.
Concrete, the manufacture method of described LTPS array base palte can also comprise the steps:
Step 7, as shown in Figure 10, described grid 60, active layer 40 and resilient coating 20 form interlayer insulating film 80, adopt one lithographic process to carry out graphical treatment to described interlayer insulating film 80, obtain two via holes 81 corresponded respectively to above the both sides of described active layer 40.
Concrete, described step 7 forms described interlayer insulating film 80 by chemical gaseous phase depositing process (CVD).
Concrete, described interlayer insulating film 80 is silica (SiO
x) layer, silicon nitride (SiN
x) layer or superpose the composite bed formed with silicon nitride layer by silicon oxide layer.
Step 8, as depicted in figs. 11-12, depositing second metal layer 90 on described interlayer insulating film 80, one lithographic process is adopted to carry out graphical treatment to described second metal level 90, obtain source electrode 91 and drain electrode 92, described source electrode 91 contacts via the both sides of two via holes 81 with described active layer 40 respectively with drain electrode 92.
Concrete, in described step 8, form described second metal level 90 by physical gas-phase deposite method (PVD).
Concrete, the material of described second metal level 90 is one or more the heap stack combination in molybdenum (Mo), titanium (Ti), aluminium (Al), copper (Cu).
In sum, the manufacture method of a kind of LTPS array base palte provided by the invention, compared with prior art, the relative position of resilient coating and light shield layer is exchanged, and the material of described light shield layer is replaced by the good metal oxide of heat-insulating property (as aluminium oxide) from conventional metal molybdenum (Mo), thus degree of crystallinity when improve amorphous silicon layer, be conducive to the electron mobility (Mobility) improving TFT device; Reduce manufacturing process for cleaning with together with lithographic process (comprise light blockage coating, exposure imaging and photoresistance and peel off processing procedure), thus reduce the production cost of 1 road light shield, and reduce the processing time (Tacttime) of LTPS array base palte, cost-saved, promote production capacity.
The above, for the person of ordinary skill of the art, can make other various corresponding change and distortion according to technical scheme of the present invention and technical conceive, and all these change and be out of shape the protection range that all should belong to the claims in the present invention.
Claims (10)
1. a manufacture method for LTPS array base palte, is characterized in that, comprises the steps:
Step 1, provide a substrate (10), described substrate (10) is formed resilient coating (30), metal oxide layer (33) and amorphous silicon layer (34) successively;
Described amorphous silicon layer (34) is converted into polysilicon layer (35) by step 2, employing low temperature crystallization technique;
Step 3, adopt one lithographic process to carry out graphical treatment to described polysilicon layer (35), obtain active layer (40), and channel doping and NMOS doping are carried out to described active layer (40);
Step 4, on described active layer (40) and metal oxide layer (33), form insulating barrier (50);
Step 5, on described insulating barrier (50), form the first metal layer (53);
Step 6, at upper coating one photoresist layer (55) of described the first metal layer (53), a light shield is adopted to expose it, after development, adopt 3 road dry ecthing procedures successively to described the first metal layer (53), insulating barrier (50), and metal oxide layer (33) etches, obtain the grid (60) of consistency from top to bottom and gate insulator (57), and the light shield layer (70) to align with described active layer (40), and described grid (60) is less than the width of described active layer (40) and light shield layer (70) with the width of gate insulator (57), peel off remaining photoresist layer (55) afterwards.
2. the manufacture method of LTPS array base palte as claimed in claim 1, it is characterized in that, in described step 6, first dry ecthing procedure is adopted to etch described the first metal layer (53), obtain grid (60), the etching gas of employing is the mist of chlorine and oxygen or the mist of sulphur hexafluoride and oxygen;
Adopt second dry ecthing procedure to etch described insulating barrier (50), obtain gate insulator (57), the etching gas of employing is the mist of carbon tetrafluoride and oxygen or the mist of sulphur hexafluoride and oxygen;
Adopt the 3rd road dry ecthing procedure to etch described metal oxide layer (33), obtain light shield layer (70), the etching gas of employing is mist or the boron chloride gas of chlorine and sulphur hexafluoride.
3. the manufacture method of LTPS array base palte as claimed in claim 1, is characterized in that, in described step 1, form described resilient coating (30) by chemical gaseous phase depositing process; Described metal oxide layer (33) is formed by physical gas-phase deposite method; Described amorphous silicon layer (34) is formed by chemical gaseous phase depositing process; In described step 4, form described insulating barrier (50) by chemical gaseous phase depositing process; In described step 5, form described the first metal layer (53) by physical gas-phase deposite method.
4. the manufacture method of LTPS array base palte as claimed in claim 1, it is characterized in that, the material of described metal oxide layer (33) is aluminium oxide.
5. the manufacture method of LTPS array base palte as claimed in claim 1, it is characterized in that, in described step 2, described low temperature crystallization technique is excimer laser annealing method.
6. the manufacture method of LTPS array base palte as claimed in claim 1, it is characterized in that, in described step 1, before formation resilient coating (30), the deionized water of deionized water or interpolation cleaning agent is adopted to clean substrate (10);
In described step 2, described amorphous silicon layer (34) is carried out low temperature crystallized before, adopt hydrofluoric acid the substrate that described step 1 obtains is cleaned;
In described step 4, before the described insulating barrier of formation (50), hydrofluoric acid is adopted to clean the substrate that described step 3 obtains;
In described step 5, before formation the first metal layer (53), the deionized water of deionized water or interpolation cleaning agent is adopted to clean the substrate that described step 4 obtains.
7. the manufacture method of LTPS array base palte as claimed in claim 1, it is characterized in that, in described step 3, the processing procedure of described channel doping is: carry out P type light dope to whole active layer (40), or only carries out P type light dope to the zone line of described active layer (40); The processing procedure of described NMOS doping is: carry out N-type heavy doping to the two ends of described active layer (40), carry out N-type light dope simultaneously to the raceway groove both sides of described active layer (40).
8. the manufacture method of LTPS array base palte as claimed in claim 1, is characterized in that, also comprise the steps:
Step 7, on described grid (60), active layer (40) and resilient coating (20), form interlayer insulating film (80), adopt one lithographic process to carry out graphical treatment to described interlayer insulating film (80), obtain two via holes (81) corresponded respectively to above the both sides of described active layer (40);
Step 8, at the upper depositing second metal layer (90) of described interlayer insulating film (80), one lithographic process is adopted to carry out graphical treatment to described second metal level (90), obtain source electrode (91) and drain electrode (92), described source electrode (91) contacts via the both sides of two via holes (81) with described active layer (40) respectively with drain electrode (92).
9. the manufacture method of LTPS array base palte as claimed in claim 8, is characterized in that, in described step 7, form described interlayer insulating film (80) by chemical gaseous phase depositing process; In described step 8, form described second metal level (90) by physical gas-phase deposite method.
10. the manufacture method of LTPS array base palte as claimed in claim 8, it is characterized in that, described resilient coating (30), insulating barrier (50) and interlayer insulating film (80) they are silicon oxide layer, silicon nitride layer or superpose the composite bed formed with silicon nitride layer by silicon oxide layer; The material of described the first metal layer (53) and the second metal level (90) is one or more the heap stack combination in molybdenum, titanium, aluminium, copper.
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| CN106711157A (en) * | 2017-01-23 | 2017-05-24 | 武汉华星光电技术有限公司 | Production method of LTPS array substrate |
| CN106773431A (en) * | 2017-04-01 | 2017-05-31 | 京东方科技集团股份有限公司 | Liquid crystal display device structure and preparation method thereof |
| CN109643657A (en) * | 2017-06-22 | 2019-04-16 | 深圳市柔宇科技有限公司 | The production method of the making apparatus and array substrate of array substrate |
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| US20150069382A1 (en) * | 2013-09-10 | 2015-03-12 | Samsung Display Co., Ltd. | Thin film transistor substrate and method of manufacturing the same |
| CN105097666A (en) * | 2015-06-15 | 2015-11-25 | 深圳市华星光电技术有限公司 | Fabrication method for low-temperature poly-silicon thin film transistor (TFT) substrate and low-temperature poly-silicon TFT substrate |
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| CN103268047A (en) * | 2012-12-31 | 2013-08-28 | 厦门天马微电子有限公司 | LTPS (Low Temperature Poly-silicon) array base plate and manufacturing method thereof |
| US20150069382A1 (en) * | 2013-09-10 | 2015-03-12 | Samsung Display Co., Ltd. | Thin film transistor substrate and method of manufacturing the same |
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| CN106711157A (en) * | 2017-01-23 | 2017-05-24 | 武汉华星光电技术有限公司 | Production method of LTPS array substrate |
| CN106711157B (en) * | 2017-01-23 | 2019-07-02 | 武汉华星光电技术有限公司 | The production method of LTPS array substrate |
| CN106773431A (en) * | 2017-04-01 | 2017-05-31 | 京东方科技集团股份有限公司 | Liquid crystal display device structure and preparation method thereof |
| CN109643657A (en) * | 2017-06-22 | 2019-04-16 | 深圳市柔宇科技有限公司 | The production method of the making apparatus and array substrate of array substrate |
| CN109643657B (en) * | 2017-06-22 | 2022-08-16 | 深圳市柔宇科技股份有限公司 | Manufacturing equipment and manufacturing method of array substrate |
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