CN105097666A - Fabrication method for low-temperature poly-silicon thin film transistor (TFT) substrate and low-temperature poly-silicon TFT substrate - Google Patents
Fabrication method for low-temperature poly-silicon thin film transistor (TFT) substrate and low-temperature poly-silicon TFT substrate Download PDFInfo
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- CN105097666A CN105097666A CN201510331333.7A CN201510331333A CN105097666A CN 105097666 A CN105097666 A CN 105097666A CN 201510331333 A CN201510331333 A CN 201510331333A CN 105097666 A CN105097666 A CN 105097666A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides a fabrication method for a low-temperature poly-silicon thin film transistor (TFT) substrate and the low-temperature poly-silicon TFT substrate. According to the fabrication method for the low-temperature poly-silicon TFT substrate, by forming a heat-conduction insulation layer having favorable insulation performance and heat conduction characteristic on a buffer layer, a large amount of heat can be absorbed by the buffer layer and transferred to an amorphous silicon layer in contact with the buffer layer during rapid thermal annealing process, the crystallization efficiency of amorphous silicon at the position is improved, poly-silicon with larger grains and less grain boundary is obtained, thus, the migration rate of a carrier of a TFT device is correspondingly enhanced, and the influence of the grain boundary on leakage current is reduced. In the low-temperature poly-silicon TFT substrate provided by the invention, the heat-conduction insulation layer is arranged on the buffer layer corresponding to the below of a poly-silicon semiconductor layer, the grain size of the poly-silicon crystal is large, the number of the grain boundary is less, the migration rate of the carrier of the TFT device is high, and the electrical property of the TFT is high.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of manufacture method and low temperature polycrystalline silicon TFT substrate of low temperature polycrystalline silicon TFT substrate.
Background technology
Along with the development of flat panel display, high-resolution, the panel demand of low energy consumption is constantly suggested.Low temperature polycrystalline silicon (LowTemperaturePoly-Silicon, LTPS) owing to having higher electron mobility, and at liquid crystal display (LiquidCrystalDisplay, LCD) with organic light emitting diode display OrganicLightEmittingDiode, OLED) obtain the attention of industry in technology, be regarded as the important materials realizing the display of low cost full color flat panel.For flat panel display, the advantages such as high-resolution, reaction speed are fast, high brightness, high aperture, low energy consumption that adopt low-temperature polysilicon silicon materials to have, and low temperature polycrystalline silicon can make at low temperatures, and can be used for making C-MOS circuit, thus be widely studied, in order to reach panel high-resolution, the demand of low energy consumption.
Low temperature polycrystalline silicon is a branch of polysilicon (poly-Si) technology.The ordered state of molecular structure in a crystal grain of polysilicon is neat and directive, and the amorphous silicon (a-Si) that therefore electron mobility is more mixed and disorderly than arrangement is fast 200-300 times, greatly improves the reaction speed of flat panel display.Current making low temperature polycrystalline silicon mainly contains: chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD), solid-phase crystallization (SolidPhaseCrystallization, SPC), crystallization inducing metal (Metal-InducedCrystallization, MIC), metal induced lateral crystallization (Metal-InducedLateralCrystallization, MILC), the multiple crystallization manufacturing method thereof such as quasi-molecule laser annealing (ExcimerLaserAnnealing, ELA).
Refer to Fig. 1 to Fig. 6, the manufacture method of existing low temperature polycrystalline silicon TFT substrate mainly comprises the steps: step 1, provides a substrate 100, buffer layer 200 over the glass substrate 100; Step 2, on resilient coating 200 deposition of amorphous silicon (a-Si) layer 300; Step 3, amorphous silicon layer 300 utilize ion embedding technology implant the boron (boron) of doses, again by rapid thermal annealing (RapidThermalAnneal, RTA) crystallization technique heating 20-30min, recrystallized amorphous silicon is made to become polysilicon (poly-Si), then conductive layer very little from one deck resistance of polysilicon surface precipitation in crystallization process is etched away, the remaining polysilicon layer 400 needed; Step 4, by gold-tinted, etch process, patterned process is carried out to polysilicon layer 400, form polysilicon semiconductor layer 450; Step 5, on polysilicon semiconductor layer 450, be coated with photoresistance, by exposing photoresistance, developing, obtain the photoresist layer 550 be positioned on polysilicon semiconductor layer 450, expose two end regions of polysilicon semiconductor layer 450; With photoresist layer 550 for shielding layer, to two end regions of polysilicon semiconductor layer 450, by ion embedding technology boron implant ion, form source/drain contact zone 451; Step 6, stripping resistance layer 550, polysilicon semiconductor layer 450 is formed gate insulator 500, grid 600, interlayer insulating film 700, source/drain 800 successively.
Traditional SPC crystallization processing procedure is formed by about low temperature polycrystalline silicon in the manufacture method of above-mentioned low temperature polycrystalline silicon TFT substrate, although this SPC crystallization processing procedure can obtain the good crystal grain of homogeneity, but crystal grain is less than normal, crystal boundary is more, can affect the mobility of charge carrier and the leakage current of TFT device.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of low temperature polycrystalline silicon TFT substrate, effectively can improve the crystallization efficiency of crystallization processing procedure, increase crystallite dimension, reduce number of grain boundaries, thus the mobility of TFT device charge carrier can be strengthened, reduce crystal boundary to the impact of leakage current, improve the electrical of TFT.
Another object of the present invention is to provide a kind of low temperature polycrystalline silicon TFT substrate, the crystallite dimension of polysilicon crystal is comparatively large, and number of grain boundaries is less, and the mobility of TFT device charge carrier is higher, and TFT's is electrically better.
For achieving the above object, the invention provides a kind of manufacture method of low temperature polycrystalline silicon TFT substrate, comprise the steps:
Step 1, provide a substrate, buffer layer on substrate;
Step 2, on the buffer layer deposition one deck heat conducting insulating film, and patterned process is carried out to this heat conducting insulating film, obtain thermally conductive insulating layer;
Step 3, on the buffer layer deposition of amorphous silicon layers, described amorphous silicon layer covers described thermally conductive insulating layer completely;
Step 4, employing ion embedding technology are implanted into boron ion at amorphous silicon layer, again quick thermal annealing process is carried out to amorphous silicon layer, make recrystallized amorphous silicon become polysilicon, then etch away the conductive layer from polysilicon surface precipitation in crystallization process by etch process, obtain polysilicon layer;
Step 5, patterned process is carried out to polysilicon layer, form polysilicon semiconductor layer;
Step 6, on described polysilicon semiconductor layer, be coated with photoresistance, by exposing described photoresistance, develop, obtain being positioned at the photoresist layer on described polysilicon semiconductor layer, expose two end regions of described polysilicon semiconductor layer; With described photoresist layer for shielding layer, ion embedding technology boron implant ion is passed through to two end regions of described polysilicon semiconductor layer, forms source/drain contact zone;
Step 7, peel off described photoresist layer, polysilicon semiconductor layer forms gate insulator, grid, interlayer insulating film, source/drain successively, and described source/drain contacts with the source/drain contact zone at polysilicon semiconductor layer two ends.
In described step 1, the material of described resilient coating is SiNx, SiOx or the combination of the two.
In described step 2, by gold-tinted, etch process, patterned process is carried out to described thermally conductive insulating layer; The material of described thermally conductive insulating layer is Al
2o
3; The thickness of described thermally conductive insulating layer is 30-50nm.
In described step 3, the thickness of described amorphous silicon layer is 200-300nm.
In described step 4, the temperature of quick thermal annealing process is 650 DEG C-700 DEG C, and the time is 15-25 minute; The thickness etching away the conductive layer that polysilicon surface is separated out is 100-150nm.
In described step 5, by gold-tinted, etch process, patterned process is carried out to polysilicon layer; The figure of described thermally conductive insulating layer is corresponding with the figure of described polysilicon semiconductor layer.
In described step 7, the material of described gate insulator is SiOx.
The present invention also provides a kind of low temperature polycrystalline silicon TFT substrate, comprise substrate, the resilient coating be located on described substrate, the thermally conductive insulating layer be located on described resilient coating, the polysilicon semiconductor layer be located in described thermally conductive insulating layer, be located at described resilient coating covers described thermally conductive insulating layer and polysilicon semiconductor layer gate insulator, the grid be located on described gate insulator, be located at the interlayer insulating film described gate insulator covering described grid and the source/drain be located on described interlayer insulating film;
Two end regions of described polysilicon semiconductor layer are the source/drain contact zone of boron implant ion; Described gate insulator and interlayer insulating film are respectively equipped with via hole above corresponding described source/drain contact zone; Described source/drain contacts with described source/drain contact zone via described via hole respectively.
The material of described resilient coating is SiNx, SiOx or the combination of the two; The material of described thermally conductive insulating layer is Al
2o
3; The material of described gate insulator is SiOx.
The thickness of described thermally conductive insulating layer is 30-50nm; The figure of described thermally conductive insulating layer is corresponding with the figure of described polysilicon semiconductor layer.
Beneficial effect of the present invention: the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention, by forming one deck insulation property and the good thermally conductive insulating layer of thermal conductive property on the buffer layer, make it can absorb amount of heat very soon and pass to the amorphous silicon layer contacted with it in quick thermal annealing process process, recrystallized amorphous silicon efficiency is herein improved, obtain the polysilicon that crystal grain is larger, crystal boundary is less, thus wild phase answers the mobility of TFT device charge carrier, reduce crystal boundary to the impact of leakage current.Low temperature polycrystalline silicon TFT substrate of the present invention, on resilient coating, the below of corresponding polysilicon semiconductor layer is provided with thermally conductive insulating layer, and the crystallite dimension of polysilicon crystal is comparatively large, and number of grain boundaries is less, and the mobility of TFT device charge carrier is higher, and TFT's is electrically better.
Accompanying drawing explanation
In order to further understand feature of the present invention and technology contents, refer to following detailed description for the present invention and accompanying drawing, but accompanying drawing only provides reference and explanation use, is not used for being limited the present invention.
In accompanying drawing,
Fig. 1 is the schematic diagram of the step 1 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 2 is the schematic diagram of the step 2 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 3 is the schematic diagram of the step 3 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 4 is the schematic diagram of the step 4 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 5 is the schematic diagram of the step 5 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 6 is the schematic diagram of the step 6 of the manufacture method of existing low temperature polycrystalline silicon TFT substrate;
Fig. 7 is the flow chart of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Fig. 8 is the schematic diagram of the step 1 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Fig. 9 is the schematic diagram of the step 2 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Figure 10 is the schematic diagram of the step 3 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Figure 11 is the schematic diagram being implanted into a certain amount of boron in the step 4 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention at amorphous silicon layer;
Figure 12 is the schematic diagram after the step 4 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention completes;
Figure 13 is the schematic diagram of the step 5 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Figure 14 is the schematic diagram of the step 6 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention;
Figure 15 is the schematic diagram of the step 7 of the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention and the cross-sectional view of low temperature polycrystalline silicon TFT substrate of the present invention.
Embodiment
For further setting forth the technological means and effect thereof that the present invention takes, be described in detail below in conjunction with the preferred embodiments of the present invention and accompanying drawing thereof.
Refer to Fig. 7 to Figure 15, first the present invention provides a kind of manufacture method of low temperature polycrystalline silicon TFT substrate, comprises the steps:
Step 1, as shown in Figure 8, provide a substrate 1, on substrate 1 buffer layer 2;
Described substrate 1 is common transparency carrier, and preferably, described substrate 1 is glass substrate;
Particularly, the material of described resilient coating 2 can be SiNx, SiOx or the combination of the two.
Step 2, as shown in Figure 9, deposits one deck heat conducting insulating film on the buffer layer 2, and carries out patterned process to this heat conducting insulating film, obtain thermally conductive insulating layer 3;
Concrete, the Al that the material of described thermally conductive insulating layer 3 is
2o
3.
Preferably, the thickness of described thermally conductive insulating layer 3 is 30-50nm.
Particularly, by gold-tinted, etch process, patterned process is carried out to described thermally conductive insulating layer 3, make the size of described thermally conductive insulating layer 3 equal the size of the follow-up polysilicon semiconductor layer 5 that will make.
Step 3, as shown in Figure 10, deposition of amorphous silicon layers 4 on the buffer layer 2, described amorphous silicon layer 4 covers described thermally conductive insulating layer 3 completely;
Preferably, the thickness of described amorphous silicon layer 4 is 200-300nm.
Step 4, as shown in Figure 11, Figure 12, ion embedding technology is adopted to be implanted into a certain amount of boron ion at amorphous silicon layer 4, again quick thermal annealing process is carried out to amorphous silicon layer 4, recrystallized amorphous silicon is made to become polysilicon, then etch away the conductive layer from polysilicon surface precipitation in crystallization process by etch process, obtain polysilicon layer 5;
Particularly, the temperature of quick thermal annealing process is 650 DEG C-700 DEG C, and the time is 15-25 minute;
Preferably, the thickness etching away the conductive layer that polysilicon surface is separated out is 100-150nm, is removed completely by described conductive layer, only remaining polysilicon structure.
Step 5, as shown in figure 13, by gold-tinted, etch process, patterned process is carried out to polysilicon layer 5, form polysilicon semiconductor layer 50;
Concrete, the figure of described polysilicon semiconductor layer 50 is corresponding with the figure of described thermally conductive insulating layer 3.
Step 6, as shown in figure 14, described polysilicon semiconductor layer 50 is coated with photoresistance, by exposing described photoresistance, develop, obtains being positioned at the photoresist layer 55 on described polysilicon semiconductor layer 50, expose two end regions of described polysilicon semiconductor layer 50; With described photoresist layer 55 for shielding layer, to two end regions of described polysilicon semiconductor layer 50, by ion embedding technology boron implant ion, form source/drain contact zone 51;
Step 7, as shown in figure 15, peel off described photoresist layer 55, polysilicon semiconductor layer 50 is formed gate insulator 6, grid 7, interlayer insulating film 8, source/drain 9 successively, and the source/drain contact zone 51 of described source/drain 9 and polysilicon semiconductor layer 50 liang of end regions contacts.
So far, the making of this low temperature polycrystalline silicon TFT substrate is completed.Because thermally conductive insulating layer 3 has good insulation property and thermal conductive property, in RTA processing procedure, thermally conductive insulating layer 3 can absorb amount of heat very soon and pass to the amorphous silicon layer 4 contacted with it, recrystallized amorphous silicon efficiency is herein improved, the crystal grain of the polysilicon in the polysilicon layer 5 formed in described step 4 is larger, crystal boundary is less, the polysilicon semiconductor layer 50 formed in step 5 electrically better, thus the mobility of TFT device charge carrier can be answered by wild phase, reduce crystal boundary to the impact of leakage current, improve the electrical of TFT.
Refer to Figure 15, the present invention also provides a kind of low temperature polycrystalline silicon TFT substrate, comprise substrate 1, the resilient coating 2 be located on described substrate 1, the thermally conductive insulating layer 3 be located on described resilient coating 2, the polysilicon semiconductor layer 50 be located in described thermally conductive insulating layer 3, be located at described resilient coating 2 covers described thermally conductive insulating layer 3 and polysilicon semiconductor layer 50 gate insulator 6, the grid 7 be located on described gate insulator 6, be located at the interlayer insulating film 8 described gate insulator 6 covering described grid 7 and the source/drain 9 be located on described interlayer insulating film 8.
Two end regions of described polysilicon semiconductor layer 50 are the source/drain contact zone 51 of boron implant ion; Described gate insulator 6 and interlayer insulating film 8 are respectively equipped with via hole 91 above corresponding described source/drain contact zone 51; Described source/drain 9 contacts with described source/drain contact zone 51 via described via hole 91 respectively.
Concrete, the material of described resilient coating 2 can be SiNx, SiOx or the combination of the two.
Preferably, the material of described thermally conductive insulating layer 3 is Al
2o
3.Concrete, the material of described gate insulator 6 is SiOx.
Preferably, the thickness of described thermally conductive insulating layer 3 is 30-50nm.
Concrete, the figure of described thermally conductive insulating layer 3 is corresponding with the figure of described polysilicon semiconductor layer 50.
Above-mentioned low temperature polycrystalline silicon TFT substrate, on resilient coating, the below of corresponding polysilicon semiconductor layer is provided with thermally conductive insulating layer, and the crystallite dimension of polysilicon crystal is comparatively large, and number of grain boundaries is less, and the mobility of TFT device charge carrier is higher, and TFT's is electrically better.
In sum, the manufacture method of low temperature polycrystalline silicon TFT substrate of the present invention, by forming one deck insulation property and the good thermally conductive insulating layer of thermal conductive property on the buffer layer, make it can absorb amount of heat very soon and pass to the amorphous silicon layer contacted with it in quick thermal annealing process process, recrystallized amorphous silicon efficiency is herein improved, obtain the polysilicon that crystal grain is larger, crystal boundary is less, thus wild phase answers the mobility of TFT device charge carrier, reduce crystal boundary to the impact of leakage current.Low temperature polycrystalline silicon TFT substrate of the present invention, on resilient coating, the below of corresponding polysilicon semiconductor layer is provided with thermally conductive insulating layer, and the crystallite dimension of polysilicon crystal is comparatively large, and number of grain boundaries is less, and the mobility of TFT device charge carrier is higher, and TFT's is electrically better.
The above; for the person of ordinary skill of the art; can make other various corresponding change and distortion according to technical scheme of the present invention and technical conceive, and all these change and be out of shape the protection range that all should belong to the accompanying claim of the present invention.
Claims (10)
1. a manufacture method for low temperature polycrystalline silicon TFT substrate, is characterized in that, comprises the steps:
Step 1, provide a substrate (1), at the upper buffer layer (2) of substrate (1);
Step 2, at resilient coating (2) upper deposition one deck heat conducting insulating film, and patterned process is carried out to this heat conducting insulating film, obtain thermally conductive insulating layer (3);
Step 3, at the upper deposition of amorphous silicon layers (4) of resilient coating (2), described amorphous silicon layer (4) covers described thermally conductive insulating layer (3) completely;
Step 4, employing ion embedding technology are implanted into boron ion at amorphous silicon layer (4), again quick thermal annealing process is carried out to amorphous silicon layer (4), recrystallized amorphous silicon is made to become polysilicon, then etch away the conductive layer from polysilicon surface precipitation in crystallization process by etch process, obtain polysilicon layer (5);
Step 5, patterned process is carried out to polysilicon layer (5), form polysilicon semiconductor layer (50);
Step 6, on described polysilicon semiconductor layer (50), be coated with photoresistance, by exposing described photoresistance, develop, obtain the photoresist layer (55) be positioned on described polysilicon semiconductor layer (50), expose two end regions of described polysilicon semiconductor layer (50); With described photoresist layer (55) for shielding layer, ion embedding technology boron implant ion is passed through to two end regions of described polysilicon semiconductor layer (50), forms source/drain contact zone (51);
Step 7, peel off described photoresist layer (55), polysilicon semiconductor layer (50) is formed gate insulator (6), grid (7), interlayer insulating film (8), source/drain (9) successively, and described source/drain (9) contacts with the source/drain contact zone (51) at polysilicon semiconductor layer (50) two ends.
2. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, it is characterized in that, in described step 1, the material of described resilient coating (2) is SiNx, SiOx or the combination of the two.
3. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, is characterized in that, in described step 2, carry out patterned process by gold-tinted, etch process to described heat conducting insulating film; The material of described thermally conductive insulating layer (3) is Al
2o
3; The thickness of described thermally conductive insulating layer (3) is 30-50nm.
4. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, it is characterized in that, in described step 3, the thickness of described amorphous silicon layer (4) is 200-300nm.
5. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, it is characterized in that, in described step 4, the temperature of quick thermal annealing process is 650 DEG C-700 DEG C, and the time is 15-25 minute; The thickness etching away the conductive layer that polysilicon surface is separated out is 100-150nm.
6. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, is characterized in that, in described step 5, carry out patterned process by gold-tinted, etch process to polysilicon layer (5); The figure of described thermally conductive insulating layer (3) is corresponding with the figure of described polysilicon semiconductor layer (50).
7. the manufacture method of low temperature polycrystalline silicon TFT substrate as claimed in claim 1, it is characterized in that, in described step 7, the material of described gate insulator (6) is SiOx.
8. a low temperature polycrystalline silicon TFT substrate, it is characterized in that, comprise substrate (1), be located at the resilient coating (2) on described substrate (1), be located at the thermally conductive insulating layer (3) on described resilient coating (2), be located at the polysilicon semiconductor layer (50) in described thermally conductive insulating layer (3), be located at the upper gate insulator (6) covering described thermally conductive insulating layer (3) and polysilicon semiconductor layer (50) of described resilient coating (2), be located at the grid (7) on described gate insulator (6), be located at the upper interlayer insulating film (8) covering described grid (7) of described gate insulator (6), and the source/drain (9) be located on described interlayer insulating film (8),
Two end regions of described polysilicon semiconductor layer (50) are the source/drain contact zone (51) of boron implant ion; Described gate insulator (6) and upper corresponding described source/drain contact zone (51) top of interlayer insulating film (8) are respectively equipped with via hole (91); Described source/drain (9) contacts with described source/drain contact zone (51) via described via hole (91) respectively.
9. low temperature polycrystalline silicon TFT substrate as claimed in claim 8, it is characterized in that, the material of described resilient coating (2) is SiNx, SiOx or the combination of the two; The material of described thermally conductive insulating layer (3) is Al
2o
3; The material of described gate insulator (6) is SiOx.
10. low temperature polycrystalline silicon TFT substrate as claimed in claim 8, it is characterized in that, the thickness of described thermally conductive insulating layer (3) is 30-50nm; The figure of described thermally conductive insulating layer (3) is corresponding with the figure of described polysilicon semiconductor layer (50).
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| CN201510331333.7A CN105097666B (en) | 2015-06-15 | 2015-06-15 | The preparation method and low temperature polycrystalline silicon TFT substrate of low temperature polycrystalline silicon TFT substrate |
| PCT/CN2015/082667 WO2016201725A1 (en) | 2015-06-15 | 2015-06-29 | Method for manufacturing low-temperature polysilicon thin film transistor (tft) substrate and low-temperature polysilicon tft substrate |
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| CN201510331333.7A CN105097666B (en) | 2015-06-15 | 2015-06-15 | The preparation method and low temperature polycrystalline silicon TFT substrate of low temperature polycrystalline silicon TFT substrate |
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| CN105514123A (en) * | 2016-01-28 | 2016-04-20 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS array substrate |
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| WO2021184430A1 (en) * | 2020-03-18 | 2021-09-23 | 武汉华星光电技术有限公司 | Photosensitive sensor and preparation method therefor, and display panel |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105374882A (en) * | 2015-12-21 | 2016-03-02 | 武汉华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor and preparation method thereof |
| US10192975B2 (en) | 2015-12-21 | 2019-01-29 | Wuhan China Star Optoelectronics Technology Co., Ltd | Low temperature polycrystalline silicon thin film transistor |
| CN105514123A (en) * | 2016-01-28 | 2016-04-20 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS array substrate |
| CN105514123B (en) * | 2016-01-28 | 2018-03-30 | 武汉华星光电技术有限公司 | The preparation method of LTPS array base paltes |
| CN108281350A (en) * | 2018-01-23 | 2018-07-13 | 武汉华星光电半导体显示技术有限公司 | The production method of solid-phase crystallization method and low temperature polycrystalline silicon TFT substrate |
| CN108281350B (en) * | 2018-01-23 | 2020-09-01 | 武汉华星光电半导体显示技术有限公司 | Solid-phase crystallization method and manufacturing method of low-temperature polycrystalline silicon TFT substrate |
| WO2021184430A1 (en) * | 2020-03-18 | 2021-09-23 | 武汉华星光电技术有限公司 | Photosensitive sensor and preparation method therefor, and display panel |
| US11557145B2 (en) | 2020-03-18 | 2023-01-17 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Photo sensor having a photosensitive layer made of intrinsic amorphous silicon, manufacturing method thereof, and display panel having the same |
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| Publication number | Publication date |
|---|---|
| WO2016201725A1 (en) | 2016-12-22 |
| CN105097666B (en) | 2017-12-01 |
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