CN100470764C - Two-dimensional display semiconductor structure and producing method thereof - Google Patents
Two-dimensional display semiconductor structure and producing method thereof Download PDFInfo
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- CN100470764C CN100470764C CNB2007100887231A CN200710088723A CN100470764C CN 100470764 C CN100470764 C CN 100470764C CN B2007100887231 A CNB2007100887231 A CN B2007100887231A CN 200710088723 A CN200710088723 A CN 200710088723A CN 100470764 C CN100470764 C CN 100470764C
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Abstract
This invention relates to a semiconductor structure and its manufacturing method for a plane display including a base plate with an active element region and a capacitance region, a patternized polysilicon layer matched on the active element region and the capacitance region of said base plate including a channel region and a source region and a drain region at both sides of the channel region, a grid stacking layer matched on said channel region and a capacitance stacking layer matched on the polysilicon layer of said capacitance region, in which, both the grid stacking layer and the capacitance stacking layer include a first dielectric layer, a first conduction layer, a second dielectric layer and a second conduction layer, a third dielectric layer matched to said polysilicon layer, the grid stacking layer and the capacitance stacking layer, the third dielectric layer includes a contact window, a pixel electrode matched on the third dielectric layer and connected to the polysilicon layer of the drain region via said contact window.
Description
Technical field
The present invention relates in particular to a kind of semiconductor structure and manufacture method thereof that is applicable to the flat-panel screens that increases capacitance about a kind of semiconductor structure and manufacture method thereof of flat-panel screens.
Background technology
Thin-film transistor is for active matrix type flat-panel screens active element commonly used, in order to drive devices such as active formula LCD, the organic motor active display of active formula and image sensor.Usually according to the composition of thin-film transistor semiconductor layer, film crystal can be divided into polycrystalline SiTFT and amorphous silicon film transistor.
For the element of realizing high-fineness and pixel are arranged, polysilicon replaces amorphous silicon gradually and becomes the development main flow of thin-film transistor technologies.Low temperature polycrystalline silicon (low temperature polysilicon, LTPS) technology are adopted in the making of general polycrystalline SiTFT.Because the carrier mobility of polycrystalline SiTFT is higher, the drive circuit integrated level is preferable, light leakage current is less, so polycrystalline SiTFT often is applied in the high-speed circuit.
Yet the structure of known manufacturing low temperature polycrystalline silicon LCD shows below.Please refer to Figure 1A to Fig. 1 F, at first, provide a substrate 10, this substrate has an active element district A and a capacitive region B.Then, in this substrate 10, utilize the photoresist layer,, on active element district A and capacitive region B, form the polysilicon layer 11 of a patterning again with the first road photoetching process.Then, shown in Figure 1B, be formed with gate insulator 12 in substrate 10 surfaces, and on corresponding to active element district A and capacitive region B, utilize the second road photoetching process to form a gate metal layer 13, and active element district A is defined a light doping section 111 and a heavily doped region 112 with the ion injection mode.This heavily doped region 112 can be used as source area 112s and the drain region 112d among the active element district A respectively.Then, shown in Fig. 1 C, form an inner layer dielectric layer 14 on substrate 10 surfaces with this gate metal layer 13, and by the photoresist layer, on the inner layer dielectric layer 14 of gate metal layer 13 both sides on the active element district A and gate insulator 12, form an interlayer hole 141 on sensible source area 112s and 112d surface, drain region again with one the 3rd road photoetching process.Afterwards, shown in Fig. 1 D, on substrate 10, form a conductive layer 15 again, and make this conductive layer 15 insert in the interlayer hole 141.Utilize the 4th this conductive layer 15 of road photoetching process patterning again.Conductive layer 15 in the interlayer hole 141 on this source area 112s can be used as one source pole conductive layer 15s, and the conductive layer 15 in the interlayer hole 141 on the 112d of drain region can be used as a drain electrode conductive layer 15d.Then, shown in Fig. 1 E, on this substrate 10, form a protective layer 16 again, and after utilizing the photoresist layer,, on corresponding to the drain electrode conductive layer 15s of drain region 112d, form a contact hole 161 again with the 5th road photoetching process.At last, shown in Fig. 1 F, form a conductive layer in these protective layer 16 surfaces and contact hole 161, this conductive layer utilizes the 6th road photoetching process can be made into a pixel electrode 17.
Yet, utilize the mode of this six road photoetching processes to make the low temperature polycrystalline silicon LCD, its manufacturing process is quite tediously long and complicated, and easily produces contraposition deviation or problem such as not accurate because of the use of multiple tracks photoetching process.In addition, directly utilize mask to define light doping section and heavily doped region, also will increase the complexity of technology and can't reduce cost and improve output capacity.Therefore, this manufacturing low temperature polycrystalline silicon LCD method still remains further to be improved.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of semiconductor structure, be applied to a flat-panel screens, its step comprises: at first, provide a substrate, this substrate has an active element district and a capacitive region.Then, on the active element district of substrate and capacitive region, form the polysilicon layer of a patterning.In addition, on substrate, form one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer in regular turn.Then, patterning first dielectric layer, first conductive layer, second dielectric layer and second conductive layer form a grid in the active element district, and form a capacitance electrode on capacitive region.Afterwards, doped polysilicon layer forms an one source pole district and a drain region in the grid both sides, and forms a channel region under grid.Then, on substrate, form an inner layer dielectric layer and a protective layer in regular turn.In protective layer and inner layer dielectric layer, form a drain electrode contact hole again, expose the polysilicon layer of drain region.Then, on substrate, form one the 3rd conductive layer, be electrically connected to the polysilicon layer of drain region.At last, patterning the 3rd conductive layer forms a pixel electrode.
According to the manufacture method of described semiconductor structure, wherein, this substrate comprises a glass substrate or a quartz base plate.
According to the manufacture method of described semiconductor structure, wherein, also be included in and form a resilient coating between this substrate and this polysilicon layer.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this first dielectric layer is in
Between.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this second dielectric layer is in
Between.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, also form this channel region on this capacitive region under formed this capacitance electrode simultaneously.
Manufacture method according to described semiconductor structure, wherein, when mixing this polysilicon layer, be formed with a plurality of light doping sections and a plurality of heavily doped region, described light doping section is formed at formed these channel region both sides under this grid, and described heavily doped region connects described light doping section.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, the dosage that formed described light doping section uses is between 1E16～1E18 atom/cubic centimetre.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, the dosage that formed described heavily doped region uses is between 1E18～1E21 atom/cubic centimetre.
According to the manufacture method of described semiconductor structure, wherein, this heavily doped region is a P type ion heavily doped region or a N type ion heavily doped region.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, also comprise the step of an activation, activating the dopant of this polysilicon layer, and the temperature of activation is between 550～1000 ℃.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this inner layer dielectric layer is in
Between.
In addition, the present invention also provides the manufacture method of another kind of semiconductor structure, is applied to a flat-panel screens, and its step comprises: at first, provide a substrate, this substrate has an active element district and a capacitive region.Then, on the active element district of substrate and capacitive region, form the polysilicon layer of a patterning.Then, on substrate, form one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer in regular turn.In addition, patterning first dielectric layer, first conductive layer, second dielectric layer and second conductive layer form a grid in the active element district, and form the one scan line and electrically connect this grid, and form a common lines on capacitive region.Afterwards, doped polysilicon layer forms an one source pole and a drain electrode in the grid both sides, and forms a channel region under grid.One of them is electrically connected to source electrode many lower floor's data line segments of formation on substrate, and described lower floor data line segment again.Then, on substrate, form an inner layer dielectric layer and a protective layer in regular turn.Then, in protective layer and inner layer dielectric layer, form a drain electrode contact hole and expose this drain electrode, and a plurality of data wire contact hole exposes described lower floor data line segment.At last, on substrate, form the 3rd conductive layer of a patterning, comprise a pixel electrode, be electrically connected to the polysilicon layer of drain region, and many data connecting lines, electrically connect lower floor's data line segment, to form a continuous data wire.
According to the manufacture method of described semiconductor structure, wherein, also be included in and form a resilient coating between this substrate and this polysilicon layer.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this first dielectric layer is in
Between.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this second dielectric layer is in
Between.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, also form this channel region on this capacitive region under formed this capacitance electrode simultaneously.
Manufacture method according to described semiconductor structure, wherein, when mixing this polysilicon layer, be formed with a plurality of light doping sections and a plurality of heavily doped region, described light doping section is formed at formed these channel region both sides under this grid, and described heavily doped region connects described light doping section.
According to the manufacture method of described semiconductor structure, wherein, described light doping section and described heavily doped region form in the mode that ion injects.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, the dosage that formed described light doping section uses is between 1E16～1E18 atom/cubic centimetre.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, the dosage that formed described heavily doped region uses is between 1E18～1E21 atom/cubic centimetre.
According to the manufacture method of described semiconductor structure, wherein, this heavily doped region is a P type ion heavily doped region or a N type ion heavily doped region.
According to the manufacture method of described semiconductor structure, wherein, when mixing this polysilicon layer, also comprise the step of an activation, activating the dopant of this polysilicon layer, and the temperature of activation is between 550～1000 ℃.
According to the manufacture method of described semiconductor structure, wherein, the thickness of this inner layer dielectric layer is in
Between.
Manufacture method according to described semiconductor structure, wherein, formed this common lines of this capacitive region comprises this first dielectric layer, this first conductive layer, this second dielectric layer and this second conductive layer, and this first dielectric layer and this first conductive layer extend to this substrate surface beyond this capacitive region.
According to the manufacture method of described semiconductor structure, wherein, described lower floor data line segment does not contact with this scan line.
In the manufacture method of semiconductor structure of the present invention, substrate is preferably a glass substrate or a quartz base plate.
In the manufacture method of aforementioned semiconductor structure of the present invention, also can between substrate and polysilicon layer, form a resilient coating.This resilient coating preferably can use materials such as silicon or silica.
In the aforementioned manufacture method of the present invention, the thickness of first dielectric layer and second dielectric layer preferably can be in respectively approximately
Between.
In the present invention, when doped polysilicon layer, also form this channel region on the capacitive region under the formed capacitance electrode simultaneously.In addition, when doped polysilicon layer, also can be formed with a plurality of light doping sections and a plurality of heavily doped region, described light doping section is formed at formed channel region both sides under the grid, and described heavily doped region connects light doping section.At this, when mixing this polysilicon layer, the dosage that formed light doping section uses preferably is between 1E16～1E18 atom/cubic centimetre, and the dosage that formed heavily doped region uses preferably is between 1E18～1E21 atom/cubic centimetre.And the mode that described light doping section and heavily doped region can ion inject forms.In addition, heavily doped region preferably can be a P type or N type ion heavily doped region.In addition, when mixing this polysilicon layer, also can comprise the step of an activation (actitation), with the dopant (dopants) of activation polysilicon layer, and this activation temperature preferably can be between 550～1000 ℃.
In the present invention, formed inner layer dielectric layer on substrate, its thickness preferably is in
Between.
In addition, manufacture method of the present invention formed common lines on capacitive region can comprise first dielectric layer, first conductive layer, second dielectric layer and second conductive layer, and first dielectric layer and first conductive layer extend to the substrate surface beyond the capacitive region.In addition, the present invention's formed many lower floor's data line segments on substrate do not contact with scan line.
According to the manufacture method of the semiconductor structure of the invention described above, the semiconductor structure that can be produced as follows, but this semiconductor structure is not limited to above-mentioned making step.
Therefore, the present invention also provides a kind of semiconductor structure, is applied to a flat-panel screens, comprising: the polysilicon layer of a substrate, a patterning, a gate stack, one the 3rd dielectric layer and a pixel electrode.At this, substrate has an active element district and a capacitive region.The polysilicon layer of patterning is disposed in the active element district and capacitive region of substrate, and polysilicon layer has a channel region, and the one source pole district and the drain region that are positioned at the channel region both sides.And gate stack is disposed on the channel region, and an electric capacity stack layer, is disposed on the polysilicon layer of capacitive region, and wherein gate stack and electric capacity stack layer all comprise one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer.The 3rd dielectric layer is disposed on polysilicon layer, gate stack and the electric capacity stack layer, has a contact hole in the 3rd dielectric layer.At last, pixel electrode is disposed on the 3rd dielectric layer, and is electrically connected to the polysilicon layer of drain region via contact hole.
According to described semiconductor structure, wherein, the 3rd dielectric layer comprises an inner layer dielectric layer and a protective layer, and this protective layer is disposed between this inner layer dielectric layer and this pixel electrode.
According to described semiconductor structure, wherein, the thickness of this inner layer dielectric layer is in
Between.
According to described semiconductor structure, wherein, the thickness of this protective layer is greater than the thickness of this inner layer dielectric layer.
According to described semiconductor structure, wherein, the thickness of this first dielectric layer is in
Between.
According to described semiconductor structure, wherein, the thickness of this second dielectric layer is in
Between.
According to described semiconductor structure, wherein, also dispose many lower floor's data line segments on this substrate, and described lower floor data line segment one of them be electrically connected to this source area.
According to described semiconductor structure, wherein, the contact hole of the 3rd dielectric layer part exposes described lower floor data line segment, and electrically connects via many data connecting lines, and forms a continuous data wire.
According to described semiconductor structure, wherein, this scan line and this gate stack electrically connect.
According to described semiconductor structure, wherein, the material of this first conductive layer and this second conductive layer is selected from the group that is made up of aluminium, tungsten, molybdenum and chromium and alloy thereof.
According to described semiconductor structure, wherein, also comprise a resilient coating, it is disposed between this substrate and this polysilicon layer.
In semiconductor structure of the present invention, the 3rd dielectric layer can comprise an inner layer dielectric layer and a protective layer, and protective layer is disposed between inner layer dielectric layer and the pixel electrode.And the thickness of foregoing inner layer dielectric layer preferably can be
Between, and the thickness of protective layer is preferably greater than the thickness of this inner layer dielectric layer.
In the aforementioned semiconductor structure of the present invention, the thickness of this first dielectric layer and second dielectric layer preferably can be in respectively approximately
Between.
In addition, in semiconductor structure of the present invention, also configurable on the substrate have many lower floor's data line segments, and described lower floor data line segment one of them be electrically connected to source area.And the contact hole of the 3rd dielectric layer part preferably exposes described lower floor data line segment, and electrically connects via many data connecting lines, and forms a continuous data wire.In addition, scan line also can electrically connect with gate stack.
In semiconductor structure of the present invention, group or other electric conducting material that the optional free aluminium of the material of first conductive layer and second conductive layer, tungsten, molybdenum and chromium and alloy thereof are formed.
In addition, in semiconductor structure of the present invention, also can comprise a resilient coating, this resilient coating is configurable between substrate and polysilicon layer.This resilient coating for example can use materials such as silicon or silica.
Semiconductor structure of the present invention mainly can be applicable to flat-panel screens, is preferably LCD.
Therefore, in semiconductor structure of the present invention and the manufacture method thereof, in capacitive region, on polysilicon layer, form the electric capacity sandwich of a kind of conductive layer, dielectric layer and conductive layer, can increase the capacitance in the capacitive region.Simultaneously, the structure that manufacture method of the present invention manufactures can increase aperture opening ratio, and can solve because the caused electrical problem that leaks outside of conductive layer.In addition, the present invention is integrated in inner layer dielectric layer with in the technology with protective layer, can overcome the electrical problem of crosstalk (cross-talk).
Description of drawings
Figure 1A to 1F is the structure flow process cutaway view of known manufacturing low temperature polycrystalline silicon LCD.
Fig. 2 to Fig. 6 is the semiconductor structure flow process cutaway view and the top view of the manufacturing flat-panel screens of one embodiment of the invention.
Wherein, description of reference numerals is as follows:
10,20 substrates, 11,21 polysilicon layers
111 light doping sections, 112 heavily doped regions
12 gate insulators, 13 gate metal layer
14,37 inner layer dielectric layers, 141 interlayer holes
15 conductive layer 15s, the source electrode conductive layer
15d drain electrode conductive layer 35s source electrode
161 contact holes, 17,39 pixel electrodes
22 first dielectric layers, 23 first conductive layers
24 second dielectric layers, 25 second conductive layers
31 grids, 311 gate stack
32 capacitance electrodes, 321 electric capacity stack layers
33 scan lines, 331 electric capacity contact holes
34 common lines, 351 drain electrode contact holes
36 lower floor's data line segments
361 data wire contact holes
37 dielectric layers, 391 data connecting lines
40 channel regions, 41 light doping sections
42 heavily doped regions, 50 data wires
60 the 3rd dielectric layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, one of ordinary skill in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.The present invention also can be implemented or be used by other different specific embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications and change under the spirit of the present invention not deviating from.
Accompanying drawing is rough schematic view described in the embodiments of the invention.Described accompanying drawing only shows the element relevant with the present invention, the shape that its shown element is non-when being actual enforcement, and component number, the shape equal proportion during its actual enforcement is an optionally design, and its component placement form may be more complicated.
Please refer to Fig. 2 to Fig. 6, it is the cutaway view and the top view of the semiconductor structure flow process of manufacturing present embodiment flat-panel screens.
At first, please refer to Fig. 2, shown in Fig. 2 A, provide a substrate 20, substrate 20 is a glass substrate in this embodiment, and also a resilient coating (not shown) can be arranged in the surface configuration of substrate 20, and the spendable material of this resilient coating can be silicon or silica.This substrate 20 has an active element district B and a capacitive region C.And the surface of this substrate 20 forms an amorphous silicon layer (not shown) earlier, can utilize the mode of heat treatment or quasi-molecule laser annealing to convert this amorphous silicon layer to a polysilicon layer 21 then.Then, via photoresist layer (not shown), the mode with the first road photoetching process (be the painting photoresist layer, expose and developing process again) forms a patterned polysilicon layer 21 again.After forming the polysilicon layer 21 of this patterning, remove the photoresist layer again, and can obtain shown in Fig. 2 B, contain substrate 20 top views of the polysilicon layer 21 of patterning.
Then, please refer to Fig. 3, in Fig. 3 A, on substrate 20, can form one first dielectric layer 22, one first conductive layer 23, one second dielectric layer 24 and one second conductive layer 25 in regular turn.At this, first dielectric layer 22 and second dielectric layer, 24 spendable materials for example can be silica or silicon nitride, and the thickness of first dielectric layer 22 and second dielectric layer 24 can be in 600～1200 respectively
Between.And first conductive layer 23 and second conductive layer, 25 spendable materials for example can be group or other electric conducting material that aluminium, tungsten, molybdenum and chromium and alloy thereof are formed.And can be via the photoresist layer on the substrate 20 with this first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25, utilize the second road photoetching process, with patterning first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25.Therefore, first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25 on active element district B can form grid 31 in a gate regions g, and this grid 31 is a gate stack 311.Then form a capacitance electrode 32 at capacitive region C, and this capacitance electrode 32 is an electric capacity stack layer 321.In addition, when on the active element district B of substrate 20 and capacitive region C, forming first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25 in regular turn, shown in Fig. 3 B, the position of not containing polysilicon layer 21 on substrate 20 also forms described first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25 simultaneously.And described first dielectric layer 22, first conductive layer 23, second dielectric layer 24 and second conductive layer 25 can form the one scan line 33 shown in Fig. 3 B, and this scan line 33 is electrically connected to grid 31, and form a common lines 34 on capacitive region C.In addition, extend out to the part of substrate, carry out photoetching process, make outward extending part only have first dielectric layer 22 and first conductive layer 23 via GTG (gray-tone) or halftoning (half-tone) mask technique at capacitive region C.Therefore can form a common lines 34.
Then, still please refer to Fig. 3 A, the mode that can utilize autoregistration (self alignment) with P type ion doping to this polysilicon layer 21.And to polysilicon layer 21, for P type ion being located fully and not making polysilicon layer 21 produce infringement even cause decrystallizedly, again via a heat treatment, with its activation, and this activation temperature is between 550～1000 ℃ at P type ion doping.Mix and to have a light doping section 41 and a heavily doped region 42 in grid 31 outsides behind this polysilicon layer 21, wherein, form these light doping section 41 employed dosage and can be between 1E16～1E18 atom/cubic centimetre, can be between 1E18～1E21 atom/cubic centimetre and form heavily doped region 42 employed dosage.At this, light doping section 41 is disposed at the both sides of gate stack 31, and heavily doped region 42 then is disposed at light doping section 41 outsides.And the heavily doped region 42 that is disposed at outside the gate regions g can form an one source pole district s and a drain region d respectively.Source area s has one source pole 35s, and has a drain electrode 35d at drain region d.In addition, form a channel region 40 31 times at grid, and also can form a channel region 40 32 times at the capacitance electrode of capacitive region C.
Then, please refer to Fig. 4 A and 4B, form a metal level (not shown) on this substrate 20, this metal level for example can be materials such as group that aluminium, tungsten, molybdenum and chromium and alloy thereof form or other electric conducting material.Then,, with the 3rd road photoetching process metal level is formed many lower floor's data line segments 36 again via the photoresist layer, and described lower floor data line segment 36 one of them be electrically connected to source electrode 35s.In addition, described lower floor data line segment 36 does not contact with scan line 33.
In addition, please refer to Fig. 5 A and 5B, on this substrate 20, form an inner layer dielectric layer 37 and a protective layer 38 in regular turn.At this, the thickness of formed inner layer dielectric layer 37 is in 1000～6000
Between, and the thickness of protective layer 38 is greater than the thickness of inner layer dielectric layer 37.Then; again in protective layer 38 and inner layer dielectric layer 37 via the photoresist layer, form a drain electrode contact hole 351 with the 4th road photoetching process again and go up formed lower floor data line segment 36, a plurality of data wire contact hole 361 (shown in Fig. 5 B) to expose a lower floor's data line segment 36 and an electric capacity contact hole 331 to expose capacitance electrode 33 to expose drain electrode 35d.
At last, please refer to Fig. 6 A and 6B, on this substrate 20, form one the 3rd conductive layer (not shown), and, form the 3rd conductive layer of a patterning again with the 5th road photoetching process via the photoresist layer.The 3rd conductive layer can be used as a pixel electrode 39 and many data connecting lines 391.Pixel electrode 39 is electrically connected to the polysilicon layer (being heavily doped region 42) of drain region d.Many data connecting line 391 electrically connects lower floor's data line segment 36, to form a continuous data wire 50.
Therefore; the present invention is applied in the structure of flat-panel screens; please refer to Fig. 6 A and 6B, can comprise polysilicon layer 21, a gate stack 311, one the 3rd dielectric layer 60 (it comprises inner layer dielectric layer 37 and protective layer 38) and a pixel electrode 39 of a substrate 20, a patterning.At this, substrate 20 has an active element district B and a capacitive region C.The polysilicon layer 21 of patterning (shown in Fig. 2 A) is disposed on the active element district B and capacitive region C of substrate 20, and polysilicon layer 21 has a channel region 40, and the one source pole district s and the drain region d that are positioned at channel region 40 both sides.And gate stack 311 is disposed on the channel region 40, and one electric capacity stack layer 321 be disposed on the polysilicon layer 21 of capacitive region C, wherein gate stack 311 all comprises one first dielectric layer 22, one first conductive layer 23, one second dielectric layer 24 and one second conductive layer 25 with electric capacity stack layer 321.The 3rd dielectric layer 60 is disposed on polysilicon layer 21, gate stack 311 and the electric capacity stack layer 321, and has a drain electrode contact hole 351 in the 3rd dielectric layer 60.At last, pixel electrode 39 is disposed on the 3rd dielectric layer, and is electrically connected to the drain electrode 35d of drain region d via drain electrode contact hole 351.
In sum; capacitive region among the present invention is made to increase capacitance with electric capacity sandwich (conductive layer, dielectric layer, conductive layer); and inner layer dielectric layer is integrated in in the photoetching technique with protective layer, makes this manufacturing process only need the photoetching process in five roads to complete.Manufacture of the present invention has not only increased the capacitance of capacitive region, and also reaches the purpose that reduces manufacturing process difficulty and production cost and raising output capacity.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described, but not only limits to the foregoing description.
Claims (37)
1. the manufacture method of a semiconductor structure, this semiconductor structure is applied to a flat-panel screens, and its step comprises:
One substrate is provided, and this substrate has an active element district and a capacitive region;
On this active element district of this substrate and this capacitive region, form the polysilicon layer of a patterning;
On this substrate, form one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer in regular turn;
This first dielectric layer of patterning, this first conductive layer, this second dielectric layer and this second conductive layer form a grid in this active element district, and form a capacitance electrode on this capacitive region;
This polysilicon layer that mixes forms an one source pole district and a drain region in these grid both sides, and under this grid formation one channel region;
On this substrate, form an inner layer dielectric layer and a protective layer in regular turn;
In this protective layer and this inner layer dielectric layer, form a drain electrode contact hole, expose this polysilicon layer of this drain region;
On this substrate, form one the 3rd conductive layer, be electrically connected to this polysilicon layer of this drain region; And
Patterning the 3rd conductive layer forms a pixel electrode.
2. the manufacture method of semiconductor structure as claimed in claim 1, wherein, this substrate comprises a glass substrate or a quartz base plate.
3. the manufacture method of semiconductor structure as claimed in claim 1 wherein, also is included in and forms a resilient coating between this substrate and this polysilicon layer.
4. the manufacture method of semiconductor structure as claimed in claim 1, wherein, the thickness of this first dielectric layer is in
Between.
5. the manufacture method of semiconductor structure as claimed in claim 1, wherein, the thickness of this second dielectric layer is in
Between.
6. the manufacture method of semiconductor structure as claimed in claim 1, wherein, when mixing this polysilicon layer, this channel region also is formed on this capacitive region under formed this capacitance electrode simultaneously.
7. the manufacture method of semiconductor structure as claimed in claim 1, wherein, when mixing this polysilicon layer, be formed with a plurality of light doping sections and a plurality of heavily doped region, described light doping section is formed at formed these channel region both sides under this grid, and described heavily doped region connects described light doping section.
8. the manufacture method of semiconductor structure as claimed in claim 7, wherein, when mixing this polysilicon layer, the dosage that formed described light doping section uses is between 1E16～1E18 atom/cubic centimetre.
9. the manufacture method of semiconductor structure as claimed in claim 7, wherein, when mixing this polysilicon layer, the dosage that formed described heavily doped region uses is between 1E18～1E21 atom/cubic centimetre.
10. the manufacture method of semiconductor structure as claimed in claim 7, wherein, this heavily doped region is a P type ion heavily doped region or a N type ion heavily doped region.
11. the manufacture method of semiconductor structure as claimed in claim 7 wherein, when mixing this polysilicon layer, also comprises the step of an activation, activating the dopant of this polysilicon layer, and the temperature of activation is between 550～1000 ℃.
12. the manufacture method of semiconductor structure as claimed in claim 1, wherein, the thickness of this inner layer dielectric layer is in
Between.
13. the manufacture method of a semiconductor structure, this semiconductor structure is applied to a flat-panel screens, and its step comprises:
One substrate is provided, and this substrate has an active element district and a capacitive region;
On this active element district of this substrate and this capacitive region, form the polysilicon layer of a patterning;
On this substrate, form one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer in regular turn;
This first dielectric layer of patterning, this first conductive layer, this second dielectric layer and this second conductive layer form a grid in this active element district, and form the one scan line and electrically connect this grid, and form a common lines on this capacitive region;
This polysilicon layer that mixes forms an one source pole and a drain electrode in these grid both sides, and under this grid formation one channel region;
On this substrate, form many lower floor's data line segments, and described lower floor data line segment one of them be electrically connected to this source electrode;
On this substrate, form an inner layer dielectric layer and a protective layer in regular turn;
In this protective layer and this inner layer dielectric layer, form a drain electrode contact hole and expose this drain electrode, and a plurality of data wire contact hole exposes described lower floor data line segment; And
On this substrate, form the 3rd conductive layer of a patterning, comprise a pixel electrode, be electrically connected to this polysilicon layer of this drain region, and many data connecting lines, electrically connect described lower floor data line segment, to form a continuous data wire.
14. the manufacture method of semiconductor structure as claimed in claim 13 wherein, also is included in and forms a resilient coating between this substrate and this polysilicon layer.
15. the manufacture method of semiconductor structure as claimed in claim 13, wherein, the thickness of this first dielectric layer is in
Between.
16. the manufacture method of semiconductor structure as claimed in claim 13, wherein, the thickness of this second dielectric layer is in
Between.
17. the manufacture method of semiconductor structure as claimed in claim 13, wherein, when mixing this polysilicon layer, this channel region also is formed on this capacitive region under formed this capacitance electrode simultaneously.
18. the manufacture method of semiconductor structure as claimed in claim 13, wherein, when mixing this polysilicon layer, be formed with a plurality of light doping sections and a plurality of heavily doped region, described light doping section is formed at formed these channel region both sides under this grid, and described heavily doped region connects described light doping section.
19. the manufacture method of semiconductor structure as claimed in claim 18, wherein, described light doping section and described heavily doped region form in the mode that ion injects.
20. the manufacture method of semiconductor structure as claimed in claim 18, wherein, when mixing this polysilicon layer, the dosage that formed described light doping section uses is between 1E16～1E18 atom/cubic centimetre.
21. the manufacture method of semiconductor structure as claimed in claim 18, wherein, when mixing this polysilicon layer, the dosage that formed described heavily doped region uses is between 1E18～1E21 atom/cubic centimetre.
22. the manufacture method of semiconductor structure as claimed in claim 18, wherein, this heavily doped region is a P type ion heavily doped region or a N type ion heavily doped region.
23. the manufacture method of semiconductor structure as claimed in claim 18 wherein, when mixing this polysilicon layer, also comprises the step of an activation, activating the dopant of this polysilicon layer, and the temperature of activation is between 550～1000 ℃.
24. the manufacture method of semiconductor structure as claimed in claim 13, wherein, the thickness of this inner layer dielectric layer is in
Between.
25. the manufacture method of semiconductor structure as claimed in claim 13, wherein, formed this common lines of this capacitive region comprises this first dielectric layer, this first conductive layer, this second dielectric layer and this second conductive layer, and this first dielectric layer and this first conductive layer extend to this substrate surface beyond this capacitive region.
26. the manufacture method of semiconductor structure as claimed in claim 13, wherein, described lower floor data line segment does not contact with this scan line.
27. a semiconductor structure is applied to a flat-panel screens, comprising:
One substrate, it has an active element district and a capacitive region;
The polysilicon layer of one patterning, it is disposed in this active element district and this capacitive region of this substrate, and this polysilicon layer has a channel region, and the one source pole district and the drain region that are positioned at the channel region both sides;
One gate stack, be disposed on this channel region, and an electric capacity stack layer, be disposed on this polysilicon layer of this capacitive region, wherein this gate stack and this electric capacity stack layer all comprise one first dielectric layer, one first conductive layer, one second dielectric layer and one second conductive layer;
One the 3rd dielectric layer is disposed on this polysilicon layer, this gate stack and this electric capacity stack layer, has a contact hole in the 3rd dielectric layer; And
One pixel electrode is disposed on the 3rd dielectric layer, and is electrically connected to this polysilicon layer of this drain region via this contact hole.
28. semiconductor structure as claimed in claim 27, wherein, the 3rd dielectric layer comprises an inner layer dielectric layer and a protective layer, and this protective layer is disposed between this inner layer dielectric layer and this pixel electrode.
29. semiconductor structure as claimed in claim 28, wherein, the thickness of this inner layer dielectric layer is in
Between.
30. semiconductor structure as claimed in claim 28, wherein, the thickness of this protective layer is greater than the thickness of this inner layer dielectric layer.
31. semiconductor structure as claimed in claim 27, wherein, the thickness of this first dielectric layer is in
Between.
32. semiconductor structure as claimed in claim 27, wherein, the thickness of this second dielectric layer is in
Between.
33. semiconductor structure as claimed in claim 27 wherein, also disposes many lower floor's data line segments on this substrate, and described lower floor data line segment one of them be electrically connected to this source area.
34. semiconductor structure as claimed in claim 33, wherein, the contact hole of the 3rd dielectric layer part exposes described lower floor data line segment, and electrically connects via many data connecting lines, and forms a continuous data wire.
35. semiconductor structure as claimed in claim 33, wherein, this scan line and this gate stack electrically connect.
36. semiconductor structure as claimed in claim 27, wherein, the material of this first conductive layer and this second conductive layer is selected from the group that is made up of the alloy of aluminium, tungsten, molybdenum and chromium and these several metals.
37. semiconductor structure as claimed in claim 27 wherein, also comprises a resilient coating, it is disposed between this substrate and this polysilicon layer.
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| CNB2007100887231A CN100470764C (en) | 2007-03-20 | 2007-03-20 | Two-dimensional display semiconductor structure and producing method thereof |
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| CN103996716B (en) | 2014-04-25 | 2017-02-15 | 京东方科技集团股份有限公司 | Preparation method of poly-silicon thin film transistor and thereof |
| CN106200167B (en) * | 2016-08-25 | 2019-06-11 | 武汉华星光电技术有限公司 | Array substrate and liquid crystal display |
| CN106783807A (en) * | 2017-01-23 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of array base palte and preparation method thereof |
| CN108257977B (en) | 2018-01-10 | 2021-01-01 | 京东方科技集团股份有限公司 | Display back plate and manufacturing method thereof, display panel and display device |
| CN108364871A (en) * | 2018-03-30 | 2018-08-03 | 武汉华星光电技术有限公司 | A kind of thin film transistor (TFT) and preparation method thereof |
| CN108565247B (en) * | 2018-04-19 | 2020-09-29 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS TFT substrate and LTPS TFT substrate |
| CN112419886B (en) * | 2019-08-20 | 2022-04-26 | 友达光电股份有限公司 | Pixel array substrate |
| EP3832744B1 (en) * | 2019-12-02 | 2022-09-07 | Plastic Logic HK Limited | Method of manufacturing structures on substrates using wet deposition |
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