KR100545028B1 - Thin film patterning method and manufacturing method of thin film transistor array substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor array substrate that can reduce the manufacturing cost by reducing the number of mask processes.

According to an embodiment of the present invention, a thin film patterning method includes loading a substrate on which an organic pattern is formed into a chamber, forming a thin film on the organic pattern within a temperature range of 20 ° C. to 100 ° C., and forming the organic pattern. And removing a portion of the thin film that is overlaid on the organic pattern.

A method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention includes forming a thin film transistor positioned on a gate line, a data line intersecting the gate line to be insulated from the gate line, and an intersection of the gate line and the data line. And depositing a passivation layer to cover the gate line, the data line, and the thin film transistor, forming a photoresist pattern on the passivation layer, and patterning the passivation layer using the photoresist pattern to form a passivation pattern. Loading a substrate in which the photoresist pattern remains on the protective pattern in a chamber, and forming a transparent electrode film on the entire surface of the substrate on which the photoresist pattern is formed at a temperature between 20 ° C. and 100 ° C .; And the photoresist pattern and a transparent layer overlapping the photoresist pattern And removing the electrode film to form a pixel electrode connected to the drain electrode.

Description

Thin film patterning method and manufacturing method of thin film transistor array substrate {THIN FILM PATTERNING METHOD AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE}

1 is a plan view showing a portion of a typical thin film transistor array substrate.

FIG. 2 is a cross-sectional view taken along line II ′ of the thin film transistor array substrate of FIG. 1. FIG.

3A through 3D are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along line II-II ′ of the thin film transistor array substrate of FIG. 4. FIG.

6 through 8C are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 5.

9 is a plan view showing a vacuum chamber of the sputter apparatus.

10 is a cross-sectional view showing a thin film formed on a photoresist pattern in a chamber.

11 is a cross-sectional view showing a deposition method of an H ₂ O amorphous ITO film.

<Explanation of symbols for main parts of the drawings>

2, 52: gate line 4, 54: data line

5, 55: pixel region 6, 56: thin film transistor

8, 58: gate electrode 10, 60: source electrode

12, 62: drain electrode 13: first contact hole

14, 64: pixel electrodes 15, 65: storage capacitor

16, 66: storage electrode 18, 68: gate pad

20, 70: gate pad lower electrode 21: second contact hole

22, 72: gate pad upper electrode 24, 74: data pad

26, 76: data pad lower electrode 27: third contact hole

28, 78: data pad upper electrode 30, 80: lower substrate

32, 82: gate insulating film 33: fourth contact hole

34, 84: active layer 36, 86: ohmic contact layer

38, 88: protective film

The present invention relates to a thin film transistor array substrate and a method of manufacturing the same, and more particularly, to a method of manufacturing a thin film transistor array substrate that can reduce the manufacturing cost by reducing the number of mask processes.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. The liquid crystal display drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display device includes a thin film transistor (TFT) array substrate (bottom plate) and a color filter array substrate (top plate) bonded together to face each other, a spacer for maintaining a constant cell gap between the two substrates, and a cell gap therebetween. It consists of filled liquid crystals.

The thin film transistor array substrate is composed of a plurality of signal wires and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The color filter array substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display, the thin film transistor array substrate includes a semiconductor process and requires a plurality of mask processes, thereby making the manufacturing process complicated. In order to solve this problem, researches for reducing the number of mask processes have been actively conducted. This research resulted in the development of a four-mask process that reduces one mask from the five-mask process, which is a standard mask process for thin film transistor array substrates.

1 and 2 illustrate a thin film transistor array substrate fabricated by a conventional four mask process.

1 and 2, the thin film transistor array substrate includes a gate line 2 and a data line 4 formed on the lower substrate 30 to intersect with the gate insulating layer 32 therebetween, and an intersection thereof. The thin film transistor 6 formed every time, the pixel electrode 14 formed in the pixel region provided in an intersecting structure, and the storage capacitor 15 formed in an overlapping portion of the gate line 2 and the storage electrode 16. And a gate pad 18 connected to the gate line 2 and a data pad 24 connected to the data line 4.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 6 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 14 in response to the gate signal of the gate line 2. For this purpose, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 further includes an active layer 34 overlapping with the gate electrode 8 and the gate insulating layer 32 therebetween to form a channel between the source electrode 10 and the drain electrode 12. do.

The active layer 34 is also formed to overlap the data line 4, the data pad lower electrode 26, and the storage electrode 16. The ohmic contact layer 36 for ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 26, and the storage electrode 16 is formed on the active layer 34. Additionally formed.

The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 13 penetrating the passivation layer 38 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 14 supplied with the pixel signal through the thin film transistor 6 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 15 includes a gate line 2 and a storage electrode 16 overlapping the gate line 2 with the gate insulating layer 32, the active layer 34, and the ohmic contact layer 36 interposed therebetween. And the pixel electrode 14 connected through the storage electrode 16 and the second contact hole 21 formed in the protective film 38. This storage capacitor 15 allows the pixel signal charged in the pixel electrode 14 to remain stable until the next pixel signal is charged.

The gate pad 18 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 18 has a gate pad lower electrode 20 through the gate pad lower electrode 20 extending from the gate line 2 and a third contact hole 27 penetrating through the gate insulating layer 32 and the passivation layer 38. And a gate pad upper electrode 22 connected to the 20.

The data pad 24 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 24 is connected to the data pad lower electrode 26 through the data pad lower electrode 26 extending from the data line 4 and the fourth contact hole 33 penetrating the passivation layer 38. It consists of a data pad upper electrode 28.

A method of manufacturing a thin film transistor array substrate having such a configuration will be described below with reference to FIGS. 3A to 3D, which show four mask processes step by step.

The four mask process may include a first mask process for forming gate patterns on the lower substrate 80, a semiconductor pattern including the gate insulating layer 32 and an active layer 34, and a source / drain pattern for forming a source / drain pattern. A second mask process, a third mask process for forming a protective film pattern, and a fourth mask process for forming transparent electrode patterns.

Referring to FIG. 3A, the first mask process first forms a first conductive pattern group on the lower substrate 30 including the gate line 2, the gate electrode 8, and the gate pad lower electrode 20. .

In detail, the gate metal layer is formed on the lower substrate 30 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a first conductive pattern group including the gate line 2, the gate electrode 8, and the gate pad lower electrode 20. In this case, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 32 is coated on the lower substrate 30 on which the first conductive pattern group is formed. The semiconductor pattern including the active layer 34 and the ohmic contact layer 36 on the gate insulating layer 32 using the second mask process, the data line 4, the source electrode 10, and the drain electrode 12. The second conductive pattern group including the data pad lower electrode 26 and the storage electrode 16 is formed.

In detail, the gate insulating layer 32, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower substrate 30 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. Is formed. Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 32. Molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), etc. are used as a source / drain metal. Subsequently, a photoresist pattern is formed on the source / drain metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than that of other source / drain pattern portions. Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the storage electrode 16 are formed. A second conductive pattern group including a is formed. Thereafter, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 36 and the active layer 34. After the ashing process removes the photoresist pattern having a relatively low height from the channel portion, the source / drain metal pattern of the channel portion and the ohmic contact layer 36 are etched by the dry etching process. Accordingly, the active layer 34 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12. Subsequently, the photoresist pattern remaining on the second conductive pattern group is removed by a stripping process.

Referring to FIG. 3C, a passivation layer 38 including first to fourth contact holes 13, 21, 27, and 33 on the gate insulating layer 32 on which the second conductive pattern group is formed using a third mask process. ) Is formed.

In detail, the protective film 38 is entirely formed on the gate insulating film 32 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the protective layer 38 is patterned by a photolithography process and an etching process using a third mask to form first to fourth contact holes 13, 21, 27, and 33. The first contact hole 13 penetrates the passivation layer 38 to expose the drain electrode 12, and the second contact hole 21 penetrates the passivation layer 38 to expose the storage electrode 16. The third contact hole 27 penetrates the passivation layer 38 and the gate insulating layer 32 to expose the gate pad lower electrode 20, and the fourth contact hole 33 penetrates the passivation layer 38 to lower the data pad. The electrode 26 is exposed. Here, when a metal having a large dry etch ratio such as molybdenum (Mo) is used as the source / drain metal, each of the first, second and fourth contact holes 13, 21, and 33 may have a drain electrode 12 and a storage electrode ( 16) and through the data pad lower electrode 26 to expose their sides. In this case, an inorganic insulating material such as the gate insulating film 32, an acrylic organic compound having a low dielectric constant, an organic insulating material such as BCB or PFCB, or the like is used as the material of the protective film 38.

Referring to FIG. 3D, a third conductive pattern group including the pixel electrode 14, the gate pad upper electrode 22, and the data pad upper electrode 28 is formed on the passivation layer 38 by using a fourth mask process. do.

In detail, the transparent conductive film is apply | coated on the protective film 38 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive film is etched through a photolithography process and an etching process using a fourth mask, thereby forming a third conductive pattern group including the pixel electrode 14, the gate pad upper electrode 22, and the data pad upper electrode 28. Is formed. The pixel electrode 14 is electrically connected to the drain electrode 12 through the first contact hole 13 and electrically connected to the storage electrode 16 through the second contact hole 21. The gate pad upper electrode 22 is electrically connected to the gate pad lower electrode 20 through the third contact hole 27. The data pad upper electrode 28 is electrically connected to the data pad lower electrode 26 through the fourth contact hole 33. In this case, materials of the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). ) Is used.

The four mask process reduces the number of manufacturing processes compared to the five mask process, and as a result, the manufacturing cost of the thin film transistor array substrate can be reduced. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for an apparatus and method for manufacturing a thin film transistor array substrate that can further simplify the manufacturing process and further reduce manufacturing costs.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor array substrate which can reduce the manufacturing cost by reducing the number of mask processes.

It is still another object of the present invention to provide a thin film patterning method capable of stably depositing an inorganic film on a substrate having an organic film during a mask process and patterning the inorganic film without a mask process.

In order to achieve the above object, a thin film patterning method according to an embodiment of the present invention comprises the steps of loading a substrate with an organic pattern formed in the chamber, and forming a thin film on the organic pattern within a temperature range of 20 ℃ to 100 ℃ And removing a portion of the thin film overlapping the organic pattern and the organic pattern.

In the thin film patterning method according to an embodiment of the present invention, the forming of the thin film on the organic pattern may include preheating the substrate on which the organic pattern is formed within the temperature range, and forming the thin film on the organic pattern of the preheated substrate. Depositing the thin film within a temperature range, and annealing the substrate on which the thin film is deposited within the temperature range.

In the thin film patterning method according to an embodiment of the present invention, the thin film is formed to have a thickness between 100 mW and 500 mW and an optimal thickness is between about 300 mW and 350 mW.

In the thin film patterning method according to an embodiment of the present invention, the forming of the thin film on the organic pattern may include forming a first thin film having a thickness of about 10 kW to about 200 kW on the power of 1 W / cm 2 to 3 W / cm 2 on the organic pattern. And forming a second thin film on the first thin film at an electric power between 1 W / cm 2 and 6 W / cm 2.

In the thin film patterning method according to an embodiment of the present invention, the forming of the thin film on the organic pattern may include forming the thin film on the organic pattern at a power between 1 W / cm 2 and 6 W / cm 2. do.

In the thin film patterning method according to an embodiment of the present invention, the chamber maintains a pressure between 10 ⁻³ mbar and 10 ⁻² mbar during the time that the thin film is deposited, and has a pressure of 10 ⁻⁶ mbar for the remaining time except the deposition time. It is characterized by maintaining the pressure.

In the thin film patterning method according to an embodiment of the present invention, the organic pattern is a photoresist pattern.

In the thin film patterning method according to an embodiment of the present invention, the thin film is at least one of a semiconductor film, a metal film, an insulating film, and a transparent electrode film.

In the thin film patterning method according to an embodiment of the present invention, the transparent electrode film may include at least one of an amorphous transparent electrode film and an H ₂ O amorphous silicon transparent electrode film.

In the thin film patterning method according to an embodiment of the present invention, the forming of the thin film on the organic pattern may include depositing an amorphous transparent electrode film on the organic pattern so as to have a thickness between 10 μm and 200 μm, and on the amorphous transparent electrode film. And depositing an H ₂ O amorphous transparent electrode film.

The thin film patterning method according to the embodiment of the present invention further comprises the step of periodically cleaning the deposition chamber using O ₂ + CF ₄ , CF ₄ , SF ₆ , SF ₆ + O ₂ gas. .

A method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention includes forming a thin film transistor positioned on a gate line, a data line intersecting the gate line to be insulated from the gate line, and an intersection of the gate line and the data line. And depositing a passivation layer to cover the gate line, the data line, and the thin film transistor, forming a photoresist pattern on the passivation layer, and patterning the passivation layer using the photoresist pattern to form a passivation pattern. Loading a substrate in which the photoresist pattern remains on the protective pattern in a chamber, and forming a transparent electrode film on the entire surface of the substrate on which the photoresist pattern is formed at a temperature between 20 ° C. and 100 ° C .; A photoresist pattern overlapping the photoresist pattern By removing the electrode film it is characterized in that it comprises a step of forming a pixel electrode connected to the drain electrode.

In the method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention, a gate line, a data line intersecting the gate line to be insulated from each other, and a thin film transistor positioned at an intersection of the gate line and the data line are formed on the substrate. The method may include forming a gate pattern including a gate line and a gate electrode of the thin film transistor on the substrate, a semiconductor pattern forming a channel portion of the thin film transistor on the gate pattern, and a source of the data line and the thin film transistor. And forming a data pattern including an electrode and a drain electrode.

In the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, the forming of the transparent electrode film may include forming the transparent electrode film to have a thickness between 100 mW and 500 mW and an optimal thickness between about 300 mW and 350 mW. do.

In the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, the forming of the transparent electrode film may include a first thickness having a thickness of between 10 W and 200 W at a power between 1 W / cm 2 and 3 W / cm 2 on the photoresist pattern. Forming a thin film and forming a second thin film on the first thin film at a power between 1 W / cm 2 and 6 W / cm 2.

In the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, the forming of the transparent electrode film may include forming an amorphous transparent electrode film on the photoresist pattern to have a thickness of between 10 mV and 200 mV, and 99.8 to 90 m. And forming an H ₂ O amorphous transparent electrode film on the amorphous transparent electrode film by using Ar, O ₂ , H ₂ O having a partial pressure ratio of about 0.1 to 5: 0.1 to 5. 5.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 9.

4 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 4 taken along a line II-II '.

4 and 5, the thin film transistor array substrate according to the present invention includes a gate line 52 and a data line 54 formed on the lower substrate 80 to intersect with the gate insulating layer 82 therebetween. And the thin film transistor 56 formed at the intersection of the gate line 52 and the data line 54, the pixel electrode 64 formed in the pixel region 55, the gate line 52 and the storage electrode 66. ), A storage capacitor 65 formed at an overlapping portion thereof, a gate pad 68 connected to the gate line 52, and a data pad 74 connected to the data line 54.

The gate line 52 for supplying the gate signal and the data line 54 for supplying the data signal have a cross structure to define the pixel region 55.

The thin film transistor 56 keeps the pixel signal of the data line 54 charged and held in the pixel electrode 64 in response to the gate signal of the gate line 52. To this end, the thin film transistor 56 includes a gate electrode 58 connected to the gate line 52, a source electrode 60 connected to the data line 54, and a drain electrode connected to the pixel electrode 64. 62). In addition, the thin film transistor 56 further includes an active layer 84 overlapping with the gate electrode 58 and the gate insulating layer 82 therebetween to form a channel between the source electrode 60 and the drain electrode 62. do.

The active layer 84 is formed to overlap the data line 54, the data pad lower electrode 76, and the storage electrode 66. On the active layer 84, an ohmic contact layer 86 for ohmic contact with the data line 54, the source electrode 60, the drain electrode 62, the data pad lower electrode 76, and the storage electrode 66 is added. Is formed.

The pixel electrode 64 is connected to the drain electrode 62 of the thin film transistor 56 exposed to the outside of the protective film 88 and is formed in the pixel region 55.

Accordingly, an electric field is formed between the pixel electrode 64 supplied with the pixel signal through the thin film transistor 56 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 55 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor 65 includes a gate line 52, a storage electrode 66 overlapping the gate line 52, a gate insulating layer 82, an active layer 84, and an ohmic contact layer 86 therebetween, The pixel electrode 64 is connected to the storage electrode 66. This storage capacitor 65 allows the pixel signal charged in the pixel electrode 64 to remain stable until the next pixel signal is charged.

The gate pad 68 is connected to an output terminal of a gate driver (not shown) to supply a gate signal to the gate line 52. The gate pad 68 may pass through the gate pad lower electrode 70 extending from the gate line 52, and pass through the gate insulating layer 82 and the passivation layer 88 to be connected to the gate pad lower electrode 70. It consists of an electrode 72.

The data pad 74 is connected to an output terminal of a data driver (not shown) to supply a data signal to the data line 54. The data pad 74 includes a data pad lower electrode 76 extending from the data line 54 and a data pad upper electrode 78 penetrating the passivation layer 88 and connected to the data pad lower electrode 76. do.

The gate insulating layer 82 and the passivation layer 88 are formed in a region where the pixel electrode 74, the gate pad upper electrode 72, and the data pad upper electrode 78 are not formed.

The thin film transistor array substrate having such a configuration is manufactured in a three mask process. In this case, the three mask process may include a first mask process for forming gate patterns, a second mask process for forming a semiconductor pattern including an active layer, and source / drain patterns, a gate insulating layer 82, a protective film 88, and the like. And a third mask process for forming the transparent electrode patterns.

Referring to FIG. 6, in the first mask process, a gate metal layer is formed on the lower substrate 80 through a deposition method such as a sputtering method. After the gate metal layer is formed, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate line 52, a gate electrode 58, and a gate pad lower electrode 70. At this time, Cr, Cr / Al, Cr / Al (Nd), Al (Nd), Cu, MoW, Mo / Al, Mo / Al (Nd) or the like is used as the gate metal in a single layer or a double layer structure.

Referring to FIG. 7, in the second mask process, the gate insulating layer 82, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are deposited on the lower substrate 80 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. This is applied all over the surface sequentially. Subsequently, a photoresist pattern is formed by a photolithography process and an etching process using a second mask. In this case, the photoresist pattern of the channel portion has a lower height than the source / drain pattern portion by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor as the second mask. After the photoresist pattern is formed, the source / drain metal layer is patterned by a wet etching process using the photoresist pattern to form the data line 54, the source electrode 60, the drain electrode 62 integrated with the source electrode 60, and Storage electrodes 66 are formed. Thereafter, the n + amorphous silicon layer and the amorphous silicon layer are simultaneously patterned by a dry etching process using the same photoresist pattern to form the ohmic contact layer 86 and the active layer 84. In addition, after the photoresist pattern having a relatively low height in the channel portion is removed by an ashing process, the source / drain pattern and the ohmic contact layer 86 of the channel portion are etched by a dry etching process. Accordingly, the active layer 84 of the channel portion is exposed to separate the source electrode 60 and the drain electrode 62. The stripping process then removes the photoresist pattern remaining on the source / drain electrodes.

In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the gate insulating layer 82, and molybdenum (Mo), titanium, tantalum, and molybdenum alloy (Mo) may be used as the source / drain metal. alloy) and the like.

8A to 8C are views continuously showing the third mask process.

8A to 8C, the third mask process may first use an inorganic insulating material such as SiNx or SiOx or an acrylic having a low dielectric constant using a deposition method such as sputtering on the gate insulating layer 82 on which source / drain patterns are formed. A protective film 88 using an organic insulating material such as an acryl) -based organic compound, BCB, or PFCB is deposited on the entire surface, and a photoresist is entirely coated on the protective film 88. Subsequently, a photoresist pattern 90 is formed by a photolithography process using a third mask, and the passivation layer 88 and the gate insulating layer 82 are patterned using the photoresist pattern 90 as a mask to form a transparent electrode pattern. The gate insulating film 82 and the protective film 88 are formed in the remaining regions except for the region to be formed. Thereafter, the transparent electrode material 64a is entirely deposited on the lower substrate 80 on which the photoresist pattern 90 remains, by a deposition method such as sputtering, as shown in FIG. 8B. The photoresist pattern 90 is removed by a strip process using a lift-off process on the thin film transistor array substrate on which the transparent electrode material 64a is entirely deposited. At this time, the transparent electrode material 64a deposited on the photoresist pattern 90 is removed while the photoresist pattern 90 is separated, so that the gate pad upper electrode 72 and the pixel electrode (as shown in FIG. 8C). 74) and a transparent electrode pattern including the data pad lower electrode 76 is formed. The gate pad upper electrode 72 is formed to cover the gate pad lower electrode 70, and the pixel electrode 64 is the drain electrode 62 of the thin film transistor 56 and the storage electrode 66 of the storage capacitor 65. Is electrically connected to the data pad upper electrode 78, and is electrically connected to the data pad lower electrode 76.

In this case, as the transparent electrode material 64a, indium tin oxide (ITO), H ₂ O amorphous ITO (H ₂ O Amorphous ITO), tin oxide (Tin Oxide: TO), and indium zinc oxide (Indium Zinc Oxide: IZO).

Meanwhile, in order to form the transparent electrode pattern by the lift-off process, the transparent electrode material 64a must be deposited on the substrate on which the photoresist pattern 90 remains. To this end, the substrate on which the photoresist pattern 90 is formed is first inserted into a preheating chamber and then the substrate is preheated to a temperature between 100 ° C and 250 ° C. After inserting the preheated substrate into the process chamber, depositing the transparent electrode material 64a on the substrate at a temperature between 100 ° C. and 250 ° C., and then depositing the substrate on which the transparent electrode material 64a was deposited into the preheat chamber. To be annealed at a temperature between 100 ° C and 300 ° C.

However, as the temperature in the chamber is relatively high, the moisture contained in the photoresist pattern 90 formed on the substrate evaporates, thereby changing the characteristics of the photoresist pattern 90. As a result, during the strip process for removing the photoresist pattern 90, the photoresist pattern 90 does not react with the stripping liquid so that the photoresist pattern 90 and the transparent electrode are deposited on the photoresist pattern 90. The material 64a is not stripped properly. In addition, when the thin film formed on the substrate is deposited to a thickness of about 500 to 1000 Å, the thin film on the photoresist pattern 90 may not be removed smoothly during the lift-off process.

Accordingly, in order to increase the efficiency of the lift-off process, the transparent electrode material 64a must be deposited on the photoresist pattern 90 using the following method.

The substrate on which the photoresist pattern 90 is formed is preheated to a temperature between 20 ° C. and 100 ° C. in the preheat chamber 102 shown in FIG. 9, and the preheated substrate is 20 ° C. in any of the process chambers 108, 110, 112. The thin film is deposited at a temperature between about 100 ° C. As the thin film, an inorganic film such as, for example, a metal film, an insulating film, or a transparent electrode material is used. The substrate on which the thin film is deposited is annealed (or cooled) to a temperature between 20 ° C and 100 ° C in an annealing chamber (or cooling chamber) not shown.

In more detail, the photoresist due to moisture evaporation of the photoresist pattern 90 when the thin film 92 is deposited on the photoresist pattern 90 formed on the substrate in the process chambers 108, 110, and 112 as shown in FIG. 10. In order to reduce the denaturation of the pattern 90, the internal temperature of the process chambers 108, 110 and 112 should be maintained in the temperature range between 20 ° C and 100 ° C. In addition, in order to minimize the loss of the photoresist pattern 90 by the plasma, power between 1W / cm 2 and 6W / cm 2 should be maintained. After the thin film 92 is deposited, it is used in a deposition process using a gas such as O ₂ + CF ₄ , CF ₄ , SF ₆ , SF ₆ + O ₂ to minimize contamination in the chamber by the photoresist pattern 90. In order to maintain the same quality of the thin film 92, the basic pressure in the chamber is maintained at about 10 ⁻⁶ mbar, and the pressure during the deposition process is maintained between 10 ⁻³ mbar and 10 ⁻² mbar. At this time, the thickness of the thin film 92 is between 100 kPa and 500 kPa in order to minimize losses such as water evaporation of the photoresist pattern 90 and to efficiently lift-off processes. Here, the optimum thickness of the thin film is about 300 kPa to 350 kPa. In addition, the thickness between the initial 10 kPa and 200 kPa of the thin film 92 is deposited at a power between 1 W / cm 2 and 3 W / cm 2, and the thickness between 300 kPa and 490 kW is deposited at a power between 1 W / cm 2 and 6 W / cm 2 Perform the step process. When the H ₂ O amorphous ITO is used as the transparent electrode material 64a among the thin film 92 deposited on the photoresist pattern 90, the resistance value when the gas partial pressure ratio of O ₂ and H ₂ O is less than 0.1 or exceeds 5 Since this increases and cannot be used as the transparent electrode material 64a, the gas partial pressure ratio of Ar: O ₂ : H ₂ O should be maintained at 99.8 to 90: 0.1 to 5: 0.1 to 5. Also, as shown in FIG. 11, to prevent moisture absorption of the photoresist pattern 90 by H ₂ O when depositing H ₂ O amorphous ITO with the transparent electrode material 64a on the photoresist pattern 90. A two-step process of depositing an amorphous ITO film 94 with a thickness between 10 kPa and 200 kPa and depositing an amorphous ITO film 96 containing about 0.1% to 5% H ₂ O at a thickness between 300 kPa and 490 kPa. It must be done.

By using the process conditions described above, the processes shown in FIGS. 6 to 8 may be sequentially performed to manufacture a more efficient thin film transistor array substrate.

In the above manufacturing method of the thin film transistor array substrate, the lift-off process is applied only to the transparent electrode, but it should be noted that the lift-off process may be applied to the thin films such as the metal layer and the gate insulating film.

As described above, the thin film transistor manufacturing method according to the embodiment of the present invention can reduce the manufacturing cost by employing three masks to further simplify the substrate structure and manufacturing process. In addition, the yield of the inorganic film can be stably deposited on the substrate on which the organic film is present.

It will be appreciated by those skilled in the art that various changes and modifications can be made in the present invention without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the scope of the claims.

Claims (17)

Loading the substrate with the organic pattern into the chamber, Forming a thin film on the organic pattern within a temperature range between 20 ° C. and 100 ° C., And removing the organic pattern and the thin film overlapping the organic pattern. The method of claim 1, Forming a thin film on the organic pattern, Preheating the substrate on which the organic pattern is formed within the temperature range; Depositing the thin film within the temperature range on the organic pattern of the preheated substrate; And annealing the substrate on which the thin film is deposited within the temperature range. The method of claim 1, Wherein said thin film is formed to have a thickness between 100 kV and 500 kV and an optimal thickness is between about 300 kV and 350 kV. The method of claim 1, Forming a thin film on the organic pattern, Forming a first thin film on the organic pattern having a thickness between 10 kW and 200 kW at a power between 1 W / cm 2 and 3 W / cm 2; And forming a second thin film on the first thin film at a power between 1W / cm 2 and 6W / cm 2. The method of claim 1, Forming a thin film on the organic pattern, And forming a thin film on the organic pattern at an electric power between 1 W / cm 2 and 6 W / cm 2. The method of claim 1, Wherein the chamber maintains a pressure between 10 ^-3 and 10 ^-2 mbar during the time the thin film is deposited and maintains a pressure of 10 ^-6 mbar for the remaining time except for the deposition time. The method of claim 1, The organic pattern is a thin film patterning method, characterized in that the photoresist pattern. The method of claim 1, The thin film is a thin film patterning method, characterized in that at least one of a semiconductor film, a metal film, an insulating film and a transparent electrode film. The method of claim 8, The transparent electrode film may include at least one of an amorphous transparent electrode film and an H ₂ O amorphous silicon transparent electrode film. The method of claim 9, Forming a thin film on the organic pattern, Depositing an amorphous transparent electrode film on the organic pattern so as to have a thickness between 10 μs and 200 μs; And depositing a H ₂ O amorphous transparent electrode film on the amorphous transparent electrode film. The method of claim 10, Forming a thin film on the organic pattern, 99.8 to 90: 0.1 to 5: characterized in that by using the Ar, O _2, H ₂ O with a partial pressure ratio of 0.1 to 5 comprising the step of depositing the H ₂ O amorphous transparent electrode film on the amorphous transparent electrode film Thin film patterning method. The method of claim 1, The chamber further comprises the step of periodically cleaning using O ₂ + CF ₄ , CF ₄ , SF ₆ , SF ₆ + O ₂ gas. Forming a thin film transistor positioned on an intersection of the gate line, the data line crossing the gate line insulated from the gate line, and the gate line and the data line; Depositing a passivation layer to cover the gate line, the data line, and the thin film transistor; Forming a photoresist pattern on the protective film; Patterning the protective layer using the photoresist pattern to form a protective pattern; Loading a substrate in which the photoresist pattern remains on the protective pattern into a chamber; Forming a transparent electrode film on the entire surface of the substrate on which the photoresist pattern is formed at a temperature between 20 ° C. and 100 ° C .; And removing the photoresist pattern and a transparent electrode film overlapping the photoresist pattern to form a pixel electrode connected to the drain electrode. The method of claim 13, Forming a thin film transistor positioned on an intersection of the gate line, the data line crossing the gate line insulated from the gate line, and the gate line and the data line on the substrate, Forming a gate pattern including a gate line and a gate electrode of the thin film transistor on the substrate; Manufacturing a thin film transistor array substrate on the gate pattern, the semiconductor pattern forming a channel portion of the thin film transistor and a data pattern including the data line, a source electrode and a drain electrode of the thin film transistor. Way. The method of claim 13, Forming the transparent electrode film, Wherein said transparent electrode film is formed to have a thickness between 100 kV and 500 kV and an optimal thickness is between about 300 kV and 350 kV. The method of claim 15, Forming the transparent electrode film, Forming a first thin film on the photoresist pattern having a thickness between 10 kW and 200 kW at a power between 1 W / cm 2 and 3 W / cm 2; Forming a second thin film on the first thin film at a power between 1 W / cm 2 and 6 W / cm 2. The method of claim 16, Forming the transparent electrode film, Forming an amorphous transparent electrode film on the photoresist pattern so as to have a thickness between 10 μs and 200 μs; 99.8 to 90: 0.1 to 5: characterized in that by using the Ar, O _2, H ₂ O with a partial pressure ratio of 0.1 to 5 comprising the step of forming H ₂ O amorphous transparent electrode film on the amorphous transparent electrode film A method of manufacturing a thin film transistor array substrate.

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