KR101128100B1 - Thin Film Transistor And Fabricating Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor capable of improving the interfacial characteristics of an LDD region and a source drain region constituting a semiconductor layer, and to lowering manufacturing time and cost.

To this end, a semiconductor layer including a source drain region formed on an upper portion of the substrate, an LDD region formed by doping at a lower concentration than the source drain region inside the source drain region, and a channel region formed inside the LDD region; A first insulating layer formed over the layer, a second insulating layer formed over the edge of the first insulating layer, and a gate electrode formed over the first insulating layer and the second insulating layer. Thin film transistors are disclosed.

Thin Film Transistor, LDD, Ion Doping, Self Align

Description

Thin Film Transistor and Fabrication Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a thin film transistor capable of improving the interfacial characteristics of an LDD region and a source drain region constituting a semiconductor layer and reducing manufacturing time and cost. It is about.

Recently, as the use of displays such as liquid crystal displays (LCDs) and active matrix organic light emitting displays (AMOLEDs) increases, the use of thin film transistors applied thereto Also increasing.

Such thin film transistors are typically formed on top of glass, and are formed by depositing silicon crystals on the glass to form a semiconductor layer. Hydrogenated amorphous silicon or polycrystalline silicon is used as the silicon crystal.

Dual hydrogenated amorphous silicon has been widely used because it can be made in a low temperature process and a low-cost insulating substrate can be used. However, because hydrogenated amorphous silicon has irregular atomic arrangements, weak bonds or dangling bonds exist, and the structure of the material changes to quasi-steady state upon light irradiation or electric field application. As a result, problems have arisen in terms of stability. In addition, the electrical characteristics such as mobility (Mobility) is not good, there was a point that it is difficult to be used as a driving circuit used in electronic products.

On the other hand, polycrystalline silicon has advantages of superior current driving capability and faster operating speed than amorphous silicon. Therefore, crystalline silicon has recently been widely used to form pixel switching elements and drive circuits for electronic products.

However, in the thin film transistor using polycrystalline silicon, since an ion implantation process for forming a source drain region is generally performed using a gate electrode as a self-aligning mask, the source drain region is located adjacent to the channel region. do. In this structure, a vertical electric field is generated in the direction of the gate electrode from the source drain region in the off state in which the voltage applied to the source drain region is higher than the voltage applied to the gate electrode. Carriers are excited and dislodged to generate a leakage current. In addition, this leakage current becomes a problem because it causes difficulty in on / off switching of the driving device.

On the other hand, in order to reduce the leakage current, various structures for dispersing the drain electric field have been proposed. Among these, LDD (Light Doped Drain) structure is a structure that forms a lightly doped region between the source drain region and the channel region, which is a heavily doped region, and prevents the flow of leakage current. It is widely used because it can act as a kind of resistance and can reduce leakage current.

However, the LDD structure is subjected to a two-step ion doping process of a high concentration impurity ion doping process for forming a source drain region and a low concentration ion doping process for forming an LDD region. In addition, since different photo masks are used in each ion doping process, misalignment may occur between these masks, thereby degrading the characteristics of the thin film transistor and increasing the process time and cost. There is an increasing problem.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems, and an object of the present invention is to improve the interfacial characteristics of the LDD region and the source drain region constituting the semiconductor layer, and to reduce the manufacturing time and cost, and the fabrication thereof. In providing a method.

In order to achieve the above object, a thin film transistor according to the present invention includes a source drain region formed on an upper portion of a substrate, an LDD region formed by doping at a lower concentration than the source drain region inside the source drain region, and an inside of the LDD region. A semiconductor layer including a formed channel region; A first insulating layer formed on the semiconductor layer; A second insulating layer formed on an edge of the first insulating layer; And a gate electrode formed on the first insulating layer and the second insulating layer.

The second insulating layer may be formed to correspond to the LDD region of the semiconductor layer.

The gate electrode may be formed while making a step in contact with the first insulating layer in a region corresponding to the channel region of the semiconductor layer and in contact with the second insulating layer in a region corresponding to the LDD region.

In addition, a third insulating layer having the same planar shape as the second insulating layer may be further formed between the second insulating layer and the gate electrode.

The gate electrode may be formed while making a step in contact with the first insulating layer in a region corresponding to the channel region of the semiconductor layer and in contact with the third insulating layer in a region corresponding to the LDD region.

The second insulating layer may be formed to cover an upper portion of the first insulating layer, and may be formed with a step so that a height of a region corresponding to the LDD region of the semiconductor layer is higher than a height corresponding to the channel layer. Can be.

In addition, the gate electrode may be formed along the step of the second insulating layer on the second insulating layer.

In addition, a third insulating layer formed along the edge of the second insulating layer may be further formed on the second insulating layer so that the height of the edge is higher than the height of the center.

The gate electrode may be formed such that a region corresponding to the channel layer of the semiconductor layer contacts the second insulating layer, and a region corresponding to the LDD region contacts the third insulating layer to form a step.

In addition, the method for manufacturing a thin film transistor according to the present invention to achieve the above object is a silicon thin film forming step of forming a silicon thin film on top of the substrate; Forming a first insulating film on the silicon thin film; A first etching step of etching the silicon thin film to form a semiconductor layer; A second insulating film forming step of forming a second insulating film on the semiconductor layer and the first insulating film; A second etching step of etching a center region of the second insulating film; Forming a gate material layer on the first insulating film and the second insulating film; A third etching step of forming a first insulating layer, a second insulating layer, and a gate electrode to etch the first insulating layer, the second insulating layer, and the gate material layer to expose edge regions of the semiconductor layer; And implanting impurities into an edge region of the semiconductor layer to form an LDD region in the source drain region and the source drain region.

Here, after the ion implantation step, a heat treatment step of diffusing the impurities to the LDD region by performing a heat treatment on the semiconductor layer may be further performed.

The third insulating film forming step of forming a third insulating film on the second insulating film may be further performed between the second insulating film forming step and the second etching step.

The second etching step may be to etch the central region of the second insulating layer to expose the central region of the first insulating layer.

In addition, the second etching step may be to etch the second insulating film so that the thickness of the edge region is formed thicker than the central region of the second insulating layer.

The third etching step may be performed such that the gate electrode remains on the second insulating layer.

In addition, the method for manufacturing a thin film transistor according to the present invention to achieve the above object is a silicon thin film forming step of forming a silicon thin film on top of the substrate; Forming a first insulating film on the silicon thin film; A second insulating film forming step of forming a second insulating film on the first insulating film; A first etching step of etching a central region of the second insulating film; Forming a gate material layer on the first insulating film and the second insulating film; Etching the first insulating film, the second insulating film, and the gate material layer to form a first insulating layer, a second insulating layer, and a gate electrode, and exposing an edge region of the silicon thin film; Implanting an impurity into an edge region of the silicon thin film to form a source drain region and an LDD region located inside the source drain region; And a third etching step of etching the silicon thin film to form a semiconductor layer.

Here, a heat treatment step may be further performed between the ion implantation step and the third etching step to heat-treat the silicon thin film to diffuse the impurities into the LDD region.

In addition, a third insulating film forming step of forming a third insulating film on the second insulating film may be further performed between the second insulating film forming step and the first etching step.

The first etching step may be to etch the central region of the second insulating layer to expose the central region of the first insulating layer.

In addition, the first etching step may be to etch the second insulating film so that the thickness of the edge region is formed thicker than the central region of the second insulating layer.

In addition, the second etching step may be performed such that the gate electrode remains on the second insulating layer.

As described above, the thin film transistor according to the present invention can improve the interfacial properties by forming an insulating film on the upper portion of the semiconductor layer, thereby reducing air exposure.

In the thin film transistor according to the present invention as described above, the source drain region and the LDD region of the semiconductor layer are formed in a single impurity implantation step using the gate electrode as a self-aligned structure, and thus the misalignment of the mask Mis-Align) can be eliminated and manufacturing time and cost can be reduced.

In addition, as described above, the thin film transistor according to the present invention further reduces the influence of the electrical bias by forming a second insulating film in addition to the first insulating film on the upper portion corresponding to the LDD region, thereby reducing the leakage current efficiently.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention.

Hereinafter, the configuration of the thin film transistor 100 according to the exemplary embodiment of the present invention will be described.

1 is a cross-sectional view illustrating a thin film transistor 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a thin film transistor 100 according to an exemplary embodiment of the present invention may include a substrate 110, a semiconductor layer 120 formed on the substrate 110, and an upper portion of the semiconductor layer 120. A gate formed on the first insulating layer 130, the second insulating layer 140 formed on the edge of the first insulating layer 130, the first insulating layer 130 and the second insulating layer 140. Electrode 160.

The substrate 110 is made of glass used in a conventional thin film transistor. That is, the substrate 110 may be formed of a glass substrate, a plastic substrate, a metal substrate, a polymer substrate, and an equivalent thereof, but the present invention is not limited thereto. In addition, although not separately illustrated, the substrate 110 may be formed of an insulating film (SiO 2, SiN x, SiO x N y, a high dielectric film, or an organic material) in some cases.

The semiconductor layer 120 is formed on the substrate 110. The semiconductor layer 120 may also include a buffer layer between the substrate 110 and the semiconductor layer 120. The semiconductor layer 120 may be immediately formed thereon immediately after it is formed in a manufacturing process. Since the first insulating layer 130 is formed, the exposure time to the air can be reduced. Therefore, the semiconductor layer 120 may have improved interface characteristics compared to the existing structure.

The semiconductor layer 120 includes a channel region 121, a source drain region 122 formed at an edge of the channel 121, and an LDD region 123 formed inside the source drain region 122. .

The channel region 121 is formed on the substrate 110 and may be formed of polycrystalline silicon. The polycrystalline silicon is typically formed amorphous silicon, and then subjected to Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC) or Metal Induced Lateral Crystallization (MILC), Solidification Phase Crystallization (SPC), etc. It can be formed by crystallization using and patterning it. In addition, a micro-, nano-crystalline silicon layer deposited by chemical vapor deposition (CVD) may be used as the active layer thin film.

The source drain region 122 is formed at an edge of the channel region 121. The source drain region 122 is formed by doping impurity ions in the channel region 121. The impurity ions doped in the source drain region 122 may be boron, phosphorus, or arsenic. In addition, a method such as ion showering or ion implantation may be used as a method of doping the impurity ions.

The lightly doped drain (LDD) region 123 is located inside the source drain region 122. The LDD region 123 is doped with impurities having a lower concentration than that of the source drain region 122. The LDD region 123 disperses a vertical electric field generated when the voltage applied to the source drain region 122 is higher than the voltage applied to the gate 121, thereby causing leakage current. Reduce In addition, as will be described later, the LDD region 123 is formed through a single impurity ion implantation process for manufacturing the source drain region 122, thereby lowering the manufacturing cost.

The first insulating layer 130 is formed on the semiconductor layer 120. The first insulating layer 130 serves as a gate insulating layer to insulate the source drain region 122 and the LDD region 123 of the semiconductor layer 120 from the gate electrode 160. The first insulating layer 130 may be formed of various kinds of insulating films (SiO ₂ , SiNx, SiOxNy, a high dielectric film or an organic material), but a silicon oxide film (SiO ₂ having good interface characteristics with the semiconductor layer 120). It is preferably formed of).

The second insulating layer 140 is formed on the first insulating layer 130. The second insulating layer 140 is formed on the edge region of the first insulating layer 130. Therefore, an upper surface of the central region of the first insulating layer 130 is exposed. In addition, the second insulating layer 140 increases the height of the edge region of the first insulating layer 130. In this case, an edge region of the first insulating layer 130 is a region corresponding to the LDD region 123 of the semiconductor layer 120. The first insulating layer 130 and the second insulating layer 140 form a path from the LDD region 123 of the semiconductor layer 120 to the gate electrode 160. Accordingly, the second insulating layer 140 increases the path of the LDD region 123 together with the first insulating layer 130, thereby reducing the influence of electrical bias, thereby reducing leakage current. . In this case, only the first insulating layer 130 is provided between the channel region 121 and the gate electrode 160 of the semiconductor layer 120. The second insulating layer 140 may also be formed of various kinds of insulating films (SiO ₂ , SiNx, SiOxNy, a high dielectric film or an organic material), but silicon having good bonding properties with the first insulating layer 130. It is preferably formed of a nitride film (SiOx).

The gate electrode 160 is formed on the first insulating layer 130 and the second insulating layer 140. The gate electrode 160 may be formed using metal or polysilicon. The gate electrode 160 is in contact with the first insulating layer 130 above the central region of the first insulating layer 130, and the second insulating layer (above the edge region of the first insulating layer 130). 140). That is, the gate electrode 160 is formed to have a step in the center region and the edge region according to the shape of the first insulating layer 130 and the second insulating layer 140. In addition, the gate electrode 160 forms a self-aligned structure, as will be described later, to form impurities for forming the source drain region 122 and the LDD region 123 of the semiconductor layer 120. It can be used as a barrier during ion implantation. Therefore, since the impurity ion implantation process for forming the semiconductor layer 120 needs to be performed only once due to the structure of the gate electrode 160, the misalignment of the mask when forming the LDD region 123 may be achieved. Mis-Aling) is eliminated, and the manufacturing process time and cost of the thin film transistor 100 according to the embodiment of the present invention can be reduced.

As described above, the thin film transistor 100 according to the exemplary embodiment of the present invention may improve the interfacial characteristics by forming the first insulating layer 130 on the semiconductor layer 120 and reducing air exposure. By using the gate electrode 160 as a self-aligned structure, the source drain region 122 and the LDD region 123 of the semiconductor layer 120 are formed in one impurity implantation process, thereby preventing misalignment. And the manufacturing process and time can be reduced. In addition, the thin film transistor 100 according to an embodiment of the present invention forms a second insulating film 140 in addition to the first insulating film 130 on the upper portion corresponding to the LDD region to reduce the influence of the electrical bias, thereby reducing the leakage current. Can be reduced efficiently.

Hereinafter, the configuration of the thin film transistor 200 according to another embodiment of the present invention will be described.

2 is a cross-sectional view illustrating a thin film transistor 200 according to another exemplary embodiment of the present invention. Parts having the same configuration and operation as those of the above-described embodiment are denoted by the same reference numerals, and will be described below with reference to differences from the previous embodiment.

As shown in FIG. 2, the thin film transistor 200 according to another embodiment of the present invention may include a substrate 110, a semiconductor layer 120, a first insulating layer 130, and a first insulating layer 130. The second insulating layer 240 is formed on the upper portion, and the gate electrode 260 is formed on the second insulating layer 240.

The second insulating layer 240 is formed on the first insulating layer 130. The second insulating layer 240 is formed while covering the entire upper surface of the first insulating layer 130. In addition, the second insulating layer 240 is formed with a step so that the height in the edge region is higher than that in the central region. Therefore, the second insulating layer 240 may reduce the leakage current by increasing the height of the edge region corresponding to the LDD region 123 of the semiconductor layer 120.

The gate electrode 260 is formed on the second insulating layer 240. The gate electrode 260 is formed with a step on a lower surface corresponding to the shape of the second insulating layer 240. Accordingly, since the center region of the gate electrode 260 is formed to be drawn into the second insulating layer 240, the channel region 121 of the semiconductor layer 120 may extend from the channel region 121 to the gate electrode 260. The distance from the LDD region 123 to the gate electrode 260 is greater than the distance of. Therefore, similarly to the embodiment described above, the leakage current can be efficiently reduced with little effect on the formation of the channel.

As described above, the thin film transistor 200 according to another exemplary embodiment of the present invention forms the second insulating layer 240 to have a step, from the LDD region 123 to the gate electrode 260 of the semiconductor layer 120. By increasing the distance of, the leakage current can be efficiently reduced.

Hereinafter, the configuration of the thin film transistor 300 according to another embodiment of the present invention will be described.

3 is a cross-sectional view illustrating a thin film transistor 300 according to another exemplary embodiment of the present invention. Parts having the same configuration and operation as those of the above-described embodiment are denoted by the same reference numerals, and will be described below with reference to differences from the previous embodiment.

As shown in FIG. 3, the thin film transistor 300 according to another embodiment of the present invention may include a substrate 110, a semiconductor layer 120, a first insulating layer 130, a second insulating layer 140, And a third insulating layer 350 formed on the second insulating layer 140 and a gate electrode 360 formed on the first to third insulating layers 130 to 350.

The third insulating layer 350 is formed on the second insulating layer 140. The third insulating layer 350 is formed to have the same planar shape as the second insulating layer 140. That is, the third insulating layer 350 is formed on the edge region of the first insulating layer 130 to correspond to the LDD region 123 of the semiconductor layer 120. The distance from the channel region 121 of the semiconductor layer 120 to the gate electrode 360 by the third insulating layer 350 remains the same as before, but the gate electrode 360 from the LDD region 123 is maintained. You can increase the distance to.

The gate electrode 360 is formed on the first to third insulating layers 130 to 350. The gate electrode 360 is formed with a step corresponding to the height of the second insulating layer 140 and the third insulating layer 350. As a result, the gate electrode 360 is formed to be in contact with the first insulating layer 130 at an upper portion of the center region of the first insulating layer 130 and to be in contact with the third insulating layer 350 at an edge region. do. Accordingly, the gate electrode 360 maintains the same distance from the top surface of the channel region 121 of the semiconductor layer 120 as the existing structure, but from the top surface of the LDD region 123 compared to the existing structure. Form a spaced structure.

As described above, the thin film transistor 200 according to another embodiment of the present invention forms the second insulating layer 140 and the third insulating layer 350 on the edge of the first insulating layer 130, LDD By increasing the distance from the region 123 to the gate electrode 360, the leakage current can be efficiently reduced.

Hereinafter, the configuration of the thin film transistor 400 according to another embodiment of the present invention will be described.

4 is a cross-sectional view illustrating a thin film transistor 400 according to another exemplary embodiment of the present invention. Parts having the same configuration and operation as those of the above-described embodiment are denoted by the same reference numerals, and will be described below with reference to differences from the previous embodiment.

As shown in FIG. 4, the thin film transistor 400 according to another exemplary embodiment of the present invention may include a substrate 110, a semiconductor layer 120, a first insulating layer 130, and the first insulating layer 130. Of the second insulating layer 440 formed on the second insulating layer 440, the third insulating layer 450 formed on the second insulating layer 440, the second insulating layer 440, and the third insulating layer 450. And a gate electrode 460 formed thereon.

The second insulating layer 440 is formed on the first insulating layer 130. The second insulating layer 440 is formed to surround the entire upper surface of the first insulating layer 130. The second insulating layer 440 is formed with a step so that the height of the edge region corresponding to the LDD region 123 is higher than the height of the central region corresponding to the channel region 121 of the semiconductor layer 120. do.

The third insulating layer 450 is formed on the second insulating layer 440. The upper portion of the edge region of the second insulating layer 440 of the third insulating layer 450 is formed. The third insulating layer 450 increases the distance from the top surface of the LDD region 123 to the gate electrode 460.

The gate electrode 460 is formed on the second insulating layer 440 and the third insulating layer 450. The gate electrode 460 is in contact with the second insulating layer 440 in the center region and in contact with the third insulating layer 450 in the edge region. In addition, since the second insulating layer 440 is formed to have a step height so that the height of the edge area is higher than that of the center area, the height of the edge area of the gate electrode 460 is equal to the step of the second insulating layer 440. The height of the third insulating layer 450 is formed to be higher by the combined height. Accordingly, the gate electrode 460 may increase the distance from the LDD region 123 while maintaining the same distance from the channel region 121 as the existing structure.

As described above, the thin film transistor 400 according to another embodiment of the present invention forms the edge region of the second insulating layer 440 higher than the center region, and is formed on the upper edge region of the second insulating layer 440. By forming the third insulating layer 450, the distance from the LDD region 123 of the semiconductor layer 120 to the gate electrode 460 can be increased to efficiently reduce the leakage current.

Hereinafter, a method of manufacturing the thin film transistor 100 according to the exemplary embodiment of the present invention will be described.

5 is a flowchart illustrating a method of manufacturing the thin film transistor 100 according to the exemplary embodiment of the present invention. 6A to 6L are cross-sectional views illustrating a method of manufacturing the thin film transistor 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in the thin film transistor 100 according to the exemplary embodiment of the present invention, a silicon thin film forming step S1, a first insulating film forming step S2, a first etching step S4, and a second insulating film forming step (S5), a second etching step (S7), a gate material layer forming step (S8), a third etching step (S10), an ion implantation step (S11). In addition, a first photoresist pattern forming step S3 may be further performed between the first insulating film forming step S2 and the first etching step S4, and the second insulating film forming step S5 and the second etching may be performed. A second photoresist pattern forming step S6 may be further performed between the steps S7 and a third photoresist pattern forming step between the gate material layer forming step S8 and the third etching step S10. S9 may be further formed, and after the ion implantation step S11, a heat treatment step S12 may be further performed. Hereinafter, each step of FIG. 5 will be described with reference to FIGS. 6A to 6L.

5 and 6A, the silicon thin film forming step S1 is a step of forming the silicon thin film 120 ′ on the substrate 110. The substrate 110 may be formed of glass, that is, a glass substrate, a plastic substrate, a metal substrate, a polymer substrate, and an equivalent thereof used in a general thin film transistor. In addition, the silicon thin film 120 ′ is formed of amorphous silicon, followed by Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC) or Metal Induced Lateral Crystallization (MILC), and Solidification Phase Crystallization (SPC). Crystallization using a method, etc., and patterning it. In addition, the silicon thin film 120 ′ may also use a micro-, nano-crystalline silicon layer deposited by chemical vapor deposition (CVD) as an active layer thin film.

5 and 6B, the first insulating film forming step S2 is a step of forming the first insulating film 130 ′ on the silicon thin film 120 ′. The first insulating layer 130 ′ may be formed of various kinds of insulating layers (SiO ₂ , SiNx, SiOxNy, a high dielectric film, or an organic material), but a silicon oxide film (SiO ₂ having good interface characteristics with the semiconductor layer 120). It is preferably formed of).

5 and 6C, the first photoresist pattern forming step S3 is a step of forming the first photoresist pattern 10 on the second insulating layer 130 ′. The first photoresist pattern 10 may be composed of either a photosensitive agent or a negative photosensitive agent. The first photoresist pattern 10 is provided in the same pattern as the pattern to be formed on the second insulating layer 130 ′.

5 and 6D, the first etching step S4 is to perform etching by using the first photoresist pattern 10 as a barrier. In the first etching step S4, the exposed portion of the second insulating layer 130 ′ is etched, and the silicon thin film 120 ′ below it is also etched in the same shape.

5 and 6E, the second insulating film forming step S5 is a step of forming the second insulating film 140 ′ over the entire upper portion of the substrate 110. The second insulating layer 140 ′ may be formed of various kinds of insulating layers (SiO ₂ , SiNx, SiOxNy, a high dielectric film, or an organic material), but a silicon nitride film having good bonding properties with the first insulating film 130 ′. It is preferably formed of (SiOx).

5 and 6F, the second photoresist pattern forming step S6 is a step of forming the second photoresist pattern 20 on the second insulating layer 140 ′. The second photoresist pattern 20 is formed to cover a region other than the central region of the second insulating layer 140 ′.

5 and 6G, the second etching step S7 is a step of etching the second insulating layer 140 ′ using the second photoresist pattern 20 as a barrier. In the second etching step S7, a center region of the second insulating layer 140 ′ is etched to expose a top surface of the center region of the first insulating layer 130 ′.

5 and 6H, the gate material layer forming step S8 may include forming the gate material layer 160 ′ over the first insulating layer 130 ′ and the second insulating layer 140 ′. to be. The gate material layer 160 ′ may be formed using metal or polysilicon.

5 and 6I, the third photoresist pattern forming step S9 is a step of forming a third photoresist pattern 30 on the gate material layer 160 ′. The third photoresist pattern 30 is formed in the same manner as the pattern of the gate electrode to etch the gate material layer 160 ′ to form a desired gate electrode.

5 and 6J, the third etching step S10 may include the first insulating layer 130 ′ and the second insulating layer 140 ′ and a gate material layer as the barriers with the third photoresist pattern 30. Etching 160 '. By etching, the first insulating layer 130 ′ is the first insulating layer 130, the second insulating layer 140 ′ is the second insulating layer 140, and the gate material layer 160 ′ is the gate electrode 160. ).

5 and 6K, the ion implantation step S11 is a step of implanting impurity ions into the silicon thin film 120 ′ using the gate electrode 160 as a barrier. The impurity ions may be boron, phosphorus, or arsenic. In addition, a method of doping the impurity ions may be ion showering or ion implantation. As a result of the ion implantation step S11, a source drain region 122 is formed in an edge region of the silicon thin film 120 ′.

5 and 6L, the heat treatment step S12 is annealing or heat treatment to the silicon thin film 120 ′. Impurity ions diffuse from the source drain region 122 to the inside by the heat treatment step S12, and as a result, an LDD region 123 having a lower doping concentration than the source drain region 122 is formed. Thus, the semiconductor layer 120 is formed.

Hereinafter, another manufacturing method of the thin film transistor 100 according to the exemplary embodiment of the present invention will be described.

7 is a flowchart for explaining another method of manufacturing the thin film transistor 100 according to the exemplary embodiment of the present invention. 8A to 8J are cross-sectional views illustrating another method of manufacturing the thin film transistor 100 according to the exemplary embodiment of the present invention.

Referring to FIG. 5, in the thin film transistor 100 according to the exemplary embodiment of the present invention, the silicon thin film forming step S1, the first insulating film forming step S2, the second insulating film forming step S3, and the first etching step are performed. S5, a gate material layer forming step S6, a second etching step S8, an ion implantation step S9, and a third etching step S12. In addition, a first photoresist pattern forming step S4 may be further performed between the second insulating film forming step S3 and the first etching step S5, and the gate material layer forming step S6 and the second etching may be performed. A second photoresist pattern forming step S7 may be further performed between the steps S8, and between the ion implantation step S9 and the third etching step S12, the heat treatment step S10 and the third photo. The resist pattern forming step S11 may be further performed. Hereinafter, each step of FIG. 7 will be described with reference to FIGS. 8A to 8J.

 The silicon thin film forming step S1 is the same as the silicon thin film forming step S1 in the method of manufacturing the thin film transistor 100 according to the exemplary embodiment described above.

7 and 8A, the first insulating film forming step S2 is a step of forming the first insulating film 130 ′ on the silicon thin film 120 ′, and the second insulating film forming step S3. ) Is a step of forming the second insulating layer 140 ′ on the first insulating layer 130 ′.

7 and 8B, the first photoresist pattern forming step S4 is a step of forming the first photoresist pattern 10 on the second insulating layer 140 ′. The first photoresist pattern 10 is formed in the remaining regions except for the central region of the second insulating layer 140 ′.

7 and 8C, the first etching step S5 is a step of etching the second insulating layer 140 ′ using the first photoresist pattern 10 as a barrier. The central region of the second insulating layer 140 ′ is etched by the first etching step S5 to expose the top surface of the first insulating layer 130 ′.

7 and 8D, the gate material layer forming step S6 is a step of forming the gate material layer 160 ′ on the first insulating layer 130 ′ and the second insulating layer 140 ′. . The gate material layer 160 ′ is formed along the stepped shape of the second insulating layer 140 ′.

7 and 8E, the second photoresist pattern forming step S7 is a step of forming the second photoresist pattern 20 on the gate material layer 160 ′. The second photoresist pattern 20 has the same pattern as the pattern of the desired gate electrode.

7 and 8F, the second etching step S8 is a step of etching the second photoresist pattern 20 as a barrier. The lower layer of the second photoresist pattern 20 is etched so that the first insulating layer 130 ′ forms the first insulating layer 130, and the second insulating layer 140 ′ is the second insulating layer 140. ) And the gate material layer 160 ′ forms the gate electrode 160.

7 and 8G, the ion implantation step S9 is a step of implanting impurity ions into the silicon thin film 120 ′. The impurity ions are performed using the second photoresist pattern 20 or the gate electrode 160 as a barrier.

Referring to FIGS. 7 and 8H, the heat treatment step S10 may be annealing or heat treatment of the silicon thin film 120 ′. The LDD region 123 is formed under the first insulating layer 130 by the heat treatment step 10.

7 and 8I, the third photoresist pattern forming step S11 may include the silicon thin film 120 ′, the first insulating layer 130, the second insulating layer 140, and the gate electrode 160. The third photoresist pattern 30 is formed on the upper side of the substrate. The third photoresist pattern 30 is formed corresponding to a region in which the semiconductor layer is to be formed in the silicon thin film 120 ′.

7 and 8J, in the third etching step S12, the semiconductor layer 120 is formed by etching the silicon thin film 120 ′ using the third photoresist pattern 30 as a barrier. to be. The semiconductor layer 120 includes a channel region 121, a source drain region 122, and an LDD region 123 formed inside the source drain region 122 to reduce leakage current.

Hereinafter, a method of manufacturing the thin film transistor 200 according to another embodiment of the present invention will be described.

9A to 9H are cross-sectional views illustrating another method of manufacturing the thin film transistor 200 according to another exemplary embodiment of the present invention. And the manufacturing method of the thin film transistor 200 according to another embodiment of the present invention is made in the same order as the flowchart of FIG. Therefore, hereinafter, each step of FIG. 7 will be described with reference to FIGS. 9A to 9H.

7 and 9A, the silicon thin film forming step S1, the first insulating film forming step S2, the second insulating film forming step S3, and the first photoresist pattern forming step S4 are described above. The steps S1 to S4 in the other method of manufacturing the thin film transistor 100 according to the exemplary embodiment are the same.

7 and 9A, the first etching step S5 is to etch the second insulating layer 240 ′ using the first photoresist pattern as a barrier. In the first etching step S5, the central region of the second insulating layer 240 ′ is partially etched to form a step.

7 and 9B, the gate material layer forming step S6 is a step of forming a gate material layer 260 ′ on the first insulating layer 130 ′ and the second insulating layer 240 ′. . The gate material layer 260 ′ is formed along the stepped shape of the second insulating layer 240 ′.

7 and 9C, the second photoresist pattern forming step S7 is a step of forming the second photoresist pattern 20 on the gate material layer 260 ′. The second photoresist pattern 20 has the same pattern as the pattern of the desired gate electrode.

7 and 9D, the second etching step S8 is a step of etching the second photoresist pattern 20 as a barrier. The lower layer of the second photoresist pattern 20 is etched so that the first insulating layer 130 ′ forms the first insulating layer 130, and the second insulating layer 240 ′ is the second insulating layer 240. ) And the gate material layer 260 ′ forms the gate electrode 260.

7 and 9E, the impurity ion implantation step (S9) is a step of implanting impurity ions into the silicon thin film 120 ′. The impurity ions are performed using the third photoresist pattern 30 or the gate electrode 260 as a barrier.

Referring to FIGS. 7 and 9F, the heat treatment step S10 is annealing or heat treatment of the silicon thin film 120 ′. The LDD region 123 is formed under the first insulating layer 130 by the heat treatment step 10.

7 and 9G, the third photoresist pattern forming step S11 may include the silicon thin film 120 ′, the first insulating layer 130, the second insulating layer 240, and the gate electrode 260. The third photoresist pattern 30 is formed on the upper side of the substrate. The third photoresist pattern 30 is formed in a region in which the semiconductor layer is to be formed in the silicon thin film 120 ′.

7 and 9H, in the third etching step S12, the semiconductor layer 120 is formed by etching the silicon thin film 120 ′ using the third photoresist pattern 30 as a barrier. to be. The semiconductor layer 120 includes a channel region 121, a source drain region 122, and an LDD region 123 formed inside the source drain region 122 to reduce leakage current.

1 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

2 is a cross-sectional view of a thin film transistor according to another exemplary embodiment of the present invention.

3 is a cross-sectional view of a thin film transistor according to another exemplary embodiment of the present invention.

4 is a cross-sectional view of a thin film transistor according to another exemplary embodiment of the present invention.

5 is a flowchart illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

6A to 6L are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

7 is a flowchart illustrating another method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

8A to 8J are cross-sectional views illustrating another method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

9A to 9H are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 400; Thin film transistor

110; A substrate 120; Semiconductor layer

121; Channel region 122; Source drain region

123; LDD region 130; First insulating layer

140, 240, 440; Second insulating layers 350 and 450; Third insulating layer

160, 260, 360, 460; Gate electrode

Claims (21)

A semiconductor layer including a source drain region formed on the substrate, an LDD region doped at a lower concentration than the source drain region inside the source drain region, and a channel region formed inside the LDD region; A first insulating layer formed on the semiconductor layer; A second insulating layer formed on the edge of the first insulating layer to correspond to the LDD region; And A thin film transistor comprising a gate electrode formed on the first insulating layer and the second insulating layer. delete The method of claim 1, And the gate electrode is formed while making a step in contact with the first insulating layer in a region corresponding to the channel region of the semiconductor layer and in contact with the second insulating layer in a region corresponding to the LDD region. The method of claim 1, And a third insulating layer having the same planar shape as the second insulating layer between the second insulating layer and the gate electrode. The method of claim 3, wherein And the gate electrode is formed in contact with the first insulating layer in a region corresponding to the channel region of the semiconductor layer, and forms a step in contact with the third insulating layer in a region corresponding to the LDD region. The method of claim 1, The second insulating layer is formed to cover the upper portion of the first insulating layer, characterized in that formed with a step so that the height of the region corresponding to the LDD region of the semiconductor layer is higher than the height corresponding to the channel region. Thin film transistor. The method of claim 6, And the gate electrode is formed along the step of the second insulating layer on the second insulating layer. The method of claim 6, And a third insulating layer formed along the edge of the second insulating layer on the second insulating layer, such that the height of the edge is higher than that of the center. The method of claim 8, And the gate electrode is formed such that a region corresponding to the channel region of the semiconductor layer is in contact with the second insulating layer, and a region corresponding to the LDD region is in contact with the third insulating layer to form a step. Forming a silicon thin film on top of the substrate; Forming a first insulating film on the silicon thin film; A first etching step of etching the silicon thin film to form a semiconductor layer; Forming a second insulating film on the semiconductor layer and the first insulating film; Etching a central region of the second insulating layer to expose the central region of the first insulating layer, or to form a thicker edge region than the central region of the second insulating layer; Forming a gate material layer on the first insulating film and the second insulating film; A third etching step of forming a first insulating layer, a second insulating layer, and a gate electrode to etch the first insulating layer, the second insulating layer, and the gate material layer to expose edge regions of the semiconductor layer; And And implanting impurities into an edge region of the semiconductor layer to form an LDD region in a source drain region and the source drain region. 11. The method of claim 10, And a heat treatment step of diffusing the impurities into the LDD region by performing heat treatment on the semiconductor layer after the ion implantation step. 11. The method of claim 10, And a third insulating film forming step of forming a third insulating film on top of the second insulating film between the second insulating film forming step and the second etching step. delete delete The method of claim 10, And the third etching step is performed such that the gate electrode remains on the second insulating film. Forming a silicon thin film on top of the substrate; Forming a first insulating film on the silicon thin film; A second insulating film forming step of forming a second insulating film on the first insulating film; Etching a central region of the second insulating layer to expose a central region of the first insulating layer, or forming a second thickness of the edge region of the second insulating layer thicker than that of the central region; Forming a gate material layer on the first insulating film and the second insulating film; Etching the first insulating film, the second insulating film, and the gate material layer to form a first insulating layer, a second insulating layer, and a gate electrode, and exposing an edge region of the silicon thin film; Implanting an impurity into an edge region of the silicon thin film to form a source drain region and an LDD region located inside the source drain region; And And etching the silicon thin film to form a semiconductor layer. The method of claim 16, And a heat treatment step of performing heat treatment on the silicon thin film between the ion implantation step and the third etching step to diffuse the impurities into the LDD region. The method of claim 16, And a third insulating film forming step of forming a third insulating film on top of the second insulating film between the second insulating film forming step and the first etching step. delete delete The method of claim 16, And the second etching step is performed such that the gate electrode remains on the second insulating film.

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