KR20040060106A - fabrication method of poly silicon TFT and array circuit including thereof - Google Patents

Abstract

PURPOSE: A polysilicon thin film transistor and a method for manufacturing an array substrate including the same are provided to form an interfacial insulation film as double layer and form a contact hole of the interfacial insulation film by three steps, that is, dry, wet and dry etchings, thereby improving a contact characteristic between source/drain electrodes and an active layer and enhancing a driving characteristic of an LCD(Liquid Crystal Display) panel. CONSTITUTION: A double layer insulation film(118,118'), as the third insulation layer, is formed at the entire surface of the gate electrode, the second active region(116,117) and the first insulation layer(102). The double layer insulation film comprises an upper layer insulation film(118) and a lower layer insulation film(118'). A photoresist layer(120) is formed on the upper layer insulation film(118). After performing an exposure processing, the second region(116,117) is developed. After removing the photoresist, the upper layer insulation film(118) is exposed. Through a wet etching method, a lower layer insulation film(118') exposed by the etched upper layer insulation film(118) is etched, so that polysilicon layers(116,117) doped impurities are exposed.

Description

Polysilicon thin film transistor and method for manufacturing array substrate including same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a method of manufacturing a poly-silicon TFT and an array substrate for a liquid crystal display including the same.

In general, a liquid crystal display (LCD) forms a thin film transistor as a switching element connected to individual pixels forming a screen of a display device, and is driven by controlling a pixel electrode potential using the thin film transistor. . The thin film transistor is usually formed on a glass substrate using a semiconductor thin film, and a polysilicon thin film transistor is one in which polysilicon is used as the semiconductor thin film.

The polysilicon has a much higher mobility of carriers than amorphous silicon. Accordingly, the transistor element for the driving circuit IC can be formed on the glass substrate together with the switching thin film transistor for the pixel electrode, thereby reducing the cost of the module process in LCD manufacturing and simultaneously using the LCD to be completed. Power consumption can also be lowered.

In general, in order to form a semiconductor thin film used in the thin film transistor as a polysilicon thin film, pure amorphous silicon (Intrinsic amorphous silicon) is a predetermined method, that is, a plasma chemical vapor deposition (Plasma chemical vapor deposition) or LPCVD process A method of depositing an amorphous silicon film by pressure CVD and then crystallizing it again was used.

The crystallization method can be classified into three types: laser annealing method, solid phase crystallization (SPC) method, and metal induced crystallization (MIC) method. A method of growing polycrystalline silicon by applying a laser to a deposited substrate, a method of forming polycrystalline silicon by heat treatment of amorphous silicon at a high temperature for a long time, and a method of forming polycrystalline silicon by depositing a metal on the amorphous silicon.

In the case of using polysilicon fabricated by such a plurality of manufacturing methods as an active channel, a coplanar type thin film transistor, that is, a top gate type thin film transistor in which the gate electrode is located on the active layer, is used. It is common to comprise in an array substrate.

1 is a schematic cross-sectional view of a portion of an array substrate for a liquid crystal display device including a top gate type thin film transistor.

Referring to FIG. 1, a semiconductor layer 8 formed on a substrate 1 and a source electrode 20 and a drain electrode 22 are in contact with both sides of the semiconductor layer 8.

The semiconductor layer 8 is defined as an active region 14 as a first region and source and drain regions 16 and 17 as a second region, and the source and drain electrodes 20 and 22 are formed as the second region. Each is constructed in contact.

A gate electrode 12 is positioned on the active region 14 with a gate insulating layer 10 interposed therebetween, and a position corresponding to the source and drain regions 16 and 17 is disposed on the gate electrode 12. The interlayer insulating film 18 including the contact holes 16 'and 17' constituted by is formed.

At this time, the source electrode 20 and the drain electrode 22 formed at both sides of the active region 14 are electrically connected to the source and drain regions 16 and 17 below through the contact holes 16 'and 17'. The drain electrode 22 is in electrical contact with the transparent pixel electrode 28 with the protective layer 26 therebetween.

In the above configuration, the contact resistance between the source and drain regions 16 and 17 and the source and drain electrodes 20 and 22, the drain electrode 22 and the pixel electrode ( 28) has a great influence on the operating characteristics of the thin film transistor T, and in this case, the interlayer insulating film 18 and the protective film between the two components affect the contact characteristics of the two components. (26)

That is, the source electrode and the drain electrodes 20 and 22 are in contact with the source and drain regions 16 and 17 through the interlayer insulating layer 18, and the drain electrode 22 and the pixel electrode 28 are respectively in contact with each other. ), The interlayer insulating layer 18 and the passivation layer 26 must be etched.

In the related art, a problem such as an etching rate is too slow or an etching nonuniformity often occurs depending on a method of etching the insulating film.

Hereinafter, a manufacturing process of an array substrate including a top gate polysilicon thin film transistor will be briefly described with reference to FIGS. 2A to 2C.

First, as shown in FIG. 2A, the first insulating material and the amorphous silicon are sequentially deposited on the substrate 1, and then the first insulating film and the amorphous silicon layer are formed.

Next, the amorphous silicon is crystallized by a predetermined method to form polysilicon, and the polysilicon is patterned to form an island-shaped semiconductor layer 8.

The first insulating film is a buffer layer 2, and is configured to prevent diffusion of the alkyl group eluted from the surface of the glass substrate at the high temperature into the semiconductor layer 8.

Next, as shown in FIG. 2B, a silicon nitride film (SiNx) or a silicon oxide film (SiO 2) is deposited on the island-shaped semiconductor layer 8 to form a second insulating film, which is a gate insulating film. A conductive metal is deposited and patterned on the insulating film 10 to form the gate electrode 12 at a position corresponding to the active region 14 of the semiconductor layer 8.

The semiconductor layer 8 may be divided into two regions, in which the first active region 14 is a pure silicon region, and the second active regions 16 and 17 are impurity regions. The second active regions 16 and 17 are located at both edges of the first active region 14.

The gate insulating layer 10 and the gate electrode 12 are formed on the first active region 14.

The gate electrode 12 and the gate insulating film 10 are preferably formed in the same pattern in order to reduce the number of masks. After the gate electrode 12 is formed, ion doping is performed to form an ohmic contact layer in the second active region. In this case, the gate electrode 12 is doped with the first active region 14. It acts as an ion stopper to prevent the penetration of the dopant. After the ion doping process, the process proceeds to the step of activating the dopant.

FIG. 2C is a step of depositing and patterning an interlayer insulator 18, which is a third insulating film, over the entire surface of the gate electrode 12, the second active regions 16 and 17, and the gate insulating film 10. Source / drain contact holes 16 'and 17' are formed in the second active regions 16 and 17, respectively. In this case, the interlayer insulating layer is formed of one selected from the group of inorganic insulating materials consisting of SiO 2, SiN x, TEOS, and Al 2 O 3.

Next, the source electrode 20 and the drain electrode 22 contacting the second active regions 16 and 17, respectively, are formed through the contact holes 16 ′ and 17 ′.

Subsequently, as shown in FIG. 1, the protective layer 26 is deposited and patterned over the entire surfaces of the electrodes 20 and 22 and the substrate to etch the protective layer 26 on the drain electrode 22. The lower drain electrode 22 is exposed.

The transparent conductive electrode is deposited and patterned to form the pixel electrode 28 in electrical contact with the exposed drain electrode 22.

Through the process as described above, it is possible to manufacture an array substrate constituting a general polysilicon thin film transistor.

However, during the process described above, the contact between the source and drain electrodes and the polysilicon region doped with the impurity is made through a contact hole formed by etching the insulating layer.

3 to 4 are enlarged cross-sectional views illustrating an enlarged area A (or B) of FIG. 1, FIG. 3 is a cross-sectional view illustrating a case of etching by a dry etching method, and FIG. 4 is a view of a case of etching an insulating film by a wet etching method. It is a cross section. However, it is sectional drawing which shows during the process of patterning the said interlayer insulation film.

First, as shown in FIG. 3, in order to pattern the interlayer insulating layer 18, a PR layer 30 is formed by coating a photoresist (PR) on the interlayer insulating layer 18.

Next, a process of exposing the PR layer 30 corresponding to the upper portion of the second region (16 and 17 of FIG. 2C) is performed through an exposure mask (not shown).

After the exposure process is completed, the exposed portion is developed and removed to expose the lower interlayer insulating film 18, and then the exposed insulating film is etched by dry etching to form a second region doped with n-type or p-type impurities ( 16, 17) dry etching to expose.

However, the dry etching method as described above has a limitation in obtaining a desired etching depth because the etching speed is too slow. In addition, as the etching time increases, the PR may be cured, and thus, the PR layer 30 may not be properly removed in the process of stripping the photoresist layer. Therefore, in the case of dry etching, the condition is set to etch all the insulating films deposited to a predetermined thickness during this time in consideration of the time that the PR layer 30 is not cured.

However, if the thickness of the insulating film 18 is deposited irregularly and thickly deposited with a slight error, this portion cannot be completely etched. As a result, the non-etched residual insulating layer C partially covers the second active regions 16 and 17 thinly.

In addition, when all of the insulating layers are etched by dry etching, since the second active region is exposed to the plasma, contact resistance with the source / drain electrodes increases to adversely affect the device characteristics.

Accordingly, when the insulating film (silicon insulating film: silicon oxide film, silicon nitride film) 18 is etched by the dry etching method, process stability is required, and a faster process time is required. (Of course, the same problem may occur in the case of the protective film 28.)

Alternatively, as shown in FIG. 4, when wet etching the interlayer insulating layer 18, a good side profile may be formed, but as the thickness of the insulating layer 18 increases, exposure to the etching solution may occur. As the time increases, the insulating layer 18 of the portion D in contact with the photoresist layer 30 is overetched to generate a CD dimension (critical dimension loss). In this case, the CD loss means a loss in which etching occurs outside the limit of the etching error without etching as the original design.

In addition, the second region (16, 17: impurity polysilicon layer) and the metal electrodes (20, 22: source and drain electrodes) do not come into contact with each other due to a decrease in etching uniformity due to a photoresist residue not properly removed after development. There is also the possibility of an open failure. As a result, the operating characteristics of the liquid crystal panel may be degraded or partial point defects may be caused.

According to the present invention, the interlayer insulating film is formed as a double layer and is formed through three steps of dry, wet, and dry when forming the contact hole of the interlayer insulating film, thereby improving contact characteristics between the source / drain electrode and the active layer to improve operating characteristics of the liquid crystal panel. An object of the present invention is to provide an improved polysilicon thin film transistor and an array substrate manufacturing method including the same.

1 is a schematic cross-sectional view of a portion of an array substrate for a liquid crystal display device including a top gate type thin film transistor;

2A to 2C are cross-sectional views illustrating a manufacturing process of an array substrate including a conventional top gate polysilicon thin film transistor.

3 to 4 are enlarged cross-sectional views illustrating the area A (or B) of FIG.

5A to 5D are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device including a polysilicon thin film transistor according to an embodiment of the present invention.

6 is a view showing a portion of a polysilicon thin film transistor array substrate according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate 116, 117: second region (source, drain region)

118: upper insulating film 118 ': lower insulating film

110 ': gate insulating film 120: photoresist layer

121: interlayer insulating film

In order to achieve the above object, a polysilicon thin film transistor manufacturing method according to an embodiment of the present invention, the polysilicon semiconductor layer, a gate insulating film, a gate electrode sequentially formed on a substrate, the semiconductor layer overlapping the gate electrode Doping impurities into regions other than the center portion of the to form source and drain regions; Forming a double layer insulating film formed of a lower layer and an upper layer on the source region, the drain region, and the gate electrode; Etching the upper insulating film by dry etching a predetermined region of the double layer insulating film; Etching the lower insulating film exposed by the etched upper insulating film through wet etching to expose the source region and the drain region; Etching side surfaces of the lower insulating film through dry etching; Cleaning surfaces of the exposed source and drain regions with hydrofluoric acid (HF); And forming a source electrode and a drain electrode in contact with the source region and the drain region, respectively.

Further, sequentially forming a polysilicon semiconductor layer, a gate insulating film, and a gate electrode on the substrate may include forming an island-like polysilicon semiconductor layer on the substrate, and forming a gate on the central portion of the island-shaped semiconductor layer. And forming an insulating film and a gate electrode.

In addition, the upper insulating film of the double layer insulating film is formed of silicon nitride (SiN, SiON), the lower insulating film is characterized in that the silicon oxide film (SiO ₂ ). In addition, the polysilicon thin film transistor manufacturing method according to another embodiment of the present invention, forming a polysilicon semiconductor layer of the island shape on the substrate; Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer, and forming a gate electrode on the gate insulating film corresponding to a central region of the semiconductor layer; Forming a source region and a drain region by doping an impurity to a surface of a region other than a central portion of the semiconductor layer overlapping the gate electrode; Forming an interlayer insulating layer over the source and drain regions and the gate electrode; Forming a photoresist on the interlayer insulating film, and exposing a portion of the photoresist by placing an exposure mask thereon; Developing and removing the exposed photoresist to expose a predetermined region of the interlayer insulating film; Etching the interlayer insulating layer by dry etching the exposed interlayer insulating layer; Etching the gate insulating film exposed by the etched upper insulating film through wet etching to expose the source region and the drain region; Etching side surfaces of the gate insulating layer through dry etching; Cleaning surfaces of the exposed source and drain regions with hydrofluoric acid (HF); And forming a source electrode and a drain electrode in contact with the source region and the drain region, respectively.

The interlayer insulating layer may be formed of silicon nitride (SiN, SiON), and the gate insulating layer may be formed of silicon oxide (SiO ₂ ).

According to the present invention, the etching profile is improved when the insulating film is etched, and the contact characteristics of the source / drain electrodes and the active pattern are improved, thereby improving the operating characteristics of the liquid crystal panel, thereby improving the manufacturing yield of the product. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 5D are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device including a polysilicon thin film transistor according to an embodiment of the present invention.

However, since the processes of forming the buffer layer 102 and the polysilicon semiconductor layer 108, which are the first insulating layers, are the same in FIGS. 2A through 2C, the description thereof will be omitted.

Subsequently, in FIG. 5A, a gate insulating film and a gate electrode are formed. A gate insulating film 110 and a gate electrode 112 are formed as a second insulating layer on the island-shaped semiconductor layer 108. The semiconductor layer 108 may be divided into two regions, wherein the first active region 114 is a pure silicon region, and the second active regions 116 and 117 are impurity regions.

The second active regions 116 and 117 are located at both edges of the first active region 114.

The gate insulating layer 110 and the gate electrode 112 are formed on the first active region 114.

The gate electrode 112 and the gate insulating layer 110 are formed in the same pattern to reduce the number of masks, and after the gate electrode 112 is formed, ion doping is performed to form an ohmic contact layer in the second active region. do. In this case, the gate electrode 112 serves as an ion stopper to prevent the dopant from penetrating into the first active 114 region. When the ion doping, the electrical characteristics of the silicon island 108 is changed according to the type of dopant. When the dopant is doped with a group 3 element such as B2H6, the dopant is a P-type semiconductor, and the group 5 element such as PH3 is doped. In this case, it operates as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device. After the ion doping process, the process proceeds to the step of activating the dopant.

Next, as shown in FIG. 5B, an interlayer insulator is a third insulating layer over the entire surface of the gate electrode 112, the second active regions 116 and 117, and the first insulating layer 102. 118, 118 '). At this time, the double insulating film is composed of an upper insulating film 118 and a lower insulating film 118 ', the upper insulating film 118 is formed of silicon nitride (SiN, SiON), the lower insulating film 118' is a silicon oxide film ( SiO ₂ ) is characterized in that.

Next, in order to perform a photo-lithography process on the upper insulating film 118 of the double layer insulating film, first, a photoresist (positive type) is coated and then a photoresist layer 120 is formed.

Next, an exposure process of placing an exposure mask (not shown) on the photoresist layer 120 and exposing a specific portion E (photoresist layer at a position corresponding to the second region) to light. Proceed).

At this time, the second regions 116 and 117, that is, the photoresist region E on the source region and the drain region, are exposed.

Next, as illustrated in FIG. 5C, when the exposed photoresist is developed and removed, the upper insulating film 118 of the double layer insulating film is exposed at the bottom.

At this time, the exposed portion of the upper insulating film 118 is removed by dry etching. The dry etching method is to remove the insulating film 118 by the principle of electron collision, in the case of the present invention by removing only the upper insulating film 118 through dry etching, since the etching speed is too low as in the conventional case desired It is difficult to obtain an etching depth, and as the etching time increases, the photoresist layer 120 is cured, thereby overcoming a problem in the process of removing the photoresist. In addition, the upper insulating layer 118 further maximizes the efficiency of dry etching by using a silicon nitride film having a good dry etching reaction.

Next, the lower layer insulating layer 118 ′ exposed by the etched upper insulating layer 118 is etched through a wet etching method, and thus the polysilicon layer 116 doped with impurities, which are the second regions 116 and 117, is formed. 117).

In this case, in the present invention, only the lower insulating layer 118 'is removed by wet etching, so that the loss of the CD into which the insulating layer existing under the photoresist enters into the photoresist is increased by the increase of the etching liquid exposure time as in the conventional case. The disadvantage of the loss and the etch uniformity due to the residual photoresist are overcome.

In addition, the lower insulating layer 118 ′ further maximizes the efficiency of wet etching by using a silicon oxide film having a good wet etching reaction.

Next, the side surface of the lower insulating layer 118 ′ is etched through dry etching. In this case, an under cut occurs when the wet etching process is performed. In this case, a step with the source / drain electrode which comes into contact with the source region 116 and the drain region 117 through the contact hole is performed later. The dry etching process is added again to improve step coverage.

Next, the surfaces of the source and drain regions 116 and 117 exposed by the dry and wet etching are cleaned using hydrofluoric acid (HF). This is to prevent damage to the source and drain region surfaces 116 and 117 by the dry etching process to improve contact characteristics with the source / drain electrodes. Accordingly, the hydrofluoric acid (HF) method may be performed by a spin method or the like. The source and drain region surfaces 116 and 117 may be cleaned by using N) to eliminate etch unevenness generated by the dry etching process and to secure excellent contact resistance characteristics of the source and drain region surfaces.

After the contact holes 116 'and 117' are formed in the same manner as described above, as shown in FIG. 5D, the second active regions 116 and 117 are respectively formed through the contact holes 116 'and 117'. The source electrode 120 and the drain electrode 122 are in contact with each other.

The source electrode and the drain electrode are formed of one selected from a conductive metal group consisting of aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), antimony (Sb), and tantalum (Ta).

Polysilicon thin film transistor can be formed in the above manner.

Thereafter, the protective layer 126 is deposited and patterned on the electrodes 120 and 122 and the entire surface of the substrate to expose the lower drain electrode 122.

In this case, the process of etching the protective layer 126 may also form an etch hole having a uniform profile by using a dry etching method and a wet etching method as described above.

Next, the transparent conductive electrode is deposited and patterned to form the transparent pixel electrode 128 in contact with the exposed drain electrode 122.

In the above-described process, a polysilicon thin film transistor array substrate according to the present invention can be manufactured.

FIG. 6 is a diagram illustrating a part of a polysilicon thin film transistor array substrate according to another embodiment of the present invention.

Referring to FIG. 6, when the polysilicon thin film transistor according to another embodiment of the present invention is compared with the polysilicon thin film transistor illustrated in FIG. 5, the gate insulating film 110 ′ may have the gate electrode 112 and the gate insulating film 110. The silver is not formed in the same pattern to reduce the number of masks but is formed entirely on the substrate including the semiconductor layer 114, and after the gate electrode 112 is formed to form an ohmic contact layer in the second active region. Ion doping is performed through the gate insulating layer 110 ′.

In addition, the double layer insulating films 118 and 118 'as shown in FIG. 5 are not formed, and the single layer interlayer insulating film 121 is formed. However, the gate insulating film 110 ′ is made of a silicon oxide film, and the interlayer insulating film 121 is made of a silicon nitride film.

However, in forming the contact holes 116 and 117 ', the material constituting the insulating layer is the same as the material of the upper insulating film 118 and the lower insulating film 118' shown in FIG. It can be formed through the process, which is the same as Figure 5 will be omitted the description.

As described above, according to the polysilicon thin film transistor according to the present invention and an array substrate manufacturing method including the same, the etching profile is improved when the insulating layer is etched, and the contact characteristics of the source / drain electrode and the active pattern are improved to operate the liquid crystal panel. It improves the characteristics, and thus there is an advantage that the manufacturing yield of the product is improved.

Claims (10)

Sequentially forming a polysilicon semiconductor layer, a gate insulating film, and a gate electrode on the substrate, and forming a source region and a drain region by doping impurities on a surface of a region other than the center portion of the semiconductor layer overlapping the gate electrode; Forming a double layer insulating film formed of a lower layer and an upper layer on the source region, the drain region, and the gate electrode; Etching the upper insulating film by dry etching a predetermined region of the double layer insulating film; Etching the lower insulating film exposed by the etched upper insulating film through wet etching to expose the source region and the drain region; Etching side surfaces of the lower insulating film through dry etching; Cleaning surfaces of the exposed source and drain regions using hydrofluoric acid (HF), Forming a source electrode and a drain electrode in contact with the source region and the drain region, respectively. The method of claim 1, Forming a polysilicon semiconductor layer, a gate insulating film, and a gate electrode on the substrate sequentially includes forming an island-shaped polysilicon semiconductor layer on the substrate, and forming a gate insulating film and a gate insulating film on a central portion of the island-shaped semiconductor layer. A method of manufacturing a polysilicon thin film transistor, characterized in that by forming a gate electrode. The method of claim 1, And the predetermined region is a region on the double layer insulating layer overlapping the source region and the drain region. The method of claim 1, The upper insulating film of the double layer insulating film is a silicon nitride film (SiN, SiON), characterized in that the polysilicon thin film transistor manufacturing method. The method of claim 1, The lower layer insulating film of the double layer insulating film is a silicon oxide film (SiO ₂ ) characterized in that the polysilicon thin film transistor manufacturing method. A polysilicon thin film transistor according to any one of claims 1 to 5, Depositing a source film and a drain electrode of the polysilicon thin film transistor to form a protective film exposing a portion of the drain electrode; And forming a transparent electrode formed on the passivation layer and in contact with the drain electrode. Forming an island-shaped polysilicon semiconductor layer on the substrate, Forming a gate insulating film on the entire surface of the substrate including the semiconductor layer, and forming a gate electrode on the gate insulating film corresponding to the central region of the semiconductor layer; Forming a source region and a drain region by doping an impurity to a surface of a region other than the central portion of the semiconductor layer overlapping the gate electrode; Forming an interlayer insulating layer over the source and drain regions and the gate electrode; Forming a photoresist on the interlayer insulating film, and exposing a portion of the photoresist by placing an exposure mask thereon; Developing and removing the exposed photoresist to expose a predetermined region of the interlayer insulating film; Etching the interlayer insulating layer by dry etching the exposed interlayer insulating layer; Etching the gate insulating film exposed by the etched upper insulating film through wet etching to expose the source and drain regions; Etching side surfaces of the gate insulating layer through dry etching; Cleaning surfaces of the exposed source and drain regions using hydrofluoric acid (HF), Forming a source electrode and a drain electrode in contact with the source region and the drain region, respectively. The method of claim 7, wherein The interlayer insulating film is a silicon nitride film (SiN, SiON), characterized in that the polysilicon thin film transistor manufacturing method. The method of claim 7, wherein The gate insulating film is a silicon oxide film (SiO ₂ ) characterized in that the polysilicon thin film transistor manufacturing method. A polysilicon thin film transistor according to any one of claims 7 to 9, Depositing a source film and a drain electrode of the polysilicon thin film transistor to form a protective film exposing a portion of the drain electrode; And forming a transparent electrode formed on the passivation layer and in contact with the drain electrode.