KR101351403B1 - Thin Film Transtistor, Method for Manufacturing the Same and Method for Manufacturing Flat Panel Display Device Using the Same - Google Patents

Abstract

The present invention provides a thin film transistor which improves device characteristics by reducing the thickness of the gate insulating layer on the top of the source / drain electrodes in a top gate structure by performing a process of defining a channel region separately from the formation of the source / drain electrodes. A manufacturing method and a method of manufacturing a display device using the same, the method of manufacturing a thin film transistor according to the present invention includes depositing a first amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer. And sequentially depositing an impurity layer and a second amorphous silicon layer on the crystalline silicon layer, etching the second amorphous silicon layer, the impurity layer, and the crystalline silicon layer in the same width to form a semiconductor layer, and One of the crystalline silicon layer, the impurity layer and the second amorphous silicon layer so as to define a channel portion in the central portion of the semiconductor layer Removing the sub-thickness, forming a gate insulating film on the semiconductor layer, and depositing a metal layer on the entire surface including the semiconductor layer and the gate insulating film and selectively removing the impurity layer and a portion of the impurity layer on both sides of the semiconductor layer. And forming a gate electrode formed on and in contact with the source electrode and the drain electrode.

Alternating Magnetic Field Crystallization (AMFC), Thin Film Transistor, Amorphous Silicon Layer, Crystalline Silicon

Description

[0001] The present invention relates to a thin film transistor (TFT), a method of manufacturing the same,

The present invention relates to a thin film transistor and more particularly to a method of forming a channel region separately from a formation of a source / drain electrode and reducing a thickness of a gate insulating film above a source / drain electrode in a top gate structure, A method of manufacturing the same, and a method of manufacturing a display using the thin film transistor.

Recently, the demand for low temperature polysilicon thin film transistors as driving elements for display devices such as active matrix liquid crystal display devices (AMLCD) and active matrix organic light emitting diodes (AMOLED) has been increasing.

A thin film transistor (TFT) is mainly used as a switching device for driving a display device, and amorphous silicon is mainly used as an active layer of the thin film transistor.

In particular, a liquid crystal display device using a liquid crystal arranged in a predetermined direction according to an electric field as a component of a display device employs a thin film transistor as a switching device. Today, in order to realize a high response speed and low power consumption, Research on the use of polysilicon as the active layer has been actively conducted.

A process for producing a liquid crystal display device using polysilicon as a channel is generally a process for forming amorphous silicon on a substrate such as glass by a plasma chemical vapor deposition (PECVD) method and crystallizing the deposited amorphous silicon It proceeds.

As a method of crystallizing the amorphous silicon, there are a high temperature heating method of crystallizing the amorphous silicon through a process of heating and cooling the amorphous silicon for a long time in a high temperature furnace, a high temperature heating method of instantaneously irradiating a high intensity laser energy, An annealing method or the like is used.

Since the amorphous silicon layer is heated at a high temperature not lower than the glass transition temperature of the crystallization method, various methods for crystallizing amorphous silicon at low temperature are not suitable because it is not suitable for application to liquid crystal display devices using glass or the like as a substrate Respectively.

Among them, AMFC (Alternating Magnetic Field Crystallization) method has been proposed in which crystallization proceeds by applying a magnetic field at which crystallization progresses at a relatively low temperature.

The AMFC crystallization method promotes crystallization by applying an alternating magnetic field to amorphous silicon to form an induced electromotive force in the silicon layer. By the FEMIC and AMFC crystallization, the silicon layer can undergo crystallization at about 500 ° C or about 430 ° C.

Amorphous silicon has a very high resistivity value of about 10 ⁶ ~ 10 ¹⁰ Ω-㎝, which is a resistivity at room temperature. However, when the temperature of amorphous silicon is increased by external heating, the resistivity rapidly decelerates and joule heating occurs It is known that AMFC crystallization promotes crystallization.

However, the AMFC crystallization method has an advantage that crystallization is possible at a low temperature, but has a disadvantage in that the voltage characteristics of the crystallized silicon are not good. That is, the channel layer formed by the AMFC crystallization is not a good crystalline material, and the thin film transistor including the crystalline silicon has a problem that the threshold voltage (Vth) is shifted to a negative value, have.

Hereinafter, a conventional thin film transistor will be described with reference to the accompanying drawings.

1A is a cross-sectional view of a conventional amorphous silicon thin film transistor, and FIG. 1B is a cross-sectional view illustrating the structure of the semiconductor layer of FIG. 1A.

1A and 1B, a conventional thin film transistor using amorphous silicon has a structure in which a gate insulating film 3, an amorphous silicon layer 4a and an n + layer 4b are sequentially stacked by a PECVD (Plasma Enhanced Chemical Vapor Deposition) At this time, the semiconductor layer 4 is composed of the amorphous silicon layer 4a and the n + layer 4b.

That is, a conventional thin film transistor using amorphous silicon has a gate electrode 2 formed on a predetermined portion of a substrate 1, a gate insulating film 3 formed on the entire surface of the substrate 1 including the gate electrode 2, A semiconductor layer 4 formed of a laminate of the amorphous silicon layer 4a and the n + layer 4b on the gate insulating film 3 and formed in the shape of a star so as to cover the gate electrode 2, And source / drain electrodes 5a / 5b formed on both sides of the source / drain electrodes 4a and 4b.

In a display device using such a thin film transistor, a contact hole is formed on the gate insulating film 3 including the source / drain electrodes 5a / 5b and exposes a part of the drain electrode 5b An interlayer insulating film 6 and a pixel electrode 7 formed by filling the contact hole and making contact with the drain electrode 5b.

The semiconductor layer 4 defines a region between the source and drain electrodes 5a and 5b as a channel and the n + layer 4b corresponding to the channel and the amorphous silicon layer 4a Is removed.

Hereinafter, an example in which a semiconductor layer crystallized by an AMFC (Alternating Magnetic Field Crystallization) method is used instead of the amorphous silicon layer will be described.

FIG. 2A is a cross-sectional view illustrating a thin film transistor having a self-crystallized (AMFC) semiconductor layer, and FIG. 2B is a cross-sectional view illustrating the structure of the semiconductor layer of FIG.

2A and 2B, a thin film transistor using a self-crystallized semiconductor layer is formed by sequentially depositing a buffer layer 11 made of an oxide film (SiO2) and a first amorphous silicon layer, applying a magnetic field thereto, The first amorphous silicon layer is crystallized to form a crystalline silicon layer 12a, and then the second amorphous silicon layer 12b and the n + layer 12c are sequentially deposited again.

That is, the thin film transistor using the self-crystallized semiconductor layer comprises a substrate 10, a buffer layer 11 formed on the entire surface of the substrate 10, a crystalline silicon layer 12a on the buffer layer 11, A semiconductor layer 12 formed of a laminate of an amorphous silicon layer 12b and an n + layer 12c and patterned in a predetermined region on the substrate 10; a source electrode 12 formed on both sides of the semiconductor layer 12; A gate insulating film 14 formed on the entire surface including the gate electrode 13b and the drain electrode 13a and the source and drain electrodes 13b and 13a and the gate insulating film 14 corresponding to the center of the gate insulating film 14. [ And a gate electrode 15 formed on the gate electrode 15.

In a display device using such a thin film transistor, a protective film 16 formed on the gate insulating film 14 including the gate electrode 15 and a predetermined portion of the protective film 16 and the gate insulating film 14 And a pixel electrode 17 which is exposed in a portion of the drain electrode 13a and which is buried in the contact and makes contact with the drain electrode 13a.

The semiconductor layer 12 defines a region between the source / drain electrodes 13b / 13a as a channel, and the n + layer 12c corresponding to the channel and the second amorphous silicon layer (12b) is removed.

During the formation of the semiconductor layer using the self-crystallization method, the second amorphous silicon layer 12b and the n + layer 12c are continuously deposited after the AMFC crystallization.

After the formation of the source / drain electrodes, the thickness of the gate insulating layer 14 is adjusted to the thickness of the source / drain electrodes 13b / 13a, the n + layer (the impurity layer The first amorphous silicon layer 12c, the second amorphous silicon layer 12b and the crystalline silicon layer 12a crystallized in the magnetic field crystallization method, The thickness of the gate insulating film 14 of the device including the semiconductor layer is relatively higher than that of the thin film transistor including the semiconductor layer formed by another method. That is, in the case of a thin film transistor using a magnetic field crystallization semiconductor layer, there is some limit in reducing the thickness of the gate insulating film.

3A and 3B are graphs showing device characteristics of the thin film transistor according to the thickness of the gate insulating film of the self-crystallizing semiconductor layer.

FIG. 3A is a graph showing the device characteristics of the thin film transistor when the thickness of the gate insulating film is 1500 ANGSTROM, and FIG. 3B is a graph showing the device characteristics of the thin film transistor when the gate insulating film is 2500 ANGSTROM.

As can be seen from the graphs, when the gate insulating film thickness is thin, the area of the sub-threshold voltage is smaller than that of the thick gate insulating film. When the device thickness is thick, the device characteristics of the thin film transistor are stabilized The results are shown in Fig.

In the above-mentioned graphs, the magnetic field crystallization semiconductor layer (AMFC) has a very characteristic dependency on the gate insulating film thickness, and in particular, it has an extreme device performance difference in the sub-threshold region. Particularly, when such a thin film transistor is used for a thin film transistor for driving an organic electroluminescent element having a large driving current, it can be considered that the thickness of the above-described gate insulating film greatly affects the device characteristics. Therefore, it is necessary to develop a device structure for lowering the thickness of the gate insulating film without causing process problems.

However, the conventional method of forming a thin film transistor using the semiconductor layer crystallized by the self-crystallization has the following problems.

An amorphous silicon layer and an impurity layer to be used as an offset barrier are deposited after AMFC (Alternating Magnetic Field Crystallization) crystallization.

As described above, there is a discontinuous interface at the interface between the amorphous silicon layer formed to prevent offsetting again and the crystallized AMFC layer below the crystallized AMFC layer. As a result, the electron mobility of the semiconductor layer And the electrical characteristics of the thin film transistor using the thin film transistor are deteriorated.

In addition, the magnetic field crystallization semiconductor layer (AMFC) has a very characteristic dependence on the thickness of the gate insulating film. Particularly, in the sub-threshold region, the AMFC has extreme device performance differences. Particularly, when such a thin film transistor is used for a thin film transistor for driving an organic electroluminescence element having a large driving current, it can be considered that the thickness of the gate insulating film greatly affects the device characteristics. However, in the case of a thin film transistor including a semiconductor layer crystallized by a general self-crystallization method, the gate insulating film substructure includes a semiconductor layer, a source / drain electrode, and the like. In order to ensure sufficient step coverage, There is a limit to reducing the thickness. Therefore, it is necessary to develop a device structure for lowering the thickness of the gate insulating film without causing process problems. Conventionally, since the thickness of the gate insulating film has to be set to about 1.5 times the thickness of the lower structure for stabilizing step coverage, it has been difficult to lower the thickness to about 3000 ANGSTROM or less. As a result, the characteristics of the thin film transistor were lowered by the increased gate insulating film thickness.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which comprises the steps of defining a channel region separately from formation of a source / drain electrode, The present invention also provides a method of manufacturing a thin film transistor and a method of manufacturing the same using the same.

The thin film transistor of the present invention for achieving the above object, a semiconductor layer comprising a crystalline silicon layer formed on the substrate by a magnetic field crystallization method and an impurity layer formed on both sides of the crystalline silicon layer; and the impurities of the semiconductor layer Source / drain electrodes formed in contact with the layer; And a gate electrode formed on the center of the semiconductor layer and formed on the same layer as the source / drain electrode through a gate insulating layer.

The gate insulating film is formed to have a larger width than the gate electrode, and the gate electrode is formed on the gate insulating film.

In addition, the manufacturing method of the thin film transistor of the present invention for achieving the same object, the step of depositing a first amorphous silicon layer on a substrate, and applying a magnetic field to the substrate to form a crystallized silicon layer; and the crystallized silicon Depositing an impurity layer and a second amorphous silicon layer on the layer in turn; and forming a semiconductor layer by etching the second amorphous silicon layer, the impurity layer, and the crystalline silicon layer in the same width; and Removing portions of the crystallized silicon layer, the impurity layer, and the second amorphous silicon layer to define a channel portion in a central portion thereof; and forming a gate insulating layer on the semiconductor layer; And depositing a metal layer on the entire surface including the semiconductor layer and the gate insulating layer and selectively removing the metal layer to form a source electrode and a drain electrode partially contacting the impurity layer on both sides of the semiconductor layer, and forming a gate electrode on the gate insulating layer. It is characterized by what is done including the steps.

Here, the gate insulating film is 1000 ~ 2000Å or less.

The gate insulating film is preferably SiO2. And etching the second amorphous silicon layer, the impurity layer, and the crystallized silicon layer with the same width to form a semiconductor layer, and defining the channel portion in the center of the semiconductor layer, wherein the crystallized silicon layer, the impurity layer, and the second layer are defined. Removing a portion of the thickness of the amorphous silicon layer may be performed using the same mask to reduce the mask in the process.

The forming of the gate insulating layer is performed by forming a width smaller than a gap between the source / drain electrodes.

In addition, the manufacturing method of the display device of the present invention for achieving the same object, the step of depositing a first amorphous silicon layer on a substrate, and applying a magnetic field to the substrate to form a crystallized silicon layer; and the crystallized silicon Depositing an impurity layer and a second amorphous silicon layer on the layer in turn; and forming a semiconductor layer by etching the second amorphous silicon layer, the impurity layer, and the crystalline silicon layer in the same width; and Removing partial thicknesses of the crystalline silicon layer, the impurity layer, and the second amorphous silicon layer to define a channel portion in a central portion thereof; forming a gate insulating film on the semiconductor layer; and forming the semiconductor layer and the gate insulating film. Deposition of a metal layer on the front surface including and selectively remove it, so formed in contact with the impurity layer on both sides of the semiconductor layer Forming a gate electrode on the gate insulating film including an electrode and a drain electrode and the gate insulating film; and forming a protective film on the gate insulating film including the gate electrode and a source / drain electrode; and selectively removing the protective film. Forming a contact hole exposing the drain electrode; And filling the contact hole, and forming a pixel electrode connected to the drain electrode.

In addition, the manufacturing method of the display device of the present invention for achieving the same object, the step of depositing a first amorphous silicon layer on a substrate, and applying a magnetic field to the substrate to form a crystallized silicon layer; and the crystallized silicon Depositing an impurity layer and a second amorphous silicon layer on the layer in turn; and forming a semiconductor layer by etching the second amorphous silicon layer, the impurity layer, and the crystalline silicon layer in the same width; and Removing portions of the crystallized silicon layer, the impurity layer, and the second amorphous silicon layer to define a channel portion in a central portion thereof; Forming a second transparent electrode pattern; and depositing a metal layer on the entire surface including the semiconductor layer and the gate insulating layer and selectively removing the metal layer. Forming a source electrode and a drain electrode on both sides of the semiconductor layer in contact with the impurity layer, and forming a gate electrode on the gate insulating layer at the center of the semiconductor layer; and forming the gate electrode and the source / drain electrode Forming a protective film on the gate insulating film, the first contact hole exposing the drain electrode by selectively removing the protective film, and forming a second contact hole exposing a second transparent electrode pattern on the substrate; Making; And forming a pixel electrode connected to the drain electrode through the first contact hole.

The method of manufacturing a thin film transistor of the present invention and the method of manufacturing a display using the same have the following effects.

First, a source / drain electrode and a gate electrode are formed on the same layer, and the gate insulating film is formed on a semiconductor layer without a step below the gate electrode, so that step coverage can be secured even by a small thickness when forming the gate insulating film. . As a result, the thickness of the gate insulating film can be reduced to 2000 GPa or less, preferably 1500 GPa or less. As a result, the characteristics of the thin film transistor can be improved.

Second, when used in a display device, the transparent electrode pattern may be patterned together with the gate insulating layer to omit a drain electrode in the pixel area, form a transparent electrode pattern, and increase an opening width.

Third, the number of times of use of the mask can be reduced by forming the gate electrode, the source electrode, and the drain electrode on the same layer.

FIGS. 4A and 4B are cross-sectional views illustrating a channel forming method and a gate electrode forming method of an example self-crystallizing semiconductor layer, and FIGS. 5A and 5B are plan views of FIGS. 4A and 4B.

As shown in FIGS. 4A and 5A, the semiconductor layer is formed by an example of the self-crystallization method. The buffer layer 51 and the first amorphous silicon layer are sequentially deposited on the substrate 50 firstly, and a magnetic field is applied thereto. The first amorphous silicon layer is crystallized at a predetermined temperature to form the crystalline silicon layer 52a, and then the second amorphous silicon layer 52b and the n + layer 52c are successively deposited.

Next, the semiconductor layers 53, 52b, and 52a are defined by selectively removing the n + layer 52c, the second amorphous silicon layer 52b, and the crystalline silicon layer 52a.

Next, a metal layer is deposited on the buffer layer 51 including the semiconductor layers 53, 52b and 52a, and a photoresist layer is deposited on the metal layer, followed by exposure and development to form a photoresist pattern 55 .

Using the photoresist pattern 55 as a mask, the metal layer is selectively removed to form source / drain electrodes source / drain electrodes 54a / 54b corresponding to both sides of the semiconductor layer and in contact with the n + layer 52c. do.

Then, the thickness of the upper part of the n + layer 53, the second amorphous silicon layer 52b and the crystalline silicon layer 52a of the semiconductor layer exposed under the source / drain electrodes 54a / 54b is removed, ≪ / RTI > Here, the channel width is the same as the separation between the source electrode 52a and the drain electrode 52b. In this case, a reference numeral 63 denotes a semiconductor layer in which a channel is completely defined and patterned.

The gate insulating layer 56 is formed on the entire surface of the buffer layer 51 including the source / drain electrodes 54a / 54b and the semiconductor layer 63, as shown in FIGS. 4B and 5B.

Subsequently, a metal layer is deposited on the gate insulating layer 56 and selectively removed to form a gate electrode 57 partially overlapping the source / drain electrodes 54a / 54b.

That is, in this manufacturing method, since the thin film transistor is defined with the channels at the time of forming the source / drain electrodes 54a / 54b, the thickness of the crystalline silicon layer 52a located at both sides of the channel at the boundary between the channel and the both sides of the channel is defined. Since the step difference occurs by the thickness of the sum of the second amorphous silicon layer 52b, the n + layer 53, and the source / drain electrodes 54a / 54b, the gate insulating film 56 must be formed to a sufficient thickness. In addition, in the gate electrode 57 patterned thereon, it was necessary to form an overlap with some source / drain electrodes 54a / 54b past the stepped portion for sufficient and stable patterning.

In the thin film transistor of the present invention, a method of manufacturing the same, and a method of manufacturing a display device using the same, a source / drain electrode and a gate electrode are formed on the same layer, and they do not overlap, and a gate insulating film is formed on the flat semiconductor layer under the gate electrode. The present invention proposes a structure capable of having a stable step coverage structure even when the gate insulating film is deposited to a small thickness.

Hereinafter, a thin film transistor of the present invention, a method of manufacturing the same, and a method of manufacturing a display using the same will be described in detail with reference to the accompanying drawings.

First Embodiment

FIGS. 6A and 6B are cross-sectional views illustrating a channel forming method and a gate electrode forming method of a self-crystallizing semiconductor layer in a method for manufacturing a thin film transistor according to a first embodiment of the present invention. FIGS. 7A and 7B are cross- Fig.

6A and 7A, the formation of a thin film transistor having a semiconductor layer by a self-crystallization method according to the first embodiment of the present invention is performed by forming a buffer layer 101 and an amorphous silicon layer And the n + layer 102b are sequentially deposited on the crystalline silicon layer 102a after the amorphous silicon layer 102a is crystallized at a predetermined temperature by applying a magnetic field to the amorphous silicon layer 102a.

Next, the semiconductor layer 102 is defined by selectively removing the n + layer 102b and the crystalline silicon layer 102a.

Subsequently, a photosensitive film is coated on the buffer layer 101 including the semiconductor layer 102 so as to have a channel length 'L' of the semiconductor layer 102, and the photosensitive layer is exposed and developed to have a 'L' corresponding to the channel. The photosensitive film pattern 103 from which the width is removed is formed.

Subsequently, partial thicknesses of the n + layer 102b and the crystalline silicon layer 102a are removed using the photoresist pattern 103 as a mask.

As shown in FIGS. 6B and 7B, an insulating film is deposited on the buffer layer 101 including the semiconductor layer 102 and selectively removed so that the gate insulating film 104 remains only partially above the center of the semiconductor layer 102. To form.

Subsequently, a metal layer is deposited on the buffer layer 101 including the gate insulating layer 104 and the semiconductor layer 102, the photoresist layer is entirely deposited on the metal layer, and the photoresist layer is exposed and developed to expose the photoresist pattern (not shown). Form.

By using the first photoresist pattern as a mask, the metal layer is selectively removed to form a gate electrode 105a on the gate insulating layer 104, and a source contacting the n + layer 102b of the semiconductor layer 102. Drain electrodes 102a / 102b are formed.

That is, in the method for manufacturing the thin film transistor of the present invention, the source / drain electrodes and the gate electrode are formed using the same mask of the same layer, and the gate insulating film is selectively formed only on the center of the semiconductor layer. Compared to the structure, it is possible to secure step coverage, whereby the gate insulating layer 106 can be formed to a low thickness.

Hereinafter, a method of manufacturing a display device including a method of manufacturing a thin film transistor according to a first embodiment of the present invention will be described in detail.

8A to 8L are process cross-sectional views illustrating a method of manufacturing a display device according to a first embodiment of the present invention. 9 is a plan view of a display device including a thin film transistor according to a first exemplary embodiment of the present invention.

The manufacturing method of the display device according to the first embodiment of the present invention is performed in the following procedure.

First, as shown in FIG. 8A, a buffer layer 101 and an amorphous silicon layer 112 made of an oxide film (SiO 2) are sequentially deposited on the substrate 100. Here, the deposition of the buffer layer 101 and the amorphous silicon layer 112 on the substrate 100 in sequence is successively deposited by plasma enhanced chemical vapor deposition (PECVD) equipment.

As shown in FIG. 8B, a magnetic field is applied to the substrate 100 to crystallize the amorphous silicon layer 112 to form the crystalline silicon layer 112a.

As illustrated in FIG. 8C, an n + layer 113 is formed on the crystalline silicon layer 112a. The n + layer 113 may be formed after further depositing an amorphous silicon layer on the crystalline silicon layer 112a.

As shown in FIG. 8D, a photoresist film is coated on the n + layer 113 and the crystalline silicon layer 112a and developed and exposed by a first mask (not shown) to form a first photoresist pattern 123. The n + layer 113 and the crystalline silicon layer 112a are selectively removed as a mask to form an n + layer pattern 113a and a crystalline silicon layer pattern 112b having the same width.

Next, the first photoresist pattern 123 is removed.

As shown in FIG. 8E, a front photosensitive film is coated on the buffer layer 101 including the n + layer pattern 113a and the crystalline silicon layer pattern 112b and selectively removed, and the center portion of the n + layer pattern 113a is removed. The second photosensitive film pattern 103 is formed to be exposed.

Subsequently, the second photoresist layer pattern 103 is used as a mask to dry-etch to remove portions of the n + layer pattern 113a and the crystalline silicon layer pattern 112b. As a result, the semiconductor layer 102 of the laminate of the crystalline silicon layer pattern 102a and the ohmic contact layer 102b, the upper thickness of which is partially removed, is formed.

As shown in FIG. 8F, an insulating film 104a is deposited on the buffer layer 101 including the semiconductor layer 102 and selectively removed, so that the semiconductor layer 102 partially remains only at the center of the semiconductor layer 102 as shown in FIG. 8G. The gate insulating film 104 is formed. At this time, the gate insulating film 104 is preferably made of SiO2, and formed to a thickness of about 1000 ~ 2000Å.

As shown in FIG. 8H, a metal layer 105 is deposited on the buffer layer 101 including the gate insulating layer 104 and the semiconductor layer 102, and a photoresist film is entirely deposited on the metal layer, and the photoresist film is exposed and developed. A pattern (not shown) is formed.

Using the photoresist pattern as a mask, the metal layer is selectively removed to form a gate electrode 105a on the gate insulating layer 104, and a source / drain in contact with the n + layer 102b of the semiconductor layer 102. Electrodes 105b / 105c are formed.

In this process, the thin film transistor according to the first embodiment including the gate electrode 105a, the source / drain electrodes 105b / 105c, and the semiconductor layer 102 crystallized by the AMFC method is defined.

Here, the thin film transistor may be used as a driving device for driving each pixel such as a liquid crystal display device or an organic light emitting device, and display is performed through a pixel electrode connected to the thin film transistor.

Hereinafter, a method for forming a pixel electrode for driving each pixel of a display device by adding another process to the above-described process will be described.

As shown in FIG. 8J, the passivation layer 106 is formed on the entire surface including the gate electrode 105a, the source electrode 105b, and the drain electrode 105c.

As shown in FIG. 8K, after the photoresist is coated on the entire surface of the passivation layer 106, the photoresist layer is selectively removed using a fifth mask (not shown) to form a photoresist pattern. The passivation layer 106 is formed using the photoresist pattern. ) Is selectively removed to form a passivation layer pattern 106a to expose a portion of the drain electrode 105c, and a contact hole C is defined in an exposed portion of the drain electrode 105c.

As shown in FIG. 8L, the contact hole C is filled, a transparent electrode material is deposited on the entire surface of the passivation layer pattern 106a, and then a photosensitive layer is coated on the upper portion of the protective layer pattern 106a and patterned by a sixth mask (not shown). Thereafter, the transparent electrode material is patterned to form a pixel electrode 107 electrically connected to the drain electrode 105c.

FIG. 9 applies the above-described method for manufacturing a display device to an organic light emitting element, and is used for a method for manufacturing a driving thin film transistor formed on a line I to I '.

125 is a scan line, 125c represents a scan gate electrode, and a select thin film transistor is further formed around the scan gate electrode 125c. At this time, the source side of the selected thin film transistor is in contact with the voltage applying line 127 through the source electrode 133a and the contact C4, and the drain side is formed through the drain electrode and the connection pattern 137. Electrically connected to 105a).

- Second Embodiment -

Hereinafter, a method of manufacturing a display device including a method of manufacturing a thin film transistor according to a second exemplary embodiment of the present invention will be described.

10 is a plan view of a display device including a thin film transistor according to a second exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line II to II 'of FIG. 10.

10 and 11, in the display device including the thin film transistor according to the second exemplary embodiment of the present invention, the crystalline silicon layer 202a and the crystalline silicon layer 202a formed on the substrate 200 by magnetic field crystallization method. The semiconductor layer 202 including the impurity layer 202b formed on both sides, the source / drain electrodes 205b and 205c formed in contact with the impurity layer 202b of the semiconductor layer 202, and the semiconductor layer 202. The gate electrode 205a is formed on the center and formed on the same layer as the source / drain electrodes 205b / 205c via the gate insulating film 203. The drain electrode 205c is formed to have a smaller width, the second transparent electrode pattern 204a is formed in the pixel region, and the drain electrode 205c and the pixel electrode 207 are formed in a first passivation layer hole. Only the upper part of CC1 has a contact.

FIG. 11 applies the above-described display device structure of FIG. 10 to an organic light emitting element, and is used in a method of manufacturing a driving thin film transistor formed on a line II to II '. Additional reference numeral 225 denotes a scan line, 225a denotes a scan gate electrode, and a selection thin film transistor is further formed around the scan gate electrode 225c. At this time, the source side of the selected thin film transistor is in contact with the voltage application line 227 through the source electrode 233a, and the drain side is connected to the first and second contacts CC1, through the drain electrode 233b and the connection pattern. CC2) and is electrically connected to the gate electrode 205a of the driving thin film transistor shown in FIG.

12A and 12O are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present invention, and FIGS. 13A to 13K are process plan views illustrating a manufacturing method of a display apparatus according to a second exemplary embodiment of the present invention. to be.

A manufacturing method of a display device according to a second embodiment of the present invention is performed in the following procedure.

First, as shown in FIGS. 12A and 13A, a buffer layer 201 and an amorphous silicon layer 212 including an oxide film SiO 2 are sequentially deposited on the substrate 200. Here, depositing the buffer layer 201 and the amorphous silicon layer 212 on the substrate 200 in sequence may be successively deposited by plasma enhanced chemical vapor deposition (PECVD) equipment.

12B and 13B, a magnetic field is applied to the substrate 200 to crystallize the amorphous silicon layer 212 to form a crystalline silicon layer 212a.

12C and 13C, an n + layer 213 is formed on the crystalline silicon layer 212a. Here, the n + layer 213 may be formed after further depositing an amorphous silicon layer on the crystalline silicon layer 212a.

12D and 13D, a photoresist film is coated on the n + layer 213 and the crystalline silicon layer 212a and developed and exposed by a first mask (not shown) to form the first photoresist film pattern 222. do.

The first photoresist layer pattern 222 may include a first photoresist layer pattern 222 having a channel defining portion of the semiconductor layer as a first height portion and source / drain electrode defining portions at both sides thereof as a second height portion (> first height portion). ).

12E and 13E, the n + layer pattern 213a and the crystalline silicon layer 212a are selectively removed by first removing the n + layer 213 and the crystalline silicon layer 212a using the first photoresist pattern 222 as a mask. And a crystalline silicon layer pattern 212b.

12F and 13F, the first photoresist layer pattern 222 is abutted to form a second photoresist layer pattern 222a such that the first height portion is removed.

12G and 13G, by using the second photoresist layer pattern 222a as a mask, partial thicknesses of the n + layer pattern 213a and the crystalline silicon layer pattern 212b are removed to form an ohmic layer of the semiconductor layer 202. The contact layer 202b and the crystalline silicon layer pattern 202a are formed.

12H and 13H, the second photoresist layer pattern 222a is stripped and removed.

12I and 13I, an insulating film 223 and a transparent electrode layer 204 are sequentially deposited on the buffer layer 201 including the semiconductor layer 202.

12J and 13J, the gate insulating layer 203 and the first transparent electrode pattern 204b formed in an island shape on the semiconductor layer 202 by removing the transparent electrode layer 204 and the insulating layer 223 in the same width. To form. In this case, the gate insulating layer 203 and the second transparent electrode pattern 204a are formed on the buffer layer 201 except for the semiconductor layer 202. In this case, a portion where the second transparent electrode pattern 204a is formed is a portion where the pixel electrode is formed in the display device.

As shown in FIG. 12J, a metal layer 205 is deposited on the buffer layer 201 including the first and second transparent electrode patterns 204b and 204a and the semiconductor layer 202, and a photoresist film is entirely deposited on the metal layer. Then, it is exposed and developed to form a photoresist pattern (not shown).

As shown in FIG. 12K, the metal layer is selectively removed using the photoresist pattern as a mask to form a gate electrode 205a in contact with the first transparent electrode pattern 204b, and n + of the semiconductor layer 202 is formed. Source / drain electrodes 205b / 205c are formed in contact with layer 202b.

In this process, the thin film transistor according to the second embodiment including the gate electrode 205a, the source / drain electrodes 205b / 205c, and the semiconductor layer 202 crystallized by the AMFC method is defined.

Here, the thin film transistor may be used as a driving device for driving each pixel such as a liquid crystal display device or an organic light emitting device, and display is performed through a pixel electrode connected to the thin film transistor.

Hereinafter, a method for forming a pixel electrode for driving each pixel of a display device by adding another process to the above-described process will be described.

As shown in FIG. 12M, the passivation layer 216 is formed on the entire surface including the gate electrode 205a, the source electrode 205b, and the drain electrode 205c.

As shown in FIG. 12N, after the photoresist is coated on the entire surface of the passivation layer 216, the photoresist layer is selectively removed using a fourth mask (not shown) to form a photoresist pattern. Passivation layer pattern 206 having a second contact hole C at an exposed portion of the first passivation layer CC1 and the drain electrode 105c to selectively remove a portion thereof to expose a portion of the drain electrode 205c. To form.

As shown in FIG. 12O, the first passivation layer hole CC1 is buried, a transparent electrode material is deposited on the entire passivation layer pattern 206, and then a photoresist layer is coated on the passivation layer. After patterning, the transparent electrode material is patterned accordingly to form a pixel electrode 207 electrically connected to the drain electrode 205c.

The top gate type AMFC (self-crystallizing semiconductor layer) is formed in the amorphous silicon forming process by merely adding a magnetic field crystallization process to the amorphous silicon thin film transistor. It is possible to realize a device with high reliability.

As described above, it is possible to ensure excellent uniformity over the laser crystallized semiconductor layer through the magnetic-field-crystallized semiconductor layer, which can be used when an active matrix organic light-emitting device or a drive IC is formed in the panel. As a result, a narrow bezel can be realized with superior device performance and reliability as compared with a thin film transistor using a semiconductor layer made of a conventional amorphous silicon layer, and more circuits can be integrated.

 In addition, in the method for manufacturing a thin film transistor of the present invention, after crystallizing an amorphous silicon layer for magnetic field crystallization, depositing an impurity layer and patterning the semiconductor layer, patterning a source / drain electrode and a gate electrode on the same layer at the same time, The gate insulating film is formed only on the semiconductor layer below the gate electrode, and the step coverage is reduced even when the gate insulating film is deposited to a low thickness by reducing the step in the formation region of the gate insulating film.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1A is a cross-sectional view of a conventional amorphous silicon thin film transistor

1B is a cross-sectional view showing the structure of the semiconductor layer of FIG. 1A

2A is a cross-sectional view showing a thin film transistor having a self-crystallizing semiconductor layer

FIG. 2B is a cross-sectional view showing the structure of the semiconductor layer of FIG. 2A

3A and 3B are graphs showing the device characteristics of the thin film transistor according to the thickness of the gate insulating film of the self-crystallizing semiconductor layer

FIGS. 4A and 4B are cross-sectional views showing a channel forming process and a gate electrode forming process of an example self-crystallizing semiconductor layer

Figs. 5A and 5B are plan views of Figs. 4A and 4B

6A and 6B are cross-sectional views illustrating a channel formation process and a gate electrode formation process of a self-crystallizing semiconductor layer in a method of manufacturing a thin film transistor according to a first embodiment of the present invention

Figs. 7A and 7B are plan views of Figs. 6A and 6B

8A to 8L are cross-sectional views showing the manufacturing method of the display device according to the first embodiment of the present invention

9 is a plan view of a display device including a thin film transistor according to a first exemplary embodiment of the present invention.

10 is a plan view of a display device including a thin film transistor according to a second exemplary embodiment of the present invention.

FIG. 11 is a structural cross-sectional view taken along line II-II ′ of FIG. 10.

12A and 12O are cross-sectional views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present invention.

13A to 13K are process plan views illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE CHARACTERS

100, 200: substrate 101, 201: buffer layer

102, 202: semiconductor layer 104: gate insulating film

105a, 205a: gate electrode 105b, 205b: source electrode

105c and 205c: drain electrodes 104 and 203: gate insulating film

106 and 206: protective films 107 and 207: pixel electrodes

Claims (9)

A semiconductor layer comprising a crystalline silicon layer formed on the substrate by a magnetic field crystallization method and an impurity layer formed on both sides of the crystalline silicon layer; A source / drain electrode formed in contact with the impurity layer of the semiconductor layer; And And a gate electrode formed on the center of the semiconductor layer, the gate electrode being formed on the same layer as the source / drain electrode via a gate insulating film. The method according to claim 1, The gate insulating film has a width greater than that of the gate electrode, and the gate electrode is formed on the gate insulating film, the thin film transistor. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Removing some thicknesses of the crystalline silicon layer, the impurity layer, and the second amorphous silicon layer so as to define a channel portion in a central portion of the semiconductor layer; Forming a gate insulating film on the semiconductor layer; And Depositing and selectively removing a metal layer on the entire surface including the semiconductor layer and the gate insulating layer to form a source electrode and a drain electrode partially contacting the impurity layer on both sides of the semiconductor layer, and forming a gate electrode on the gate insulating layer Method for manufacturing a thin film transistor comprising a. The method of claim 3, Wherein the gate insulating layer has a thickness of 1000 to 2000 ANGSTROM or less. The method of claim 3, Wherein the gate insulating film is SiO2. The method of claim 3, Etching the impurity layer and the crystalline silicon layer with the same width to form a semiconductor layer, and removing a portion of the thickness of the impurity layer and the crystalline silicon layer so as to define a channel portion in the center of the semiconductor layer The manufacturing method of the thin film transistor characterized by the above-mentioned. The method of claim 3, The forming of the gate insulating film is a method of manufacturing a thin film transistor, characterized in that formed in a width smaller than the gap between the source / drain electrode. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Removing some thicknesses of the impurity layer and crystalline silicon so as to define a channel portion in a central portion of the semiconductor layer; Forming a gate insulating film on the semiconductor layer; Depositing and selectively removing a metal layer on the entire surface including the semiconductor layer and the gate insulating layer to form a source electrode and a drain electrode partially contacting the impurity layer on both sides of the semiconductor layer, and forming a gate electrode on the gate insulating layer ; Forming a passivation layer on the gate insulating layer including the gate electrode and a source / drain electrode; Selectively removing the passivation layer to form a contact hole exposing the drain electrode; And And filling the contact hole with the drain electrode to form a pixel electrode connected to the drain electrode. Depositing an amorphous silicon layer on a substrate and applying a magnetic field to the substrate to form a crystallized silicon layer; Depositing an impurity layer on the crystallized silicon layer; Forming a semiconductor layer by etching the impurity layer and the crystallized silicon layer to the same width; Removing some thicknesses of the impurity layer and the crystalline silicon layer so as to define a channel portion in a central portion of the semiconductor layer; Forming a gate insulating film and first and second transparent electrode patterns on the substrate except for the semiconductor layer and the semiconductor layer; Depositing a metal layer on the entire surface including the semiconductor layer and the gate insulating layer and selectively removing the metal layer, and forming a source electrode and a drain electrode on both sides of the semiconductor layer in contact with the impurity layer; Forming a gate electrode; Forming a passivation layer on the gate insulating layer including the gate electrode and a source / drain electrode; Selectively removing the passivation layer to form a first passivation layer hole exposing the drain electrode and a second passivation layer hole exposing a second transparent electrode pattern on the substrate; And And forming a pixel electrode connected to the drain electrode through the first passivation layer hole.

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