CN103258745A - Thin film transistor, manufacturing method of thin film transistor, array substrate and display device - Google Patents

Thin film transistor, manufacturing method of thin film transistor, array substrate and display device Download PDF

Info

Publication number
CN103258745A
CN103258745A CN201310133306XA CN201310133306A CN103258745A CN 103258745 A CN103258745 A CN 103258745A CN 201310133306X A CN201310133306X A CN 201310133306XA CN 201310133306 A CN201310133306 A CN 201310133306A CN 103258745 A CN103258745 A CN 103258745A
Authority
CN
China
Prior art keywords
layer
active layer
etching
etching barrier
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310133306XA
Other languages
Chinese (zh)
Inventor
任庆荣
郭炜
卜倩倩
赵磊
王路
姜志强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201310133306XA priority Critical patent/CN103258745A/en
Priority to PCT/CN2013/080280 priority patent/WO2014169544A1/en
Priority to US14/342,234 priority patent/US20150295094A1/en
Publication of CN103258745A publication Critical patent/CN103258745A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers

Abstract

The invention discloses a thin film transistor, a manufacturing method of the thin film transistor and a display device, and relates to the field of display. The problems of uneven etching, incomplete etching, over-etching and the like during interlayer through hole forming are resolved and technology reject ratio is lowered. The manufacturing method of the array substrate comprises the steps of forming an active layer, and after the active layer is formed, forming an etching blocking layer at the position, where an interlayer through hole is formed subsequently, on the active layer to protect the active layer during the process of etching the interlayer through hole. The active layer is connected with a source and a leakage electrode through the interlayer through hole.

Description

Thin-film transistor and preparation method thereof, array base palte, display unit
Technical field
The present invention relates to the demonstration field, relate in particular to a kind of thin-film transistor and preparation method thereof, array base palte, display unit.
Background technology
Existing display is many based on amorphous silicon (a-si), be that (Thin Film Transistor TFT) adopts amorphous silicon materials more, but by contrast for the thin-film transistor of display floater, polysilicon (Poly-Si) has higher electron mobility, is considered to the TFT better than amorphous silicon and makes material.
As shown in Figure 1, existing polysilicon array base palte comprises from bottom to top successively: substrate 10, be arranged on the resilient coating 11 (SiO on the substrate 10 x/ SiN xLaminated construction), polysilicon active layer 12, gate insulation layer 13, grid 14 and interlayer insulating film (ILD) 15, also comprise the source leakage source metal layer drain electrode (not shown) that is arranged on the interlayer insulating film 15, the source is leaked the source metal layer drain electrode and is contacted conducting by interlevel via 100 with polysilicon active layer 12.Wherein, interlayer insulating film 15 also needs high visible light transmissive degree except needs good coverage property and insulation effect, and in order to reach above purpose and to keep out external steam and the mechanicalness scratch, interlayer insulating film more than 15 adopts SiO x, SiN xThe perhaps laminated construction SiO of the two x/ SiN xAs interlayer insulating film.The SiO of employing in concrete the enforcement more x/ SiN xLaminated construction, except having pretty good electrology characteristic, and, the preparation SiN xThe working gas of layer comprises hydrogen, therefore forms SiN xAlso have in the time of layer existing rete is carried out hydrotreated effect.
When forming interlevel via 100, the inventor finds prior art, and there are the following problems at least:
Because interlayer insulating film 15 is generally thicker, and is laminated construction, add when forming interlevel via 100, except etching interlayer insulating film 15, also need etching gate insulation layer 13, rete to be etched is blocked up, and compares SiO with polysilicon xThe etching difficulty is a lot of greatly, be difficult to debug out the two splendid selective etching during physical etchings and compare technology, and the polysilicon of active layer is thinner, the zone that often has there is not etching saturating, the zone that has serious over etching again causes active layer to damage, have a strong impact on the product yield, and the application of low temperature polycrystalline silicon technology on large scale shows.
Summary of the invention
The invention provides a kind of thin-film transistor and preparation method thereof, array base palte, display unit, can solve when forming interlevel via, etching is inhomogeneous, do not have problems such as etching is saturating, overetch, reduces the technology fraction defective.
For solving the problems of the technologies described above, on the one hand, the invention provides a kind of film crystal tube preparation method, comprising: form active layer, after the described formation active layer, also comprise:
The position of follow-up formation interlevel via forms etching barrier layer on described active layer, in order to protect described active layer when the described interlevel via of etching;
Described active layer is connected by described interlevel via with source, drain electrode.
Further, the position of follow-up formation interlevel via forms etching barrier layer on described active layer, after protecting described active layer when the described interlevel via of etching, also comprises:
Form gate insulation layer at the active layer that is provided with etching barrier layer;
Form grid at described gate insulation layer;
On described grid, form interlayer insulating film;
The described gate insulation layer of the described interlayer insulating film of etching and below forms described interlevel via.
Alternatively, described etching barrier layer is the semiconductor film of metallic diaphragm or doping.
Preferably, described etching barrier layer adopts identical material with described source-drain electrode.
Alternatively, described etching barrier layer is a kind of in molybdenum film, aluminum metal film, the copper metal film, perhaps,
A kind of in stepped construction titanium/aluminium/titanium and the stepped construction molybdenum/aluminium neodymium/molybdenum.
Preferably, described active layer is polysilicon active layer.
Particularly, described formation active layer specifically comprises:
Form resilient coating at substrate;
Form amorphous silicon layer at described resilient coating;
Described amorphous silicon layer is converted into polysilicon layer;
The described polysilicon layer of etching, the active layer of formation TFT;
Mixing in subregion to described active layer, forms the semiconductor doping zone; Perhaps,
Form resilient coating at substrate;
Form amorphous silicon layer at described resilient coating;
Described amorphous silicon layer is converted into polysilicon layer;
Mixing in subregion to described polysilicon layer, forms the semiconductor doping zone;
Polysilicon layer after mixing is carried out etching, form the polysilicon active layer of TFT.
Alternatively, the thickness of described etching barrier layer is
Figure BDA00003061862800031
On the other hand, the present invention also provides a kind of thin-film transistor, comprising: active layer also comprises:
In order to the etching barrier layer of protection active layer when forming interlevel via, be arranged on the position of follow-up formation interlevel via on the described active layer;
Described interlevel via is in order to connect described active layer and source-drain electrode.
Further, described thin-film transistor also comprises:
Gate insulation layer is arranged on described active layer and the described etching barrier layer;
Grid is arranged on the described gate insulation layer;
Interlayer insulating film is arranged on the described grid;
The described gate insulation layer of described interlayer insulating film and below is provided with interlevel via.
Alternatively, described etching barrier layer is the semiconductor film of metallic diaphragm or doping.
Alternatively, described etching barrier layer adopts the material identical with described source-drain electrode.
Alternatively, described etching barrier layer is a kind of in molybdenum film, aluminum metal film, the copper metal film, perhaps,
A kind of in stepped construction titanium/aluminium/titanium and the stepped construction molybdenum/aluminium neodymium/molybdenum.
Alternatively, described active layer is polysilicon active layer.
Alternatively, the thickness of described etching barrier layer is
Figure BDA00003061862800032
The present invention also provides a kind of array base palte, comprises described arbitrary thin-film transistor.
In addition, the present invention also provides a kind of display unit, comprises described arbitrary thin-film transistor.
The invention provides a kind of row substrate and preparation method thereof, array base palte, display unit; the position of follow-up formation interlevel via forms etching barrier layer on active layer; at the etching interlayer insulating film when forming interlevel via; can protect active layer not to be etched; inhomogeneous when having solved the interlayer insulating film etching, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the cross section structure schematic diagram of array base palte;
The flow chart of the film crystal tube preparation method that Fig. 2 provides for the embodiment of the invention one;
Fig. 3 is the structural representation of etching barrier layer on the thin-film transistor in the embodiment of the invention one;
The flow chart of the film crystal tube preparation method that Fig. 4 provides for the embodiment of the invention two;
Fig. 5 is the schematic flow sheet that forms polysilicon active layer in the embodiment of the invention two;
Fig. 6 is the schematic flow sheet that forms etching barrier layer in the embodiment of the invention two;
Fig. 7 is the schematic diagram of gate insulation layer, grid and interlayer insulating film in the embodiment of the invention two;
Fig. 8 is the schematic diagram that forms interlevel via in the embodiment of the invention two.
Description of reference numerals
The 10-substrate, the 11-resilient coating, the 12-polysilicon active layer, the 13-gate insulation layer,
14-grid 15-interlayer insulating film, 100-interlevel via 100, the 120-active layer,
The 121-amorphous silicon layer, the 122-polysilicon layer, the 160-metallic diaphragm, the 16-etching barrier layer,
The 17-photoresist, the 171-etching window.
Embodiment
The invention provides a kind of row substrate and preparation method thereof, display unit, can solve the interlayer insulating film etching inhomogeneous, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.
Embodiment one
The embodiment of the invention provides a kind of film crystal tube preparation method, and shown in Fig. 2 and 3, this method comprises:
101, form active layer 120, after forming active layer 120, also comprise:
102, the position of follow-up formation interlevel via forms etching barrier layer 16 on active layer 120, and in order to protection active layer 120 when the etching interlevel via, described interlevel via (not shown) is in order to connect active layer 120 and source-drain electrode (not shown).
The described interlevel via of present embodiment is the via hole that runs through all retes between active layer 120 and source, the drain electrode, and source electrode, drain electrode are electrically connected by the doped region of interlevel via with active layer 120 respectively.
Preferably, the material of described etching barrier layer 16 should be metal or the doped semiconductor that can conduct electricity, and not being afraid of during etching has residually, could protect active layer 120 not to be damaged when the etching interlevel via like this.Particularly; this step is depositing metal membrane layer (or the semiconductor film of mixing) on active layer 120; form etching barrier layer 16 by photoetching process in the position of follow-up formation interlevel via; etching barrier layer 16 is in order to protection active layer 120 when adopting lithographic method to form interlevel via, so the area of etching barrier layer 16 should be greater than the area of section of interlevel via.
And, etching barrier layer 16 should have enough thickness, can guarantee etching away interlayer insulating film on the active layer 120 fully (for the TFT of top gate structure, then be gate insulation layer and the interlayer insulating film that etches away on the active layer 120) time, do not damage the active layer 120 below the gate insulation layer, but the thickness of etching barrier layer 16 again should not be too thick, in order to avoid the deposition of face mask layer in the too high influence of step that forms, the thickness of etching barrier layer 16 is generally selected described in concrete the enforcement
Figure BDA00003061862800051
The embodiment of the invention provides a kind of row base plate preparation method; the position of follow-up formation interlevel via forms etching barrier layer on active layer; when adopting lithographic method with the formation interlevel via; can protect active layer 120 not to be etched; inhomogeneous when having solved the interlayer insulating film etching, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
Embodiment two
Further, the embodiment of the invention also provides a kind of film crystal tube preparation method, and shown in Fig. 4 and Fig. 5～7, this method specifically comprises:
201, form resilient coating 11 at substrate 10;
202, form amorphous silicon layer 121 at described resilient coating 11;
203, described amorphous silicon layer 121 is converted into polysilicon layer 122;
204, the described polysilicon layer of etching, the active layer 12 of formation TFT;
205, mixed in the subregion of active layer 12, form the semiconductor doping zone;
As shown in Figure 5, alternatively, at first adopt chemical vapour deposition technique (PECVD) deposition resilient coating 11 and amorphous silicon layer 121 in step 201～204, carry out dehydrogenation then, adopt excimer laser crystallization method (ELA) that amorphous silicon layer 121 is converted into polysilicon layer (P-Si) 122 again, by photoetching process polysilicon layer 122 is carried out the active layer etching more at last, utilize photoresist to do mask and carry out source leakage doping, form the active layer 12 of TFT, can certainly carry out source leakage doping earlier and carry out active layer etching (order of these two steps can be changed) again, and then the activation of annealing, activate the doping ion.
Preferably, above-mentioned resilient coating 11 is SiN x/ SiO 2Laminated construction.
206, as shown in Figure 6, depositing metal membrane layer 160, by composition technology, the position of follow-up formation interlevel via forms etching barrier layer 16 on active layer 12;
The described interlevel via of present embodiment is the via hole that runs through gate insulation layer and interlayer insulating film, and the source electrode in the source-drain electrode, drain electrode are electrically connected by the doped region of interlevel via with active layer 120 respectively.
This step forms one deck etching barrier layer 16 in doped polycrystalline silicon layer (active layer 12), in order to protection active layer when the etching interlevel via.Preferably, this etching barrier layer 16 is general to adopt the material identical with source-drain electrode, as molybdenum Mo, aluminium Al, copper Cu etc., and perhaps stepped construction titanium/aluminium/titanium (Ti/Al/Ti), stepped construction molybdenum/aluminium neodymium/molybdenum (Mo/AlNd/Mo) etc.When the etching interlevel via, residual even if etching barrier layer 16 has, can not influence the ohmic contact between source, drain electrode and the active layer yet.
Etching barrier layer 16 is selected the stepped construction titanium of metal such as molybdenum Mo, aluminium Al, copper Cu or metal, etch rate is lower, and etching barrier layer 16 is not afraid of by a spot of over etching like this, be not afraid of yet have residual, so just avoided because the etching homogeneity is bad, and etching selection ratio is not good, and the technology that causes is bad.
207, form gate insulation layer 13 at the active layer 12 that is provided with etching barrier layer 16;
208, form grid 14 at gate insulation layer 13;
209, on grid 14, form interlayer insulating film 15;
As shown in Figure 7, deposition gate insulation layer 13 and gate metal layer are continued at the active layer 12 that is provided with etching barrier layer 16 in step 207～209, form grid 14 by photoetching process, and then continue deposition interlayer insulating film 15.Wherein, gate insulation layer 13 and interlayer insulating film 15 are SiO x/ SiN xLaminated construction, grid 14 forms for Mo metal film etching.
210, the gate insulation layer 13 of etching interlayer insulating film 15 and below forms interlevel via.
As shown in Figure 8, this step applies photoresist 17 at interlayer insulating film 15, after exposure, developing, predeterminated position in interlevel via forms the etching window 171 that photoresist is peeled off fully, and then the interlayer insulating film that etching window 171 places are exposed carries out dry etching, remove the interlayer insulating film 15 at etching window 171 places and the gate insulation layer 13 of below, form interlevel via 100.At last, proceed subsequent handling, formation source, drain electrode, pixel electrode (perhaps pixel electrode and public electrode) and passivation protection layer are finished the preparation of thin-film transistor.
The embodiment of the invention provides a kind of film crystal tube preparation method; the position of follow-up formation interlevel via forms etching barrier layer on polysilicon active layer; when adopting dry etching with the formation interlevel via; can protect polysilicon active layer not to be etched; inhomogeneous when having solved the interlayer insulating film etching, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
Embodiment three
Accordingly, the present invention also provides a kind of thin-film transistor on the other hand, comprising: active layer also comprises:
In order to the etching barrier layer of protection active layer when forming interlevel via, be arranged on the position of follow-up formation interlevel via on the described active layer;
Described interlevel via is in order to connect active layer and source-drain electrode.
Further, described thin-film transistor also comprises:
Gate insulation layer is arranged on described active layer and the described etching barrier layer;
Grid is arranged on the described gate insulation layer;
Interlayer insulating film is arranged on the grid;
Described interlevel via runs through the gate insulation layer of described interlayer insulating film and below.
The embodiment of the invention provides a kind of thin-film transistor; the position of follow-up formation interlevel via is provided with etching barrier layer on the active layer; be not etched in order to protection polysilicon active layer when adopting dry etching to form interlevel via; inhomogeneous in the time of can solving the interlayer insulating film etching, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
Alternatively, described etching barrier layer is the semiconductor film of metallic diaphragm or doping.
Alternatively, described etching barrier layer adopts the material identical with described source-drain electrode.
Alternatively, described etching barrier layer is a kind of in molybdenum film, aluminum metal film, the copper metal film, perhaps,
A kind of in stepped construction titanium/aluminium/titanium and the stepped construction molybdenum/aluminium neodymium/molybdenum.
Alternatively, described active layer is polysilicon active layer.
Alternatively, the thickness of described etching barrier layer is
Figure BDA00003061862800081
In addition, the present invention also provides a kind of array base palte, comprises described arbitrary thin-film transistor.
The present invention also provides a kind of display unit, comprises described arbitrary thin-film transistor.
Array base palte provided by the invention, display unit; the position of follow-up formation interlevel via forms etching barrier layer on active layer; when forming interlevel via; can protect active layer not to be etched; inhomogeneous when having solved the interlayer insulating film etching, do not have problems such as etching is saturating, overetch, reduce the technology fraction defective.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.

Claims (17)

1. the preparation method of a thin-film transistor comprises: form active layer, it is characterized in that, after the described formation active layer, also comprise:
The position of follow-up formation interlevel via forms etching barrier layer on described active layer, in order to protect described active layer when the described interlevel via of etching;
Described active layer is connected by described interlevel via with source, drain electrode.
2. method according to claim 1 is characterized in that, the position of follow-up formation interlevel via forms etching barrier layer on described active layer, after protecting described active layer when the described interlevel via of etching, also comprises:
Form gate insulation layer at the active layer that is provided with etching barrier layer;
Form grid at described gate insulation layer;
On described grid, form interlayer insulating film;
The described gate insulation layer of the described interlayer insulating film of etching and below forms described interlevel via.
3. method according to claim 1 and 2 is characterized in that,
Described etching barrier layer is the semiconductor film of metallic diaphragm or doping.
4. method according to claim 3 is characterized in that,
Described etching barrier layer adopts the material identical with described source-drain electrode.
5. method according to claim 4 is characterized in that, described etching barrier layer is a kind of in molybdenum film, aluminum metal film, the copper metal film, perhaps,
A kind of in stepped construction titanium/aluminium/titanium and the stepped construction molybdenum/aluminium neodymium/molybdenum.
6. method according to claim 1 and 2 is characterized in that,
Described active layer is polysilicon active layer.
7. method according to claim 6 is characterized in that, described formation active layer specifically comprises:
Form resilient coating at substrate;
Form amorphous silicon layer at described resilient coating;
Described amorphous silicon layer is converted into polysilicon layer;
The described polysilicon layer of etching, the active layer of formation TFT;
Mixing in subregion to described active layer, forms the semiconductor doping zone; Perhaps,
Form resilient coating at substrate;
Form amorphous silicon layer at described resilient coating;
Described amorphous silicon layer is converted into polysilicon layer;
Mixing in subregion to described polysilicon layer, forms the semiconductor doping zone;
Polysilicon layer after mixing is carried out etching, form the polysilicon active layer of TFT.
8. method according to claim 1 is characterized in that,
The thickness of described etching barrier layer is
Figure FDA00003061862700021
9. thin-film transistor comprises: active layer, it is characterized in that, and also comprise:
In order to the etching barrier layer at etching interlevel via time protection active layer, be arranged on the position of follow-up formation interlevel via on the described active layer;
Described interlevel via is in order to connect described active layer and source-drain electrode.
10. thin-film transistor according to claim 9 is characterized in that, also comprises:
Gate insulation layer is arranged on described active layer and the described etching barrier layer;
Grid is arranged on the described gate insulation layer;
Interlayer insulating film is arranged on the described grid;
Described interlevel via runs through the gate insulation layer of described interlayer insulating film and below.
11. according to claim 9 or 10 described thin-film transistors, it is characterized in that,
Described etching barrier layer is the semiconductor film of metallic diaphragm or doping.
12. thin-film transistor according to claim 11 is characterized in that,
Described etching barrier layer adopts the material identical with described source-drain electrode.
13. thin-film transistor according to claim 11 is characterized in that, described etching barrier layer is a kind of in molybdenum film, aluminum metal film, the copper metal film, perhaps,
A kind of in stepped construction titanium/aluminium/titanium and the stepped construction molybdenum/aluminium neodymium/molybdenum.
14. according to claim 9 or 10 described thin-film transistors, it is characterized in that,
Described active layer is polysilicon active layer.
15. thin-film transistor according to claim 9 is characterized in that,
The thickness of described etching barrier layer is
Figure FDA00003061862700022
16. an array base palte is characterized in that, comprises each described thin-film transistor of claim 9-15.
17. a display unit is characterized in that, comprises each described thin-film transistor of claim 9-15.
CN201310133306XA 2013-04-17 2013-04-17 Thin film transistor, manufacturing method of thin film transistor, array substrate and display device Pending CN103258745A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310133306XA CN103258745A (en) 2013-04-17 2013-04-17 Thin film transistor, manufacturing method of thin film transistor, array substrate and display device
PCT/CN2013/080280 WO2014169544A1 (en) 2013-04-17 2013-07-29 Thin film transistor, preparation method therefor, array substrate, and display device
US14/342,234 US20150295094A1 (en) 2013-04-17 2013-07-29 Thin film transistor, manufacturing method thereof, array substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310133306XA CN103258745A (en) 2013-04-17 2013-04-17 Thin film transistor, manufacturing method of thin film transistor, array substrate and display device

Publications (1)

Publication Number Publication Date
CN103258745A true CN103258745A (en) 2013-08-21

Family

ID=48962582

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310133306XA Pending CN103258745A (en) 2013-04-17 2013-04-17 Thin film transistor, manufacturing method of thin film transistor, array substrate and display device

Country Status (3)

Country Link
US (1) US20150295094A1 (en)
CN (1) CN103258745A (en)
WO (1) WO2014169544A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316874A (en) * 2017-07-28 2017-11-03 武汉华星光电技术有限公司 Array base palte and preparation method thereof, display device
CN109273409A (en) * 2018-08-24 2019-01-25 京东方科技集团股份有限公司 A kind of display panel, its production method and display device
CN110931566A (en) * 2018-09-20 2020-03-27 三星显示有限公司 Transistor substrate, method of manufacturing the same, and display device including the same
WO2020140750A1 (en) * 2019-01-02 2020-07-09 京东方科技集团股份有限公司 Thin film transistor, thin film transistor manufacturing method and display device
CN111785635A (en) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 Thin film transistor, manufacturing method thereof, array substrate and display device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609567A (en) * 2016-03-29 2016-05-25 京东方科技集团股份有限公司 Thin film transistor and manufacturing method, array substrate and display device
CN109273498B (en) * 2018-09-25 2021-01-26 京东方科技集团股份有限公司 Array substrate, preparation method thereof, display panel and display device
US11094784B2 (en) 2019-04-08 2021-08-17 International Business Machines Corporation Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101123222A (en) * 2007-08-31 2008-02-13 吉林大学 Making method for multi-crystal TFT array of active driven organic EL display screen
US20080293322A1 (en) * 2004-03-26 2008-11-27 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
CN102790096A (en) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 Film transistor as well as manufacturing method thereof, array substrate and display equipment

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331476B1 (en) * 1998-05-26 2001-12-18 Mausushita Electric Industrial Co., Ltd. Thin film transistor and producing method thereof
US6426268B1 (en) * 2000-11-28 2002-07-30 Analog Devices, Inc. Thin film resistor fabrication method
KR20060099870A (en) * 2005-03-15 2006-09-20 삼성전자주식회사 Thin film transistor comprising capping layer and method of manufacturing the same
US7682882B2 (en) * 2007-06-20 2010-03-23 Samsung Electronics Co., Ltd. Method of manufacturing ZnO-based thin film transistor
KR20100073356A (en) * 2008-12-23 2010-07-01 엘지디스플레이 주식회사 Color electric phoretic display device and method for manufacturing the same
US9107335B2 (en) * 2013-02-19 2015-08-11 Infineon Technologies Ag Method for manufacturing an integrated circuit and an integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080293322A1 (en) * 2004-03-26 2008-11-27 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
CN101123222A (en) * 2007-08-31 2008-02-13 吉林大学 Making method for multi-crystal TFT array of active driven organic EL display screen
CN102790096A (en) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 Film transistor as well as manufacturing method thereof, array substrate and display equipment

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316874A (en) * 2017-07-28 2017-11-03 武汉华星光电技术有限公司 Array base palte and preparation method thereof, display device
CN107316874B (en) * 2017-07-28 2020-03-10 武汉华星光电技术有限公司 Array substrate, manufacturing method thereof and display device
CN109273409A (en) * 2018-08-24 2019-01-25 京东方科技集团股份有限公司 A kind of display panel, its production method and display device
US11257849B2 (en) 2018-08-24 2022-02-22 Boe Technology Group Co., Ltd. Display panel and method for fabricating the same
CN110931566A (en) * 2018-09-20 2020-03-27 三星显示有限公司 Transistor substrate, method of manufacturing the same, and display device including the same
WO2020140750A1 (en) * 2019-01-02 2020-07-09 京东方科技集团股份有限公司 Thin film transistor, thin film transistor manufacturing method and display device
US11489052B2 (en) 2019-01-02 2022-11-01 Mianyang Boe Optoelectronics Technology Co., Ltd. Thin film transistor, manufacturing method of thin film transistor and display device
CN111785635A (en) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 Thin film transistor, manufacturing method thereof, array substrate and display device

Also Published As

Publication number Publication date
WO2014169544A1 (en) 2014-10-23
US20150295094A1 (en) 2015-10-15

Similar Documents

Publication Publication Date Title
CN103258745A (en) Thin film transistor, manufacturing method of thin film transistor, array substrate and display device
CN103745978B (en) Display device, array base palte and preparation method thereof
US9391207B2 (en) Thin film transistor, array substrate and manufacturing method thereof, and display device
US9761616B2 (en) Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device
US9685461B2 (en) Display device, array substrate and method for manufacturing the same
US11177293B2 (en) Array substrate and fabricating method thereof, and display device
CN107425044B (en) Flexible display panel, manufacturing method thereof and display device
WO2016086531A1 (en) Array substrate and manufacturing method therefor
CN103996716A (en) Poly-silicon thin film transistor and preparation method thereof, and array substrate
KR20100005779A (en) Poly silicon thin film transistor and method of fabricating the same
CN107316874B (en) Array substrate, manufacturing method thereof and display device
CN107221501A (en) Vertical-type thin film transistor (TFT) and preparation method thereof
WO2018214732A1 (en) Array substrate and manufacturing method thereof, and display device
US9704998B2 (en) Thin film transistor and method of manufacturing the same, display substrate, and display apparatus
US9812541B2 (en) Array substrate, method for fabricating the same and display device
EP3001460B1 (en) Thin film transistor and preparation method therefor, display substrate, and display apparatus
WO2020042834A1 (en) Electro-static discharge protection circuit, display panel, and display device
US20170278873A1 (en) Thin film transistor, thin film transistor panel, and method for manufacturing the same
CN104681632A (en) Thin-film transistor and production method and display device thereof
US20210225898A1 (en) Manufacturing method of tft array substrate and tft array substrate
CN107275343B (en) Manufacturing method of bottom gate type TFT substrate
CN105552035A (en) Manufacturing method for low-temperature poly-silicon TFT (thin film transistor) array substrate and structure thereof
CN110676266B (en) TFT substrate, preparation method thereof and display device
US20230163136A1 (en) Display panel, array substrate, and manufacturing method thereof
CN105789052A (en) Fabrication method of low-temperature poly-silicon thin film transistor and product

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20130821

RJ01 Rejection of invention patent application after publication