CN112786667A

CN112786667A - AMOLED display panel and preparation method thereof

Info

Publication number: CN112786667A
Application number: CN202110006806.1A
Authority: CN
Inventors: 陈远鹏; 徐源竣
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-01-05
Filing date: 2021-01-05
Publication date: 2021-05-11

Abstract

The embodiment of the invention discloses an AMOLED display panel and a preparation method thereof, wherein the AMOLED display panel comprises: TFT array substrate and set up in top emitting OLED device on the TFT array substrate, the TFT array substrate includes: the buffer layer is arranged on the shading layer and comprises a first buffer layer positioned in the driving TFT area, wherein the buffer layer is not arranged in the capacitor area; the embodiment of the invention reduces the thickness of the capacitor in the capacitor area by not arranging the buffer layer in the capacitor area, does not change the area of the capacitor and does not adopt interlayer capacitors, ensures high capacitance and simultaneously ensures the flatness below the anode of the top-emitting OLED device, and further improves the yield of the panel.

Description

AMOLED display panel and preparation method thereof

Technical Field

The invention relates to the technical field of display, in particular to an AMOLED display panel and a preparation method thereof.

Background

Organic Light-Emitting diodes (OLEDs) are active Light-Emitting devices. Compared with the Liquid Crystal Display (LCD) panel in the current mainstream flat panel Display technology, the OLED has the advantages of high contrast, wide viewing angle, low power consumption, thinner volume and the like, is expected to become the next generation flat panel Display technology after the LCD, and is one of the technologies which are most concerned in the current flat panel Display technology. Among them, the AMOLED (Active-matrix organic light emitting diode) has the characteristics of large size, power saving, high resolution, long panel life, and the like, and thus has received high attention in the field of display technology.

The existing AMOLED display panel includes: the OLED display device comprises a TFT array substrate containing a Thin Film Transistor (TFT) driving circuit and a plurality of OLED display devices arranged on the TFT array substrate, wherein each OLED display device is controlled by a corresponding TFT. At present, the manufacturing process of a Top-gate Thin Film Transistor (Top-gate TFT) has a complicated structure and a large number of layers. Each additional array process not only increases the time cost and material cost, but also reduces the yield. Therefore, a new process of Gate Source Drain electrode Layer Thin Film Transistor (GSD one Layer TFT) is proposed by reducing the process. And by combining Ink Jet Printing (IJP) technology, the preparation time and cost can be further reduced, and the feasibility of mass production can be effectively improved. Compared with the bottom-emitting AMOLED display technology, the top-emitting technology can realize higher aperture opening ratio and improve display performance because the light emission is not independent of a driving circuit area. As shown in fig. 1, the array substrate of such a GSD one Layer TFT generally includes: the substrate 11 is divided into a plurality of driving TFT areas A, a plurality of capacitance areas B and a plurality of metal wiring areas C; a light shielding layer 12 disposed on the substrate 11 and located in the driving TFT area a, the capacitor area B, and the metal wiring area C; the buffer layer 13 is arranged on the light shielding layer 12 and is positioned in the driving TFT area A, the capacitor area B and the metal wiring area C; an active layer 14 disposed on the buffer layer 13 and located in the driving TFT region a, the capacitor region B, and the metal wiring region C; a gate insulating layer 15 disposed on the active layer 14 and located in the driving TFT region a and the metal wiring region C; the metal layer 16 is arranged on the gate insulating layer 15 and is positioned in the driving TFT area a and the metal wiring area C, and the metal layer of the driving TFT area a includes a gate 162, a source 163 and a drain 161 on the same layer; and a passivation layer 17 over the metal layer 16. The capacitor in the capacitor area B is in a sandwich capacitor structure with three electrode plates, wherein the upper electrode plate is an anode 19 positioned above the flat layer 18, the middle electrode plate is a flat layer, and the lower electrode plate is a light shielding layer.

However, using such a conventional design in which the capacitor is not directly below the OLED display device may have an effect on pixel resolution. If the capacitor is disposed right below the OLED display device, the requirement for the flatness of the pixel light emitting area is very high due to the inkjet printing technology, and particularly, if the anode of the pixel light emitting area adopts the conventional interlayer capacitor structure, the yield of the AMOLED is inevitably reduced due to the low flatness.

Disclosure of Invention

The embodiment of the invention provides an AMOLED display panel and a preparation method thereof, aiming at improving the phenomenon of AMOLED yield reduction caused by low flatness generated by a sandwich capacitor structure of a traditional top-emission AMOLED display panel.

To solve the above problem, in a first aspect, the present application provides an AMOLED display panel, including: a TFT array substrate and a plurality of top-emitting OLED devices disposed on the TFT array substrate,

the TFT array substrate includes:

the substrate is divided into a plurality of driving TFT areas, a plurality of capacitance areas and a plurality of metal wiring areas; wherein the drive TFT area is provided with a drive TFT, the capacitance area is provided with a capacitor, the metal wiring area is provided with metal wirings,

the shading layer is arranged on the substrate and comprises a first shading layer positioned in the driving TFT area and a second shading layer positioned in the capacitor area, and the second shading layer is used as a lower electrode plate of a capacitor in the capacitor area;

the buffer layer is arranged on the shading layer and comprises a first buffer layer positioned in the driving TFT area, wherein the buffer layer is not arranged in the capacitor area;

an active layer disposed on the buffer layer and including a first active layer located in the driving TFT region;

the grid electrode insulating layer is arranged on the active layer and comprises a first grid electrode insulating layer positioned in the driving TFT area and a second grid electrode insulating layer positioned in the capacitance area, and the second grid electrode insulating layer is used as a capacitance dielectric layer of a capacitor in the capacitance area; and

and a metal layer disposed on the gate insulating layer and including a first metal layer located in the driving TFT region and a second metal layer located in the capacitor region, wherein the first metal layer includes a gate 162, a source 163, and a drain 161 on the same layer, and the second metal layer serves as an upper electrode plate of a capacitor in the capacitor region.

Further, in the metal routing area, the light shielding layer further includes a third light shielding layer, the buffer layer further includes a second buffer layer, the active layer further includes a second active layer, the gate insulating layer further includes a third gate insulating layer, and the metal layer further includes a third metal layer.

Further, the top-emitting OLED device includes: an anode electrode positioned above the capacitor area and electrically connected with the driving TFT area, wherein the orthographic projection of the anode electrode on the AMOLED display panel covers the capacitor area;

a layer of light emitting material on the anode; and

a cathode overlying the layer of light emitting material.

Furthermore, the grid electrode, the source electrode and the drain electrode are divided into two layers, the lower layer contains one or more of Mo, Ti and Ni, and the upper layer contains Cu or Cu-containing alloy. Wherein the thickness range of the lower layer

Thickness range of upper layer

Furthermore, the shading layer is divided into three layers, the lower layer contains one or more alloys of Mo, Ti and Ni, the middle layer is Cu or Cu alloy, and the upper layer contains one or more alloys of Mo, Ti and Ni. Wherein the thickness range of the lower layer

Thickness range of intermediate layer

Thickness range of upper layer

Further, the active layer material is IGZO, ITZO or IGZTO.

In a second aspect, the present application provides a method for manufacturing an AMOLED display panel, including the following steps:

providing a substrate, and dividing a plurality of driving TFT areas, a plurality of capacitor areas and a plurality of metal wiring areas on the substrate;

depositing a light shielding layer, a buffer layer and an active layer on the substrate in sequence, and removing the buffer layer in the capacitance region;

and sequentially depositing a grid electrode insulating layer, a metal layer and a top-emitting OLED device on the light shading layer, the buffer layer and the active layer.

Further, depositing a light shielding layer, a buffer layer and an active layer on the substrate in sequence, and removing the buffer layer in the capacitance region, includes:

depositing a whole shading layer on a substrate, and etching the whole shading metal layer by using a first yellow light process to form a first shading layer of the driving TFT area, a second shading layer of the capacitor area and a third shading layer of the metal wiring area;

depositing a whole buffer layer and a whole active layer above the shading metal layer in sequence, etching and patterning the whole active layer by using a second yellow light process, and forming a first active layer of the driving TFT area and a second active layer of the metal wiring area;

and etching the lower buffer layer by utilizing the first active layer and the second active layer, removing the buffer layer in the capacitance area, and forming the first buffer layer in the drive TFT area and the second buffer layer in the metal wiring area.

Further, the sequentially depositing a gate insulating layer, a metal layer and a top-emitting OLED device on the light shielding layer, the buffer layer and the active layer includes the steps of:

depositing a whole gate insulating layer above the active layer, and performing hole opening and conductor processing on the gate insulating layer of the driving TFT region by using a third yellow light process to form a first gate insulating layer of the driving TFT region, a second gate insulating layer of the capacitor region and a third gate insulating layer of the metal wiring region;

depositing a metal layer above the gate insulating layer, patterning the metal layer by using a fourth yellow light process, and etching the metal layer to form a first metal layer of the driving TFT region, a second metal layer of the capacitor region and a third metal layer of the metal wiring region, wherein the first metal layer comprises a gate, a source and a drain on the same layer;

performing self-aligned etching on the gate insulating layer by using the patterned metal layer to form a self-aligned channel region in the driving TFT region;

and depositing a passivation layer and a flat layer in sequence, patterning and opening the passivation layer and the flat layer, depositing and patterning an anode of the top-emitting OLED device, depositing an organic photoresist layer again, and patterning to define an OLED light emitting area.

Further, the material of the active layer adopts IGZO, ITZO or IGZTO.

The invention provides a top-emitting OLED display panel with a grid electrode, a source electrode and a drain electrode on the same layer, which reduces the thickness of a capacitor in a capacitor area by not arranging a buffer layer in the capacitor area, ensures high capacitance without changing the area of the capacitor and adopting an interlayer capacitor, thereby ensuring the flatness below the anode of a top-emitting OLED device and further improving the yield of the panel.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.

Fig. 1 is a schematic structural diagram of a conventional AMOLED display panel;

fig. 2 is a schematic structural diagram of an AMOLED display panel according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of the AMOLED display panel after step S11 according to the embodiment of the invention;

fig. 4 is a schematic structural diagram of the AMOLED display panel after step S12 according to the embodiment of the invention;

fig. 5 is a schematic structural diagram of the AMOLED display panel after step S13 according to the embodiment of the invention;

fig. 6 is a schematic structural diagram of the AMOLED display panel after step S14 according to the embodiment of the invention;

fig. 7 is a schematic structural diagram of the AMOLED display panel after step S15 according to the embodiment of the invention;

fig. 8 is a schematic structural diagram of the AMOLED display panel after step S16 according to the embodiment of the invention.

Wherein the reference numbers indicate:

a-a drive TFT region; b-a capacitance region; c-metal routing area; 11-a substrate; 12-a light-shielding layer; 121-a first light-shielding layer; 122-a second light-shielding layer; 123-a third light-shielding layer; 13-a buffer layer; (ii) a 131-a first buffer layer; 132-a second buffer layer; 14-an active layer; 141-a first active layer; 142-a second active layer; 15-a gate insulating layer; 151-first gate insulating layer; 152-a second gate insulation layer; 153-third gate insulation layer; 16-a metal layer; 160-first metal layer; 161-a drain electrode; 162-a gate; 163-source; 164-a second metal layer; 165-a third metal layer; 17-a passivation layer; 18-a planar layer; 19-an anode; 10-photoresist layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The embodiment of the invention provides an AMOLED display panel and a preparation method thereof, which are respectively explained in detail below.

First, referring to fig. 2 to 7, an AMOLED display panel according to an embodiment of the present invention includes: the TFT array substrate and set up in a plurality of top-emitting OLED devices on the TFT array substrate, the TFT array substrate includes: a substrate 11, a light-shielding layer 12, a buffer layer 13, an active layer 14, a Gate insulating layer 15 (GI), and a metal layer 16. In one embodiment, the TFT array substrate further includes: a passivation layer 17 and a planarization layer 18.

The substrate 11 may be divided into a plurality of driving TFT areas a, a plurality of capacitor areas B, and a plurality of metal routing areas C, where the driving TFT areas a are provided with driving TFTs, the capacitor areas B are provided with capacitors, and the metal routing areas C are provided with metal routing lines.

Specifically, the capacitor comprises two capacitor electrode plates and a capacitor dielectric layer directly arranged between two adjacent capacitor electrode plates.

It is understood that the substrate 11 may be divided into other regions, such as a switching TFT region, and the details are not limited herein.

Specifically, the light shielding layer 12 is a light shielding metal layer, is disposed on the substrate 11, and includes a first light shielding layer 121 located in the driving TFT area a and a second light shielding layer 122 located in the capacitor area B; the second light shielding layer 122 is used as a lower electrode plate of the capacitor in the capacitor region B.

Specifically, the buffer layer 13 is disposed on the light-shielding layer 12 and includes a first buffer layer 131 located in the driving TFT area a, wherein the capacitor area B is not provided with the buffer layer 13 and is configured to reduce the thickness of the capacitor in the capacitor area B, so as to ensure high capacitance.

Specifically, the active layer 14 is disposed on the buffer layer 13 and includes a first active layer 141 in the driving TFT region a.

Specifically, the gate insulating layer 15 is disposed on the active layer 14, and includes a first gate insulating layer 151 located in the driving TFT area a and a second gate insulating layer 152 located in the capacitor area B, where the second gate insulating layer 152 is used as a capacitor dielectric layer of a capacitor in the capacitor area B;

specifically, the metal layer 16 is disposed on the gate insulating layer 15 and includes a first metal layer 160 located in the driving TFT region a and a second metal layer 164 located in the capacitor region B, wherein the first metal layer 160 includes a gate 162, a source 163 and a drain 161 on the same layer, and the same layer is designed to reduce the number of yellow light processes. The second metal layer 164 serves as an upper electrode plate of the capacitor in the capacitor region B.

The top emission technology can realize higher aperture ratio and improve display performance. The design of the same layer of the gate 162, the source 163 and the drain 161 can reduce the manufacturing cost of the AMOLED display panel, but due to the design of the same layer of the gate 162, the source 163 and the drain 161, the capacitor needs to adopt an interlayer capacitor structure, and the interlayer capacitor generates low flatness, which will affect the anode 19 of the top-emitting OLED device above the capacitor, which has a high requirement on flatness, thereby affecting the yield of the AMOLED display panel.

The embodiment of the invention provides a top emission AMOLED display panel with the same layer as the gate 162, the source 163 and the drain 161, the thickness of a capacitor in a capacitor area B is reduced by not arranging a buffer layer 13 in the capacitor area B, the second light shielding layer 122 is used as a lower electrode plate of the capacitor, the second metal layer 164 is used as an upper electrode plate, high capacitance is ensured under the conditions of not changing the area of the capacitor and not adopting an interlayer capacitor, the traditional condition that the anode 19 of a top emission AMOLED device is used as an upper electrode plate to generate low flatness is broken through, the flatness below the anode 19 is ensured, and the yield of the panel is improved.

On the basis of the above embodiments, as shown in fig. 2, in another specific embodiment of the present application, in the metal routing area C, the light shielding layer 12 further includes a third light shielding layer 123, the buffer layer 13 further includes a second buffer layer 132, the active layer 14 further includes a second active layer 142, the gate insulating layer 15 further includes a third gate insulating layer 153, and the metal layer 16 further includes a third metal layer 165.

In the above embodiments of the present invention, in order to avoid the Buffer layer 13 loss (Buffer loss) in the etching process of the Buffer layer 13 in the capacitor region B, the active layer 14 is present above the region to reduce the risk of Short circuit (Short) between the metal layer 16 and the light shielding layer 12 due to the reduction of the thickness of the dielectric layer caused by the etching of the Buffer layer 13, thereby improving the process yield.

In one embodiment, as shown in fig. 2, the top-emitting OLED device includes:

an anode 19, wherein the anode 19 is positioned above the capacitor region B and electrically connected with the driving TFT region a;

a layer of light emitting material on the anode 19; and

a cathode overlying the layer of light emitting material.

Specifically, the orthographic projection of the anode 19 on the AMOLED display panel covers the capacitance region B. The covering refers to partial covering or complete covering.

The anode 19 is an Indium Tin Oxide (ITO) layer, a silver (Ag) metal layer 16 and an ITO/Ag/ITO three-layer structure of the ITO layer.

In the embodiment of the invention, the anode 19 is positioned right above the capacitor area B, so that the problem that the anode 19 of the traditional top-emitting OLED device is not positioned right above the capacitor area B is solved, and the resolution of the display panel is higher.

In another embodiment of the present application, the gate electrode, the source electrode 163 and the drain electrode 161 are divided into two layers, and the lower layer is a contact enhancing layer comprising an alloy of one or more of molybdenum (Mo), titanium (Ti) and nickel (Ni) in a thickness range

(angstroms). The upper layer is a main metal wiring layer containing copper (Cu) or Cu alloy and having a thickness in the range

In another embodiment of the present application, the light-shielding layer 12 is divided into three layers, the upper layer is a contact enhancement layer and contains one or more alloys of Mo, Ti, and Ni, the middle layer is a main metal routing layer and contains Cu or Cu alloy, and the upper layer is an oxidation protection layer and prevents oxidation failure of the middle main routing layer in an Array substrate (Array) process, and contains one or more alloys of Mo, Ti, and Ni. Wherein the thickness range of the lower layer

Thickness range of intermediate layer

Thickness range of upper layer

In another embodiment of the present application, the active layer 14 is made of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) or Indium Gallium Zinc Tin Oxide (IGZTO).

It should be noted that, in the foregoing display panel embodiment, only the above structure is described, and it is understood that, in addition to the above structure, the display panel according to the embodiment of the present invention may further include any other necessary structure, such as a polarizer, a cover plate, and the like, as needed, and the specific description is not limited herein.

The embodiment of the invention also provides a preparation method of the AMOLED display panel, which comprises the following steps:

(1) providing a substrate 11, and dividing a plurality of driving TFT areas A, a plurality of capacitance areas B and a plurality of metal wiring areas C on the substrate 11;

(2) depositing a light shielding layer 12, a buffer layer 13 and an active layer 14 on the substrate 11 in sequence, and removing the buffer layer 13 of the capacitance region B;

(3) a gate insulating layer 15, a metal layer 16 and a top-emitting OLED device are sequentially deposited on the light-shielding layer 12, the buffer layer 13 and the active layer 14.

Specifically, the sequentially depositing the light shielding layer 12, the buffer layer 13 and the active layer 14 on the substrate 11 and removing the buffer layer 13 in the capacitance region B includes:

s11 as shown in fig. 3, depositing the entire light-shielding layer 12 on the substrate 11, etching and patterning the entire light-shielding layer 12 by using a first photolithography process, and forming the first light-shielding layer 121 of the driving TFT area a, the second light-shielding layer 122 of the capacitor area B, and the third light-shielding layer 123 of the metal routing area C;

s12 as shown in fig. 4, sequentially depositing a complete buffer layer 13 and a complete active layer 14 on the light-shielding metal layer 16, depositing an organic photoresist layer 10 on the active layer 14, and etching and patterning the complete active layer 14 by using a second photolithography process to form a first active layer 141 of the driving TFT region a and a second active layer 142 of the metal routing region C;

s13 as shown in fig. 5, the first active layer 141 and the second active layer 142 are used to etch the lower buffer layer 13, remove the buffer layer 13 in the capacitor region B, and form the first buffer layer 131 in the driving TFT region a and the second buffer layer 132 in the metal routing region C.

Specifically, the sequentially depositing a gate insulating layer 15, a metal layer 16 and a top-emitting OLED device on the light shielding layer 12, the buffer layer 13 and the active layer 14 includes:

s14 as shown in fig. 6, depositing the entire gate insulating layer 15 on the active layer 14, and performing a hole opening and a conductor forming process on the gate insulating layer 15 in the driving TFT region a by using a third photolithography process to form the first gate insulating layer 151 in the driving TFT region a, the second gate insulating layer 152 in the capacitor region B, and the third gate insulating layer 153 in the metal routing region C;

s15 as shown in fig. 7, depositing a metal layer 16 on the gate insulating layer 15, depositing an organic photoresist layer 10 on the metal layer 16, patterning by a fourth photolithography process, and etching the metal layer 16 to form a first metal layer 160 in the driving TFT region a, a second metal layer 164 in the capacitor region B, and a third metal layer 165 in the metal routing region C, wherein the first metal layer 160 includes a gate electrode 162, a source electrode 163, and a drain electrode 161 on the same layer;

s16 as shown in fig. 8, using the patterned metal layer 16 to perform self-aligned etching on the gate insulating layer 15, forming a self-aligned channel region in the driving TFT region a;

s17 sequentially depositing a passivation layer 17 and a planarization layer 18, patterning and opening the passivation layer 17 and the planarization layer 18, depositing and patterning an anode 19 of the top-emitting OLED device, depositing an organic photoresist layer 10 again, and patterning to define an OLED light-emitting region, thereby obtaining the AMOLED display panel shown in fig. 2.

Specifically, the material of the active layer 14 is IGZO, ITZO, or IGZTO.

In order to better implement the method for preparing the AMOLED display panel, the invention also provides a more specific embodiment, which comprises the following steps:

s21 cleaning the glass substrate 11, dividing a plurality of driving TFT areas A, a plurality of capacitance areas B and a plurality of metal wiring areas C, depositing a whole light shielding layer 12 on the glass substrate 11, wherein the whole light shielding layer 12 adopts a three-layer wiring structure, the lower layer is a contact enhancement layer and contains one or more alloys of Mo, Ti and Ni, and the thickness range is within

The middle layer is a main metal wiring layer made of Cu or Cu alloy and having a thickness range

The upper metal layer is an oxidation protection layer to prevent oxidation failure of the middle main wiring layer in the Array process, contains one or more alloys of Mo, Ti and Ni, and has a thickness range

Patterning the whole light shielding layer 12 by using a first yellow light process and Wet etching (Wet) to form a light shielding layer 12 pattern with wiring and light shielding functions;

s22 depositing a buffer layer 13 on the substrate 11 of the patterned light-shielding layer 12 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, wherein the buffer layer 13 may be a single layer of Si₃N₄Single layer of SiO₂Single layer of SiON, or double layer structure of the above layers, total thickness

S23 Physical Vapor Deposition (PVD) depositing an active layer 14, the active layer 14 being IGZO, ITZO, IGZTO or the like, patterning the active layer 14 using a second photolithography process to define an active region and a light shielding layer 12 trace region, the active layer 14 having a thickness of the active layer 14

S24, etching the buffer layer 23 by using the yellow light pattern of the active layer 14 to ensure that the buffer layer 13 above the light shielding layer 12 of the capacitor region B is removed, and the buffer layer 13 is remained in the metal wiring region C due to the existence of the yellow light pattern of the active layer 14;

s25 PECVD process for depositing the whole gate insulation layer 15, wherein the material is SiOx, the oxygen content can be adjusted and controlled by the PECVD process, and the thickness of the SiOx

The gate insulating layer 15 is used as a dielectric layer of the capacitor in the capacitor region B, since the thickness of the gate insulating layer 15 is significantly larger than that of the buffer layer 13The capacitance value can be effectively improved;

s26, using the third yellow light process to open the GI of TFT area to form S/D area metal contact hole, and conducting conductor treatment to reduce the resistance of AOS;

s27 PVD process deposits metal layer 16, the metal is double-layer metal structure, the lower layer is contact enhancement layer, contains one or more of Mo, Ti, Ni alloy, thickness range

The upper layer is a main metal wire made of Cu or Cu alloy and has a thickness

Patterning the two layers of metal simultaneously by using a fourth yellow light process, and etching the two layers of metal routing by using a Wet process to form the metal layer 16 of the driving TFT area a, the capacitor area B and the metal routing area C, wherein the metal layer 16 of the driving TFT area a includes a gate 162, a source 163 and a drain 161 on the same layer, and the metal layer 16 of the capacitor area B can be used as an upper electrode plate of the capacitor area B;

s28, etching the Gate insulating layer 15 by using the metal layer 16 pattern as a Dry etching (Dry) pattern of the Gate insulating layer 15, forming a Gate 162/Gate insulating layer 15/active layer 14(Gate/GI/IGZO) channel region structure in a self-aligned manner, and performing a conductor process to reduce the IGZO resistance value of the source 163/drain 161(S/D) region;

s29 deposition of passivation layer 17(PV) SiO by PECVD process₂Film, thickness

For protecting the underlying TFT device;

s210, depositing an organic flat layer 18(PLN), patterning the PLN layer by using a fifth yellow light process, and etching the PV opening by using the PLN pattern to form a contact hole;

s211, depositing a first OLED device electrode layer, and patterning the electrode layer by using a sixth yellow light manufacturing process;

s212, covering the patterned OLED device electrode layer with an organic photoresist layer, defining a light emitting region of the OLED device by using a yellow light process, and preparing the OLED device by using an ink-jet printing technology in a later process.

According to the embodiment of the invention, the AMOLED display panel is prepared, the buffer layer 13 is not arranged in the capacitance area B to reduce the thickness of the capacitance in the capacitance area B, the high capacitance is ensured without changing the area of the capacitance and adopting interlayer capacitance, and the flatness below the anode 19 of the top-emitting OLED device is ensured.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and a part which is not described in detail in a certain embodiment may refer to the detailed descriptions in the other embodiments, and is not described herein again.

In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.

The above operations can be implemented in the foregoing embodiments, and are not described in detail herein.

The AMOLED display panel and the method for manufacturing the same provided by the embodiment of the present invention are described in detail above, and the principle and the embodiment of the present invention are explained herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. An AMOLED display panel, comprising: a TFT array substrate and a plurality of top-emitting OLED devices disposed on the TFT array substrate,

the TFT array substrate includes:

the substrate is divided into a plurality of driving TFT areas, a plurality of capacitance areas and a plurality of metal wiring areas;

the shading layer is arranged on the substrate and comprises a first shading layer positioned in the driving TFT area and a second shading layer positioned in the capacitor area;

the grid electrode insulating layer is arranged on the active layer and comprises a first grid electrode insulating layer positioned in the driving TFT area and a second grid electrode insulating layer positioned in the capacitance area; and

and the metal layer is arranged on the grid electrode insulating layer and comprises a first metal layer positioned in the driving TFT area and a second metal layer positioned in the capacitance area, wherein the first metal layer comprises a grid electrode, a source electrode and a drain electrode on the same layer.

2. An AMOLED display panel as set forth in claim 1, wherein the light-shielding layer further comprises a third light-shielding layer at the metal routing region, the buffer layer further comprises a second buffer layer, the active layer further comprises a second active layer, the gate insulating layer further comprises a third gate insulating layer, and the metal layer further comprises a third metal layer.

3. The AMOLED display panel of claim 1, wherein the top-emitting OLED device comprises:

an anode electrode positioned above the capacitor area and electrically connected with the driving TFT area, wherein the orthographic projection of the anode electrode on the AMOLED display panel covers the capacitor area;

a layer of light emitting material on the anode; and

a cathode overlying the layer of light emitting material.

4. The AMOLED display panel of claim 1, wherein the gate, the source and the drain are divided into two layers, a lower layer containing an alloy of one or more of Mo, Ti, Ni, and an upper layer containing Cu or an alloy containing Cu.

5. The AMOLED display panel as recited in claim 1, wherein the light shielding layers are divided into three layers, the lower layer contains an alloy of one or more of Mo, Ti and Ni, the middle layer contains Cu or an alloy containing Cu, and the upper layer contains an alloy of one or more of Mo, Ti and Ni.

6. An AMOLED display panel as claimed in claim 1, wherein the active layer material is IGZO, ITZO or IGZTO.

7. A preparation method of an AMOLED display panel is characterized by comprising the following steps:

8. The method for manufacturing an AMOLED display panel as claimed in claim 7, wherein the sequentially depositing a light shielding layer, a buffer layer and an active layer on the substrate and removing the buffer layer of the capacitor region comprises the steps of:

9. The method of fabricating an AMOLED display panel of claim 7, wherein sequentially depositing a gate insulating layer, a metal layer, and a top-emitting OLED device on the light-shielding layer, the buffer layer, and the active layer comprises:

10. The method of manufacturing an AMOLED display panel as claimed in claim 7, wherein the material of the active layer is IGZO, ITZO or IGZTO.