CN113782616A - Thin film transistor, preparation method thereof, array substrate and display device - Google Patents
Thin film transistor, preparation method thereof, array substrate and display device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Abstract
The invention provides a thin film transistor and a preparation method thereof, an array substrate and a display device, belongs to the technical field of display, and can solve the problem that an active layer loses semiconductor performance or the distribution uniformity of TFT channel length on the substrate is poor due to the existing conductor treatment. The preparation method of the thin film transistor comprises the step of forming the through hole on one side of the conductive area, which is adjacent to the semiconductor area, wherein the through hole can prevent the conductive area from diffusing to the semiconductor area, and can prevent the middle part of the active layer from being diffused to form a conductor.
Description
The application has the application number of 201910024065.2 and the application date of 2019, month 01
The invention is a divisional application of 'a thin film transistor and a preparation method thereof, an array substrate and a display device' on 10 days.
Technical Field
The invention belongs to the technical field of display, and particularly relates to a thin film transistor, a preparation method thereof, an array substrate and a display device.
Background
As the size of displays is continuously increased, amorphous silicon thin film transistors have problems of insufficient electron mobility and poor uniformity, and in order to solve the problems, technologies using an oxide semiconductor material such as IGZO, ITZO, IZO, etc. instead of amorphous silicon as an active layer have been developed.
When a Thin Film Transistor (TFT) is manufactured, in order to ensure that a source electrode and a drain electrode (S/D) in the TFT are in good contact with an IGZO, reduce S/D overlap resistance, and improve the performance of the TFT, a position where an edge of an active layer is in contact with the source electrode and the drain electrode needs to be subjected to a conductor treatment.
The inventor finds that at least the following problems exist in the prior art: the problem of conductor diffusion cannot be avoided after the edge of the active layer is subjected to conductor treatment, and the conductor diffusion can cause the middle part of the active layer to be diffused to form a conductor, so that the semiconductor performance is lost or the distribution uniformity of the channel length of the TFT on the substrate is poor.
Disclosure of Invention
The invention provides a thin film transistor, a preparation method thereof, an array substrate and a display device, aiming at the problem that the existing conductor treatment can cause the loss of the semiconductor performance of an active layer or the poor distribution uniformity of the channel length of a TFT on a substrate.
The technical scheme adopted for solving the technical problem of the invention is as follows:
a method for preparing a thin film transistor comprises the steps of forming an oxide active layer on a substrate, and a source electrode and a drain electrode, wherein the oxide active layer comprises a conductive region and a semiconductor region which are connected, and the source electrode and the drain electrode are electrically connected with the conductive region;
the method further comprises the step of forming a via at a side of the region of conductimerization adjacent to the semiconductor region.
Optionally, the forming of the oxide active layer specifically includes the following steps:
forming a pattern of oxide semiconductor material on a substrate and including a via, the pattern of oxide semiconductor material including a connected region of conductibility and a semiconductor region, the via being located on a side of the region of conductibility adjacent the semiconductor region;
and conducting the oxide semiconductor material in the conducting area to obtain an oxide active layer.
Optionally, the performing of the conductive treatment on the conductive region includes hydrogenating or de-oxidizing the oxide semiconductor material of the conductive region by means of ion bombardment.
Optionally, the forming of the oxide active layer, and the source and the drain specifically include the following steps:
forming an oxide active layer over a substrate;
forming a gate insulating layer on the substrate after the above steps;
forming a grid on the substrate after the step is finished;
forming an interlayer insulating layer on the substrate after the above steps;
and forming a source electrode and a drain electrode on the substrate after the step.
Optionally, the via hole includes a sidewall, wherein the sidewall far from the semiconducting region is a first sidewall; the source and drain electrodes cover at least a portion of the first sidewall.
The invention also provides a thin film transistor, which comprises a substrate, an oxide active layer arranged above the substrate, a source electrode and a drain electrode, wherein the oxide active layer comprises a conductor region and a semiconductor region which are connected, and the source electrode and the drain electrode are electrically connected with the conductor region; wherein, a via hole is arranged on one side of the conductor region close to the semiconductor region.
Optionally, the conductive region is formed by hydrogenating or de-oxidizing the same oxide semiconductor material as the semiconductor region.
Optionally, the conductive region forms a side surface at the via hole, wherein the side surface far away from the semiconductive region is a first side surface; the source and drain electrodes cover at least a portion of the first side.
Optionally, the thin film transistor is of a top gate type.
The invention also provides an array substrate comprising the thin film transistor.
The invention also provides a display device comprising the array substrate.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor according to embodiment 1 of the present invention;
fig. 2 is a schematic flow chart of a thin film transistor according to embodiment 2 of the present invention;
fig. 3 is a schematic diagram of the formation of an active layer of a thin film transistor according to embodiment 2 of the present invention;
fig. 4 is a schematic diagram of forming a source electrode and a drain electrode of a thin film transistor according to embodiment 2 of the present invention;
fig. 5 is a schematic structural diagram of a thin film transistor according to embodiment 3 of the present invention;
fig. 6 is another schematic structural diagram of a thin film transistor according to embodiment 3 of the present invention;
wherein the reference numerals are: 1. a substrate; 11. a protective layer; 12. a buffer layer; 2. an oxide active layer; 21. a region of electrical conductivity; 22. a semiconductor region; 23. a via hole; 3. a source and a drain; 4. a gate insulating layer; 5. a gate electrode; 6. an interlayer insulating layer; 7. and (7) photoresist.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
the present embodiment provides a method for manufacturing a thin film transistor, as shown in fig. 1, including the steps of forming an oxide active layer 2 on a substrate 1, and a source electrode and a drain electrode, wherein the oxide active layer 2 includes a conductive region 21 and a semiconductor region 22 which are connected, and the source electrode and the drain electrode are electrically connected to a first conductive region 211 of the conductive region 21; the method also comprises a step of forming a via between the first region of conductimetric 211 and the second region of conductimetric 212 of the region of conductimetric 21, i.e. a step of forming a via 23 on the side of the region of conductimetric 21 adjacent to the semiconductor region 22.
The method for manufacturing the thin film transistor of the embodiment includes the step of forming the via hole 23 on the side of the conductive region 21 adjacent to the semiconductor region 22, the via hole 23 can prevent the conductive region 21 from diffusing to the semiconductor region 22, the conductor can be prevented from being diffused in the middle of the active layer, and both sides of the via hole are adjacent to the conductive region 21, so that the uniformity of manufacturing the via hole 23 is improved.
Example 2:
the embodiment provides a method for manufacturing a thin film transistor, as shown in fig. 2 to 4, which includes the following steps:
optionally, S01, forming a patterned protection layer 11 on the substrate 1, and a buffer layer 12 covering the protection layer 11; the substrate 1 may be made of a transparent material such as glass, and may be cleaned in advance. The buffer layer 12 may be a single layer structure or a stacked structure of a plurality of sub-layers, and the buffer layer 12 may be formed using silicon oxide or silicon nitride. Specifically, the buffer layer 12 may be formed by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
S02, forming an oxide active layer 2 on the substrate 1 where the above steps are completed; wherein the oxide active layer 2 comprises a conductive region 21 and a semiconductor region 22 which are connected; specifically, S02 includes:
s02a, forming a pattern of an oxide semiconductor material and including a via 23 on the substrate 1 after the above steps by using a one-step patterning process, wherein the pattern of the oxide semiconductor material includes a conductive region 21 and a semiconductor region 22 which are connected to each other, the conductive region 21 includes a first conductive region 211 and a second conductive region 212, the via 23 is disposed between the first conductive region 211 and the second conductive region 212, and the via 23 is located on a side of the conductive region 21 adjacent to the semiconductor region 22; specifically, as shown in fig. 3, a layer of photoresist 7 may be formed on the oxide semiconductor material, and the photoresist 7 may be exposed and developed, and then dry-etched to form a pattern including an active layer and a via 23.
S02b, the oxide semiconductor material in the conductive region 21 is subjected to a conductive treatment to obtain the oxide active layer 2.
As an alternative to this embodiment, the conductimetric treatment of the conductimetric region 21 comprises a hydrogenation or a deoxidation of the oxide semiconductor material of the conductimetric region 21 by means of ion bombardment.
In this embodiment, the conductor is formed after the via hole 23 is formed, so that diffusion of hydrogen atoms during the conductor formation process can be avoided to a greater extent, wherein the via hole 23 and the active layer can be formed by one-step mask formation.
As a preferable mode of the present embodiment, as shown in fig. 5 and 6, the first conductive region 211 forms a first sidewall 213 near the source and the drain 3, and the second conductive region 212 forms a second sidewall 214 far from the semiconductor region 22, wherein the first sidewall 213 and the second sidewall 214 together form a via 23; the source and drain electrodes 3 cover at least part of the first sidewall 213.
This is equivalent to increasing the overlapping contact area of the source and drain electrodes with the side surface of the via hole 23 of the conductive region 21, and is more favorable for electron transfer.
S03, forming a gate insulating layer 4 on the substrate 1 after the above steps; specifically, the gate insulating layer 4 may be formed over the active layer by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
S04, forming a gate 5 on the substrate 1 after the above steps; the gate electrode 5 may be formed using at least one material of molybdenum, molybdenum-niobium alloy, aluminum-neodymium alloy, titanium, or copper. Specifically, the gate metal electrode film may be formed by a sputtering method, a thermal evaporation method, a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or an electron cyclotron resonance chemical vapor deposition method.
S05, forming an interlayer insulating layer 6 on the substrate 1 after the above steps; among them, the interlayer insulating layer 6 may be formed using silicon oxide, silicon nitride, hafnium oxide, or aluminum oxide.
S06, forming a source and a drain 3 on the substrate 1 where the above steps are completed, the source and the drain 3 being electrically connected to the first conductive region 211 of the conductive region 21. The source electrode and the drain electrode are made of at least one of molybdenum, molybdenum-niobium alloy, aluminum-neodymium alloy, titanium or copper. As shown in fig. 4, a layer of photoresist 7 may be formed on the conductive material layer, and the photoresist 7 may be exposed and developed, and then etched to form a pattern including the source and drain electrodes 3.
The preparation method of the thin film transistor of the embodiment comprises the step of forming the via hole 23 on one side of the conductor region adjacent to the semiconductor region 22 before the conductor is formed, wherein the via hole 23 can prevent the conductor region 21 from diffusing to the semiconductor region 22, the conductor can be effectively prevented from being formed by diffusing in the middle of the active layer, and both sides of the via hole 23 are adjacent to the conductor region 21, so that the via hole manufacturing uniformity is improved. When the subsequent SD lap joint is carried out, the source electrode and the drain electrode 3 cover at least part of the first side wall of the through hole 23, so that the contact area is increased, the lap joint impedance can be effectively reduced, and the conductivity is improved. The TFT prepared by the method has good uniformity.
In the drawings corresponding to the present embodiment, the size, thickness, and the like of each structural layer are shown only for illustration. In the process implementation, the projection areas of the structural layers on the substrate 1 can be the same or different, and the required projection areas of the structural layers can be implemented through an etching process; meanwhile, the structure shown in the drawings is not limited to the geometric shape of each structural layer, and may be, for example, a rectangle shown in the drawings, a trapezoid, or other shapes formed by etching, and may also be realized by etching.
Example 3:
the present embodiment provides a thin film transistor, as shown in fig. 5, which includes a substrate 1, an oxide active layer 2 disposed above the substrate 1, and source and drain electrodes 3, wherein the oxide active layer 2 includes a conductive region 21 and a semiconductor region 22 connected to each other, the conductive region 21 includes a first conductive region 211 and a second conductive region 212, and the source and drain electrodes 3 are electrically connected to the first conductive region 211 of the conductive region 21; a via 23 is provided between the first and second conductive regions 211 and 212, that is, the via 23 is provided on the side of the conductive region 21 closer to the semiconductor region 22.
In the thin film transistor in the embodiment, the via hole 23 is provided on the side of the conductive region 21 adjacent to the semiconductor region 22, and since the second conductive region 212 is provided close to the semiconductor region 22, the via hole 23 is provided between the first conductive region 211 and the second conductive region 212, so that the via hole 23 can prevent the conductive region 21 from diffusing to the semiconductor region 22, the conductor can be prevented from being diffused in the middle of the active layer, and the via hole 23 is adjacent to the conductive region 21 on both sides, thereby improving the uniformity of via hole fabrication. Further, since the width of the first conductive region 211 is not equal to the width of the second conductive region 212, optionally the width of the first conductive region 211 is greater than the width of the second conductive region 212, so that the influence of the second conductive region 212 on the middle portion of the active layer can be further reduced.
As an alternative to this embodiment, the conductive region 21 is formed by hydrogenating or deoxidizing the same oxide semiconductor material as the semiconductor region 22.
In the present embodiment, a conductor method of hydrogenation or deoxidation is provided, and similar via holes 23 can be provided by other conductor methods. It should be noted that, the formation of the via hole 23 followed by the formation of the conductor can avoid the diffusion of hydrogen atoms during the formation of the conductor to a greater extent, wherein the via hole 23 can be formed with the active layer by one step of masking.
In one embodiment, the thin film transistor is a top gate type. A gate insulating layer 4 is disposed over the oxide active layer 2, and a gate electrode 5 is disposed over the gate insulating layer 4.
In one embodiment, the thin film transistor further comprises a first insulating layer covering the second sidewall 214 and filling the via 23. The first insulating layer comprises a third side at the location of the via 23, which third side extends into the via 23. The first insulating layer may be the interlayer insulating layer 6 disposed above the gate 5, and the first insulating layer partially fills the via hole 23, thereby effectively reducing leakage current.
In this embodiment, a top gate type thin film transistor is taken as an example for specific description, and similar schemes may be adopted for other bottom gate type thin film transistors, which are not described herein again.
In one embodiment, as shown in fig. 6, the conductive region 21 forms a side surface at the via 23, wherein the side surface away from the semiconductive region 21 is a first side surface; the source and drain electrodes 3 cover at least part of the first side. That is, in the scheme shown in fig. 6, the overlapping contact area between the source/drain and the side surface of the via hole 23 of the conductive region 21 is increased, which is more favorable for electron transfer.
In one embodiment, as shown in fig. 6, the gate 5 does not overlap the first region of conductimetric 211. The gate 5 does not overlap the second region of conductivity 212. Since the gate 5 is disposed above the gate insulating layer 4, and the gate 5 is further provided with a first insulating layer, the first insulating layer is partially filled in the via hole 23, so that the gate 5 is not overlapped with the first conductive region 211 and the second conductive region 212, thereby greatly reducing the parasitic capacitance.
In one embodiment, as shown in fig. 6, the gate 5 and the via 23 do not overlap, and the gate 5 and the via 23 do not overlap because the gate 5 is covered by the first insulating layer, so that the uniformity of channel fabrication is improved.
Example 4:
the embodiment provides an array substrate comprising the thin film transistor.
Example 5:
the embodiment provides a display device, which comprises any one of the array substrates. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal display panel, electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (13)
1. A thin film transistor comprising a substrate, an active layer, a source, a drain and a gate provided over the substrate, the active layer comprising a conductive region and a semiconductor region connected, the conductive region comprising a first conductive region connected to the source and the drain and a second conductive region connected to the active layer, a via being provided between the first conductive region and the second conductive region.
2. The thin film transistor according to claim 1, wherein a width of the first conductive region is not equal to a width of the second conductive region.
3. The thin film transistor of claim 1, wherein the first region of conductivity forms a first sidewall proximate the source and drain and the second region of conductivity forms a second sidewall distal the semiconductor region.
4. The thin film transistor of claim 3, further comprising a first insulating layer covering the second sidewall and filling the via.
5. The thin film transistor of claim 4, wherein the first insulating layer includes a third side at the via location, the third side extending into the via.
6. The thin film transistor according to claim 1, wherein the gate electrode does not overlap with the first conductive region.
7. The thin film transistor according to claim 1, wherein the gate electrode does not overlap with the second conductive region.
8. The thin film transistor of claim 1, wherein the gate does not overlap the via.
9. The thin film transistor according to claim 1, wherein the thin film transistor is a top gate type.
10. The thin film transistor according to claim 1, wherein the active layer material is an oxide semiconductor material.
11. An array substrate comprising the thin film transistor according to any one of claims 1 to 10.
12. A display device comprising the array substrate according to claim 11.
13. A display device as claimed in claim 12, characterized in that the display device is an OLED panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111069469.7A CN113782616B (en) | 2019-01-10 | 2019-01-10 | Thin film transistor, preparation method thereof, array substrate and display device |
Applications Claiming Priority (2)
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| CN114883343B (en) * | 2022-04-21 | 2024-03-26 | 北海惠科光电技术有限公司 | Thin film transistor, display substrate and preparation method of thin film transistor |
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| CN113782616B (en) | 2024-01-16 |
| CN109742031B (en) | 2022-07-05 |
| CN115663032A (en) | 2023-01-31 |
| CN109742031A (en) | 2019-05-10 |
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