JPH1093094A - Thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable making the withstand voltage higher, without adopting an LDD structure by making a first distance set to the thickness of a channel region longer than a second distance set to the thickness of a source/drain region. SOLUTION: The surface of an n<+> -type source/drain region 16 is etched selectively without using a photomask, so that a first distance being the distance between the insulating substrate 11 and the interface between the semiconductor film 12 of the whole part of a channel region and a gate-insulating film 13 may be longer than a second distance, being the distance between the insulating substrate 11 and the interface between an n<+> -type source/drain region 16 and a source/drain region 18 to be formed in a subsequent process. As the result of this, the thickness d1 of the semiconductor film 12 of the channel region becomes larger than the thickness d2 of the semiconductor film 12 of the n<+> -type source/drain region 16. Accordingly, it becomes possible to ease the high electric field of the drain region, and to make the drain withstand voltage higher by obtaining a thin-film transistor TFT having an element structure satisfying d1>d2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a high breakdown voltage coplanar thin film transistor.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been widely used as display devices for various devices. This is because the liquid crystal display has advantages such as low power consumption, light weight, low voltage driving, and flat display.

A liquid crystal display device in which a switching element is provided for each pixel electrode to control the operation of each pixel is called an active matrix liquid crystal display device. This type of liquid crystal display device is advantageous in increasing the size of a screen because a high quality display such as a decrease in contrast, a viewing angle range, and a response speed does not occur even when the number of scanning lines increases.

[0004] As a switching element, a thin film transistor (hereinafter, referred to as TFT) is widely used. T
Since the FT is formed on a large-area insulating substrate, an element structure and a manufacturing method different from those of a semiconductor element formed on a normal silicon substrate are required.

FIG. 5 shows a conventional coplanar n-channel T
FIG. 4 shows a cross-sectional view of the FT. In the figure, reference numeral 81 denotes an insulating substrate, on which a semiconductor film 82 is formed. A pair of n ⁺ -type source / drain regions 83 are selectively formed on the surface of the semiconductor film 82. A source / drain electrode 84 is provided in the n ⁺ type source / drain region 83.

A gate electrode 86 is provided on a semiconductor film 82 in a channel region sandwiched between two n ⁺ -type source / drain regions 83 via a gate insulating film 85. The gate insulating film 85 is about 3 to 4 times thicker than that of a normal MOS transistor formed on a silicon substrate.

In this type of coplanar n-channel TFT, it is known that the device characteristics are degraded by a high electric field in the n ⁺ -type source / drain region 83 used as a drain region. One of the characteristic deteriorations is an abnormal increase in leakage current due to a so-called parasitic bipolar.

This is because an insulating substrate 81 is provided under a semiconductor film 82.
Therefore, the high electric field in the drain region causes the semiconductor film 8
This is because the holes generated in 2 cannot escape to the substrate and are accumulated in the semiconductor film 82, unlike a MOS transistor formed on a normal silicon substrate.

When a polycrystalline semiconductor film is used as the semiconductor film 82, the crystal flowing between the grains is destroyed by carriers flowing in the polycrystalline semiconductor film, and the electrical properties of the polycrystalline semiconductor film are changed. There is also a problem that the performance is reduced.

FIG. 6 is a cross-sectional view of a high-breakdown-voltage coplanar TFT capable of relaxing a high electric field in the drain region. This is obtained by introducing a LDD (Lightly Doped Drain), in the element structure shown in FIG. 5, n ⁺ -type source and drain regions 8
The channel side of No. 3 is replaced with an n ⁻ type layer 87.

However, this type of TF having an LDD structure
A liquid crystal display device in which T is integrated on a large-sized substrate has the following problems. In order to form a TFT having the above-described LDD structure, first, as shown in FIG. 7A, a semiconductor film 82, a gate insulating film 85, and a gate electrode 86 are formed on an insulating substrate 81. Next, as shown in FIG. 3A, an n-type impurity ion 88 such as phosphorus ion is implanted by using a gate electrode 86 having a gate width L0 as a mask to form n.
^{A +} type source / drain region 83 is formed.

Next, as shown in FIG. 7 (b), after the gate electrode 86 is patterned to reduce its width from L0 to L1, the gate electrode 86 having the gate width L0 is used as a mask to form n such as phosphorus ions. N ^- type layer 87 is formed by ion implantation of type impurity ions 88.

At this time, the LDD dimension is (L0−L1) /
2 (= L). However, due to misalignment of the photomask in the process of reducing the gate width from L0 to L1, the LDD dimension becomes left-right asymmetric, and the left-right symmetry of the element is lost.

FIG. 7C shows this state. In the figure, the misalignment occurs with respect to the center line 89 by δ, and the LD on the left
The state where the D dimension is L-δ and the LDD dimension on the right side is L + δ is shown.

The n ⁻ -type layer 87 is for preventing the element characteristics from deteriorating due to an increase in the electric field in the n ⁺ -type source / drain regions. However, since the n ⁻ -type layer 87 simultaneously becomes a resistance component of the n ⁺ -type source / drain region 83, if the LDD dimension on the source region side is longer than that on the drain region side, the drain current Will decrease. Thus, the left-right symmetry of the LDD dimension has a great effect on the element characteristics.

Since the misalignment δ is not a fixed value but a value having a certain width, the left-right symmetry of the LDD dimension differs depending on the TFT. For this reason, when the TFTs having the LDD structure are integrated on a large-sized substrate, the device characteristics such as the drain current vary, which causes a problem that the image quality is deteriorated.

As the display area of the liquid crystal display device increases,
The mask moving distance of the exposure apparatus also increases. As the mask movement distance increases, the pattern shift also increases. Therefore, forming the LDD structure uniformly over a large area is limited by the performance of the exposure apparatus.

On the other hand, in the LDD structure, n ⁻ type layer 87
Impurity concentration (LDD concentration) is important. However, when a large-area substrate such as a liquid crystal display device is used, it is difficult to uniformly inject impurities into the entire substrate.

When the LDD concentration differs depending on the TFT, n
The electric field in the ⁺ type source / drain region 83 varies, and the drain current varies. As a result, LD
As in the case of the variation in the D dimension, the image quality deteriorates.

In the above description, the case where a TFT is used for a switching element has been described. However, when a TFT is used for a logic circuit element, a high breakdown voltage is required. This is because a large drain current is required to operate the logic circuit at high speed.

[0021]

As described above, there has been proposed a TFT having an LDD structure introduced as a high breakdown voltage TFT using an insulating substrate. In the liquid crystal display device integrated thereon, there is a problem that the LDD size and the LDD concentration vary, thereby deteriorating the image quality.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a TFT using an insulating substrate capable of improving the breakdown voltage without introducing an LDD structure.

[0023]

[Means for Solving the Problems]

[Summary] In order to achieve the above object, a liquid crystal display device according to the present invention (claim 1) comprises a semiconductor film formed on an insulating substrate and a pair of semiconductor films selectively formed on the semiconductor film. A source / drain region, source / drain electrodes provided in the source / drain regions, and a gate insulating film interposed on the semiconductor film in a channel region sandwiched between the pair of source / drain regions Wherein the first distance that is the thickness of the channel region is larger than the second distance that is the thickness of the source / drain regions.

Further, another liquid crystal display device according to the present invention (claim 2) is the liquid crystal display device according to the present invention (claim 1).
The semiconductor film is formed on the insulating substrate via a light shielding film.

[Operation] According to the present invention, the distance (channel length) between the source and the drain is effectively increased, so that the electric field in the drain region is relaxed and the breakdown voltage is increased. Therefore, according to the present invention, the breakdown voltage can be improved without using the LDD structure.

According to the present invention, the first distance is made larger than the second distance without using a resist pattern mask by etching the semiconductor film in the source / drain region using the gate electrode as a mask. it can. Therefore, according to the present invention, a high-breakdown-voltage TFT can be integrated and formed on a large-area insulating substrate without variation.

[0027]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a process sectional view showing a method of forming a coplanar n-channel TFT according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a semiconductor film 12, a gate insulating film 13, and a gate electrode 14 are sequentially formed on an insulating substrate 11. Here, as the insulating substrate 11, if the TFT is a switching element of a liquid crystal display device, a transparent substrate such as a glass substrate is used.

As the semiconductor film 12, for example, a polycrystalline silicon film is used. As a forming method, for example, a method is used in which after forming an amorphous silicon film, the amorphous silicon film is changed to a polycrystalline silicon film by solid phase growth or laser annealing.

As the gate insulating film 13, for example, a silicon oxide film or a silicon nitride film is used. As a material of the gate electrode 14, for example, Mo, W, Al, or an alloy containing at least two metals selected from the metal group is used.

Next, as shown in FIG. 1B, after the gate insulating film 13 other than the channel region is removed by etching using the gate electrode 14 as a mask, n-type such as phosphorus ions is formed using the gate electrode 14 as a mask. Impurity ions 15 are implanted into the semiconductor film 12 to form n ⁺ -type source / drain regions 16.

In the case of a p-channel TFT, for example, p ⁺ -type source / drain regions are formed by implanting p-type impurity ions such as boron ions. Next, FIG.
(C), the etched surface of the n ⁺ -type source and drain regions 16 using the gate electrode 14 as a mask, a self-aligned manner with the n ⁺ -type source and drain regions 16 of a predetermined thickness I do.

That is, the first distance between the interface between the semiconductor film 12 and the gate insulating film 13 in the entire channel region and the insulating substrate 11 is equal to the n ⁺ type source / drain region and the source formed in a later step. The surface of the n ⁺ -type source / drain region 16 is selectively etched without using a photomask so as to be larger than the second distance between the interface with the drain electrode 18 and the insulating substrate 11.

As a result, the thickness d1 (first distance) of the semiconductor film 12 in the channel region becomes larger than the thickness d2 (second distance) of the semiconductor film 12 in the n ⁺ type source / drain region 16. .

Next, as shown in FIG. 1D, an interlayer insulating film 17 is formed on the entire surface, and then n ⁺
A contact hole for the mold source / drain region 16 is opened, and finally a conductive film is formed on the entire surface, and this is patterned to form a source / drain electrode 18, thereby completing the process.

Here, as the interlayer insulating film 17, for example, an oxide film is used. The source / drain electrodes 18
For example, Mo, W, Al, or an alloy containing at least two metals selected from the group of metals is used as the material.

The TFT of this embodiment is different from the conventional TFT in that d1> d2. According to the TFT having such an element structure, an effect similar to that of a conventional TFT having an LDD structure can be obtained. That is, the high electric field in the drain region can be reduced, and the drain withstand voltage can be improved.

The reason will be described with reference to FIG. FIG.
FIG. 3 is an enlarged cross-sectional view of the n ⁺ -type source / drain region 16 and its vicinity when the TFT of FIG. 1 is in an ON state.

In the case of this embodiment, the pinch-off point A of the channel 19 and the channel side end B of the n ⁺ -type source / drain region 16 are separated by d1−d2 (= Δd). Therefore, the effective channel length is Δd
Is added. That is, the channel length increases by Δd as compared with the related art. As a result, the high electric field in the drain region is alleviated, and the abnormal rise of the leak current can be suppressed as in the case of using the LDD structure.

In addition, since the high electric field is alleviated, it is possible to suppress breakage of crystallinity between grains due to carriers flowing in the polycrystalline semiconductor film when the polycrystalline semiconductor film is used as the semiconductor film 12. Thus, a decrease in reliability due to a change in the electrical properties of the polycrystalline semiconductor film due to the destruction of crystallinity can be prevented.

FIG. 3 is a characteristic diagram showing the relationship between the gate voltage V _gs and the drain current I _ds of the present embodiment and the conventional TFT. In the figure, a is a characteristic curve of the TFT of this embodiment,
b is a characteristic curve of a TFT not using the conventional LDD structure, b
Shows a characteristic curve of a TFT using the conventional LDD structure.

From the figure, it can be seen that the drain current I _ds flowing when the gate voltage V _gs is around 0 V is several μmA in the conventional TFT not using the LDD structure, whereas it is smaller than 1 pA in the TFT of the present embodiment. . That is,
According to the present embodiment, it can be seen that the high electric field in the drain region can be sufficiently relaxed, whereby the leakage current can be extremely reduced.

On the other hand, it can be seen that there is no difference between the TFT of the present embodiment and the TFT using the conventional LDD structure in the drain current I _ds flowing in the region where the gate voltage V _gs is high. That is, according to the present embodiment, it can be seen that a sufficiently large drain current can be obtained.

Summarizing the above results, according to the present embodiment, the leakage current can be sufficiently suppressed without using the LDD structure, and a sufficient level of the drain current (ON current) can be obtained. . That is, LDD
Even without using the structure, it becomes possible to realize a TFT having the same element characteristics as the case using the LDD structure.

According to the present embodiment, the element structure satisfying d1> d2 can be formed in a self-aligned manner by etching the n ⁺ -type source / drain region 16 using the gate electrode 14 as a mask. That is, the above element structure is the same as the conventional TF
It can be easily integrated and formed on a large-area substrate without largely changing the T process.

Therefore, if the TFT of the present embodiment is used as a switching element formed on an insulating substrate (matrix array substrate) of a liquid crystal display device instead of a conventional TFT having an LDD structure, variations in element characteristics may occur. This can prevent the deterioration of the image quality.

Further, the TFT of the present embodiment has d1> d2
Since the element structure improves the drain withstand voltage and allows a large drain current to flow, a high-speed operation logic circuit can be realized by using the TFT of this embodiment as a logic circuit element. (Second Embodiment) The TFT of the present embodiment uses a light shielding film, unlike the TFT of the first embodiment.
This light shielding film is for preventing a leak current generated by irradiating the semiconductor film with light. In the case of a liquid crystal display device, since it is used in a situation where light is irradiated to the TFT, a light shielding film is usually required.

FIG. 4 is a process sectional view showing a method for forming a coplanar n-type channel TFT according to the second embodiment of the present invention. First, as shown in FIG. 4A, a light shielding film 22 is formed on an insulating substrate 21 such as a glass substrate. Next, as shown in FIG. 1A, a semiconductor film 23 is formed on the insulating substrate 21 so as to cover the light shielding film 22.

Here, as the light shielding film 22, for example,
A thin film made of Mo, Al, Ta, W or an alloy composed of at least two metals selected from the group of metals is used. In short, any thin film having a small light transmittance may be used.

As the semiconductor film 23, for example, an amorphous silicon film or a polycrystalline silicon film is used. Next, as shown in FIG. 4B, after a gate insulating film 24 and a gate electrode 25 are sequentially formed, n-type impurity ions 26 such as phosphorus ions are formed using the gate electrode 25 as a mask.
3 are implanted into the n ⁺ -type source / drain regions 27.
To form

Here, the ion implantation may be performed after removing the gate insulating film 24 other than the channel region. As the gate insulating film 24, for example, a silicon oxide film or a silicon nitride film is used.

As the material of the gate electrode 25, for example, Mo, W, Al or an alloy containing at least two metals selected from the group consisting of these metals is used. In the case of a p-channel TFT, for example, p ⁺ -type source / drain regions are formed by implanting p-type impurity ions such as boron ions.

Next, as shown in FIG. 4C, an interlayer insulating film 28 is formed on the entire surface, and then n ⁺
A contact hole for the mold source / drain region 27 is opened, and finally a conductive film is formed on the entire surface, and this is patterned to form a source / drain electrode 29, thereby completing the process.

Here, as the interlayer insulating film 28, for example, an oxide film is used. Also, the source / drain electrodes 29
For example, Mo, W, Al, or an alloy containing at least two metals selected from the group of metals is used as the material.

In the case of this embodiment, the thickness d 1 of the semiconductor film 23 in the channel region is the same as that of the n ⁺ type source / drain region 27.
Is the same as the thickness d2 of the semiconductor film 23, but the light shielding film 22 exists below the semiconductor film 23 in the channel region.
Semiconductor film 23 and gate insulating film 2 in the center of channel region
4 and the first distance between the insulating substrate 21 and the interface between the n ⁺ -type source / drain region 27 on the channel region side and the gate insulating film 24 and the insulating substrate 21. 2
Is greater than the distance.

As a result, the flat portion end C of the upper surface of the semiconductor film 23 and the channel side end B of the n ⁺ type source / drain region 16 are formed.
Is defined as L _BC , and the angle between the flat portion on the upper surface of the semiconductor film 23 and the inclined portion on the side surface of the semiconductor film 23 is θ.
The effective channel length is L _BC (1-co
sθ). That is, L
_The channel length increases by _BC (1−cos θ).

Therefore, also in this embodiment, the high electric field in the drain region is reduced without using the LDD structure, and the first electric field is reduced.
The same effect as that of the embodiment can be obtained. Note that the present invention is not limited to the embodiment described above. For example, in the above embodiment, the first distance is larger than the second distance, but conversely, the second distance may be larger than the first distance. Also in this case, since the channel length is effectively increased, the electric field in the drain region can be reduced without using the LDD structure. In addition, various modifications can be made without departing from the scope of the present invention.

[0058]

As described above in detail, according to the present invention, since the distance (channel length) between the source and the drain is effectively increased, a high breakdown voltage can be formed on the insulating substrate without introducing the LDD structure. TFT can be realized.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a method for forming a TFT according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the function and effect of the TFT of FIG. 1;

FIG. 3 shows a gate voltage V of the present embodiment and a conventional TFT.
characteristic diagram showing the relationship between _gs and the drain current I _ds

FIG. 4 is a process sectional view showing a method for forming a TFT according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a conventional TFT.

FIG. 6 is a sectional view showing a TFT adopting a conventional LDD structure.

FIG. 7 is a process sectional view showing the method of forming the TFT in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Insulating substrate 12 ... Semiconductor film 13 ... Gate insulating film 14 ... Gate electrode 15 ... N-type impurity ion 16 ... n ⁺ type source / drain region 17 ... Interlayer insulating film 18 ... Source / drain electrode 21 ... Insulating substrate 22 ... light shielding film 23 ... semiconductor film 24 ... gate insulating film 25 ... gate electrode 26 ... n-type impurity ion 27 ... n ⁺ type source / drain region 28 ... interlayer insulating film 29 ... source / drain electrode

Claims (2)

[Claims] A semiconductor film formed on an insulating substrate; a pair of source / drain regions selectively formed in the semiconductor film; and source / drain electrodes provided in the source / drain regions, respectively. And a gate electrode disposed on the semiconductor film in a channel region sandwiched by the pair of source / drain regions via a gate insulating film, wherein a thickness of the channel region is 2. The thin film transistor according to claim 1, wherein the first distance is greater than a second distance that is the thickness of the source / drain region. 2. The thin film transistor according to claim 1, wherein the semiconductor film is formed on the insulating substrate via a light shielding film.