CN111987165A - Method for manufacturing lateral double-diffused transistor - Google Patents
Method for manufacturing lateral double-diffused transistor Download PDFInfo
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- CN111987165A CN111987165A CN202010864193.0A CN202010864193A CN111987165A CN 111987165 A CN111987165 A CN 111987165A CN 202010864193 A CN202010864193 A CN 202010864193A CN 111987165 A CN111987165 A CN 111987165A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The application provides a manufacturing method of a transverse double-diffused transistor, which comprises the following steps: forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; etching the grid conductor layer and the grid oxide layer in the source end region, and injecting to form a body region; obliquely injecting the photoresist in the body region by taking the photoresist as a mask to form a first type injection region; forming a first barrier layer on the surfaces of the gate conductor layer and the body region; forming second-type implantation regions between the first-type implantation regions via the first barrier layer; and partially etching the first barrier layer to expose the second type injection region and part of the first type injection region to form a second barrier layer, obliquely injecting photoresist as a mask to form the first type injection region, and then etching the first barrier layer step by step, so that the size of the injection region can be reduced, the size of a device can be reduced, the source-drain on-resistance can be effectively reduced, raw materials can be saved, the cost can be saved, the process steps can be greatly simplified in the whole manufacturing process, and the operation difficulty can be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a transverse double-diffused transistor.
Background
A Lateral Double-Diffused MOS (LDMOS) transistor is widely used as a power field effect transistor because of its excellent characteristics of good thermal stability, high gain, low thermal resistance, and the like. The main parameters for measuring the LDMOS performance are the on resistance and the breakdown voltage, and in practical application, the source and drain on resistance Rdson is required to be reduced as much as possible on the premise of meeting the condition that the source and drain breakdown voltage off-BV is high enough. The method commonly used is to Reduce the surface electric field (RESURF) theory while increasing the concentration of the drift region, so that it can be completely depleted. In addition, the size of the device also affects the on-resistance of the device, and the existing LDMOS has larger size and higher impedance due to the influence of the manufacturing process.
Fig. 1d shows a schematic cross-sectional view of the source region of a conventional LDMOS. As shown in fig. 1d, the formation of the LDMOS device includes: providing a substrate 101; forming a drift region 102 and on top of a substrate 101; forming a gate oxide layer 111 and a gate conductor layer 112 on the surface of the drift region 102, and etching to form an opening; implanting ions through the opening to form a body region 103; forming a barrier layer 121 on the sidewalls of the gate conductor layer 112 at both sides of the opening; forming an N + source region in the body region 103 using the photoresist as a mask; after the photoresist is removed, a P + body contact region is formed in the body region 103 by using a new photoresist as a mask again; covering the surfaces of the gate conductor layer 112 and the body region 103 with a metal silicide layer 151 respectively; a dielectric layer 161 is formed on the surface of the metal silicide layer 151, and a through hole penetrating the surface of the metal silicide layer 151 is etched to extract a source electrode. The formation of the N + source region and the P + body contact region of the source region is limited by the lithography capability and has a large size. Taking an NLDMOS with a 180nm technology as an example, the width of each injection region reaches about 0.4um, and on the basis, the on-resistance between the source end and the drain end of the LDMOS device is very large, so that the performance of the device is reduced; the steps of forming the structure by the process are complex, and the photoresist is used for multiple times and is not easy to operate.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method for manufacturing a lateral double-diffused transistor, which can provide a simpler manufacturing process while reducing the size of an injection region of a multi-source end region, save raw materials, reduce the size of a device, effectively reduce source-drain on-resistance and is convenient to realize.
The invention provides a method for manufacturing a lateral double-diffused transistor, which comprises the following steps:
forming a drift region on top of a substrate;
forming a gate oxide layer and a gate conductor layer which are stacked in sequence on the surface of the drift region, wherein the gate conductor layer defines a drain end region and a source end region which are separated from each other;
etching the grid conductor layer and the grid oxide layer in the source end region through a patterned photoresist layer to form an opening, and injecting ions into the drift region through the opening to form a body region;
injecting ions into the openings from the top two ends of the body region obliquely by taking the photoresist layer as a mask to form a first type injection region;
forming a first barrier layer on the surfaces of the gate conductor layer and the body region; and
and implanting ions between the first type implantation regions at two ends of the body region through the first barrier layer to form a second type implantation region.
Preferably, the first barrier layer is recessed on the surface of the body region.
Preferably, the forming of the second-type implantation region further includes:
and partially etching the first barrier layer to expose the second type injection region and part of the first type injection region so as to form a second barrier layer.
Preferably, the width of the first type implant region within the body region is defined in accordance with the thickness of the photoresist layer.
Preferably, when the injection is performed obliquely, the angle between the injection direction and the normal of the surface of the substrate is 20-60 °.
Preferably, the first barrier layer has a recess width over the body region equal to the distance between the first-type implant regions, and the second-type implant regions are respectively adjacent to two of the first-type implant regions located at both ends of the body region.
Preferably, the second blocking layer is formed in the opening and is two side walls which are independent of each other and located on two side walls of the gate conductor layer on two sides of the opening.
Preferably, the thickness of the first barrier layer formed on both sidewalls of the gate conductor layer on both sides of the opening is greater than the thickness of the first barrier layer formed at a notch between the both sidewalls.
Preferably, the first barrier layer is etched by a dry etching process.
Preferably, the first barrier layer on the surface of the gate conductor layer and the surface of the second-type implantation region is completely etched, and the first barrier layer on the two sidewalls is partially etched to form the second barrier layer by adjusting the isotropic and anisotropic etching rates.
Preferably, the manufacturing method further includes:
forming a metal silicide layer between the second barrier layers and on the exposed surface of the gate conductor layer;
forming a dielectric layer on the surfaces of the metal silicide layer and the second barrier layer, wherein a through hole is formed in the dielectric layer above a region corresponding to the second type injection region and is communicated with the metal silicide layer;
and respectively forming a metal contact leading-out drain electrode, a grid electrode and a source electrode in the drain end region, the surface of the grid conductor layer and the through hole.
Preferably, the first type implantation region has a first doping type, the second type implantation region has a second doping type, the first doping type is P-type, and the second doping type is N-type; or, the first doping type is an N type, and the second doping type is a P type.
The invention has the beneficial effects that: the manufacturing method of the transverse double-diffusion transistor provided by the embodiment of the invention comprises the steps of forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; etching the gate conductor layer and the gate oxide layer in the source end region through the patterned photoresist, and injecting to form a body region; obliquely injecting the photoresist in the body region by using the photoresist as a mask to form a first type injection region; forming a first barrier layer on the surfaces of the gate conductor layer and the body region; second-type implant regions are formed between the first-type implant regions via the first barrier layer. The photoresist is used as a mask to be injected obliquely to form a first type injection region, the injection width of the injection region is controlled, the size of the injection region can be reduced, the size of a device is reduced, the source and drain on-resistance is effectively reduced, the process steps are greatly saved, the first type injection region is formed simply, the process difficulty is reduced, and the on-resistance of the device is reduced while the supply flow is simplified.
Furthermore, the first barrier layer covers the body region and the grid conductor layer, the opening position above the body region is in a concave shape, the semiconductor structure below the first barrier layer is protected, and the first barrier layer can be directly etched when the second barrier layer is formed subsequently, so that raw materials are saved, waste of barrier layer materials is avoided, process steps are saved, cost is saved, process steps are greatly simplified in the whole manufacturing process, and operation difficulty is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a to 1d are schematic cross-sectional views of a source end region at various stages in a conventional method for manufacturing a lateral double-diffused transistor, respectively;
fig. 2 shows a schematic cross-sectional structure of a lateral double diffused transistor in a source end region according to an embodiment of the invention;
fig. 3 shows a flow chart of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention;
fig. 4a to 4h respectively show schematic cross-sectional structures of a source end region at various stages in a method for manufacturing a lateral double-diffused transistor according to an embodiment of the present invention;
fig. 5a to 5f are schematic cross-sectional views of a source end region at various stages in a method for manufacturing a lateral double-diffused transistor according to another embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions. If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1a to fig. 1d respectively show schematic cross-sectional structures of source end regions in various stages of a conventional method for manufacturing a lateral double-diffused transistor, and a manufacturing process of the source end region of the lateral double-diffused transistor and its disadvantages will be briefly described below by taking an N-type lateral double-diffused transistor as an example.
As shown in fig. 1a, ion doping and diffusion are performed on top of an N-type doped semiconductor substrate 101, such as a silicon substrate, to form a drift region 102 with a certain ion concentration; then at least depositing a gate dielectric layer 111 and a polysilicon gate 112 on the surface of the semiconductor substrate 101 in sequence to form a mask layer, etching the gate dielectric layer 111 and the polysilicon gate 112 in the source end region of the semiconductor device by using a photoresist layer 113 coated on the polysilicon gate 112 as a barrier, performing ion doping and diffusion through the etched opening to form a body region 103 with a certain ion concentration, and then removing the photoresist layer to form a gate structure.
As shown in fig. 1b, a sidewall 121 is formed on a side surface of the gate structure, and when forming the sidewall 121, a deposition layer, such as a silicon dioxide layer, is formed on the surface of the polysilicon gate 112 and the body 103, and then the sidewall 121 is formed by an etching process. Then, a photoresist layer 114 is deposited on the surfaces of the polysilicon gate 112 and the body region 103, and a first doping type ion implantation is performed through the patterned photoresist layer 114 by using a photolithography process and a mask to form two N + implantation regions having source end regions below the side walls 121 and located at two ends of the top of the body region 103. Due to the possible slippage of the photoresist 114 on the surface of the body region 103 and the precision limitations of the photolithography process itself, the size of the N + implant region cannot be made small to ensure that it can perform its function. For example, in the NLDMOS of 180nm process, each implant region width reaches about 0.4 um.
As shown in fig. 1c, after the implantation of the N + source region is completed, the photoresist is removed, and then the photoresist layer 115 is deposited on the surface of the semiconductor structure again, an opening is left in the middle of the photoresist layer 115, and the width of the opening is the width of the gap between the two N + source regions. Ion implantation of the second doping type is performed at the top of the body region 103 through self-alignment by using a photolithography process and a mask to form a P + implantation region, i.e., a body contact region, between the two N + source regions. The N + source region is doped N-type, the P + body contact region is doped P-type, the N-type doped ions include but are not limited to phosphorous ions or arsenic ions, and the P-type doped ions include but are not limited to boron ions. For the same reasons as described above, the width of the P + body contact region cannot be too small, also around 0.4um in the above process, and then the total width of the implanted region within the entire body region 103 reaches around 1.2um, whereby the width of the body region 103 cannot be too small or the device performance cannot be achieved.
As shown in fig. 1d, the photoresist is removed, and a metal silicide layer 151 is formed on the surfaces of the polysilicon gate 112 and the body region 103, wherein the metal silicide layer 151 is a metal silicide (silicide), which is typically TiSi2 (titanium silicide) film; then depositing a dielectric layer 161, wherein the dielectric layer 161 is used for providing isolation and protection; subsequently, a via 162 penetrating to the surface of the metal silicide layer corresponding to the source terminal region is formed on the dielectric layer 161 by etching, and a source electrode is led out by forming a metal contact, thereby completing the fabrication of the LDMOS.
According to the above description, since the N + implantation region and the P + implantation region in the LDMOS are formed by re-implantation through a photolithography process, the size of the formed implantation region is not too small due to the photolithography capability. The width between the side measuring walls 121 is about 1.2 um. On the basis of the structure, the on-resistance between the source end and the drain end of the LDMOS device is very large, so that the performance of the LDMOS device is reduced, and the application prospect of the LDMOS device is influenced. In addition, the LDMOS has the advantages of complex manufacturing process, complex steps, difficulty in operation and high cost.
Based on the method, the size of a source region of a multi-source region can be reduced through improvement and optimization of a manufacturing process, the size of a formed device is reduced, the on-resistance of a source and a drain is effectively reduced, the process steps can be greatly reduced, the process flow is simplified, and the method is convenient to implement.
Fig. 2 shows a schematic cross-sectional structure diagram of a lateral double-diffused transistor in a source end region according to an embodiment of the present invention.
Referring to fig. 2, an LDMOS device provided in an embodiment of the present invention is the same as the LDMOS structure introduced in fig. 1d, and further includes: the semiconductor device comprises a substrate 201 with a first doping type, a drift region 202 with a second doping type and a body region 203 with the first doping type, wherein the drift region 202 is located in the substrate 201 and is arranged around the body region 203, the body region 203 and the drift region 202 are formed in the substrate 201 and are used for transmitting electrons to achieve electrical conduction, and the doping concentrations of the body region 203 and the drift region 202 are different so as to obtain different conduction performances; and a source region, a drain region, a gate structure, a sidewall spacer 261, a metal silicide layer 271, a dielectric layer 281, and an opening 282 on the substrate 201.
The source end region is communicated with the body region 203, and the drain end region is communicated with the drift region 102 and is used for electrically connecting the input of external voltage; the gate structure includes a gate conductor layer 212 and a gate oxide layer 211 located between the gate conductor layer 212 and the substrate 201, a sidewall 261 is formed on a sidewall of the gate structure, a part of the metal silicide layer 271 covers an upper surface of the source end region, another part covers an upper surface of the gate structure, the source end region has an N + injection region and a P + injection region which are independent of each other and are not included, in this embodiment, the source end region includes an N + injection region, a P + injection region and an N + injection region which are adjacent in sequence, and the widths of the three regions formed by process control are the same.
The dielectric layer 281 is located on the surface of the metal silicide layer 271, and has a via penetrating to the surface of the metal silicide layer 271 in the upper center of the source end region, and the via is used for leading out the source electrode.
In the lateral double-diffused transistor device formed by the method for manufacturing the lateral double-diffused transistor provided by the embodiment of the invention, the N + injection region, the P + injection region and the N + injection region which are positioned in the source region, are sequentially connected and mutually independent and do not contain each other can be free from the limitation of the photoetching process capability compared with the prior art, and the three formed injection regions have smaller widths, namely, the interval of the polycrystalline silicon layer above the source end region in the grid structure is also smaller, so that the lateral double-diffused transistor device has smaller source-drain on-resistance. The method for manufacturing the LDMOS of the present invention is described below with reference to a flow chart and a cross-sectional structure diagram of a process flow.
Fig. 3 shows a flow chart of a method of manufacturing a lateral double diffused transistor according to an embodiment of the invention; fig. 4a to 4h respectively show schematic cross-sectional structures of a source end region at various stages in a method for manufacturing a lateral double-diffused transistor according to an embodiment of the present invention.
The method for manufacturing the lateral double diffused transistor of the present application is described below with reference to fig. 3 to 4 h.
In step S110, a drift region is formed on top of a substrate.
Referring to fig. 4a, ion doping and diffusion are performed in an N-type doped semiconductor substrate 201 such as a silicon substrate to form a drift region 202 of a first doping type having a certain ion concentration, and the formation of the drift region 202 is a conventional step and is not specifically described.
In step S120, a gate oxide layer and a gate conductor layer stacked in sequence are formed on the surface of the drift region, and the gate conductor layer defines a drain region and a source region that are separated from each other.
As shown in fig. 4b, a gate oxide layer 211 and a gate conductor layer 212 are sequentially deposited on the surface of the drift region 202 of the semiconductor substrate 201 to form a gate structure, and the sequentially stacked gate oxide layer 211 and gate conductor layer 212 define a drain region and a source region which are isolated from each other, and only the structure of the source region is shown in the figure. The gate oxide layer 211 is, for example, a silicon oxide layer, and the gate conductor layer 212 is, for example, a polysilicon layer. The formation process of the gate oxide layer 211 and the gate conductor layer 212 is conventional and not limited herein, and the gate conductor layer 212 is formed by deposition of chemical vapor deposition, for example. Meanwhile, from the scheme implementation point of view, another dielectric layer may be further disposed between the gate oxide layer 211 and the gate conductor layer 212, or another dielectric layer may be further disposed below the gate oxide layer 211 or above the gate conductor layer 212.
In step S130, the gate conductor layer and the gate oxide layer are etched in the source region through the patterned photoresist layer, an opening is formed, and ions are implanted into the drift region through the opening to form a body region.
Still referring to fig. 4b, a photoresist layer 213 is disposed on the surface of the gate conductor layer 212, the gate conductor layer 212 and the gate oxide layer 211 are sequentially etched through the patterned photoresist layer 213 by using the coated photoresist layer 213 as a barrier to form an opening for injecting the body region 203, the body region 203 of the second doping type having a certain ion concentration is formed in the drift region 202 through ion doping and diffusion through the opening, and then the photoresist layer is removed. Taking LDMOS of 180nm technology as an example, the width of the opening is about 0.6um, and the photoresist layer 213 limits the width of the opening. The opening of this width is provided here because it is sufficient to carry out the implantation of the source region in the subsequent process.
In step S140, ions are respectively implanted into the top of the body region from the openings in an oblique direction by using the photoresist layer as a mask to form first type implantation regions.
As shown in fig. 4c, the photoresist layer 213 used in the previous step is retained, and at the opening, the photoresist layer 213 is used as a mask, and a tilted large-angle implantation process is adopted to implant first-type doped regions into two ends of the top of the body region from the left and right sides, respectively, as shown in the figure, along the directions indicated by two arrows L1 and L2, so as to form two first-type implanted regions. The first type injection region comprises a first N + injection region and a second N + injection region, and the N + injection region is an N + source region. In this step, the left N + implant region is formed by left implantation from the direction of the arrow of the right L1, and the right N + implant region is formed by right implantation from the direction of the arrow of the left L2. By adopting the process, the width of the N + source region (N + injection region) is reduced to about 0.2 um. In addition, the width of the first type implant region within the body region 203 is defined according to the thickness of the photoresist layer 213. The thickness of the photoresist layer 213 is adjusted to obtain a suitable width of the N + implantation region. Under the condition that the photoresist layer 213 with a certain thickness is used as a mask, an oblique implantation process is adopted, so that the doped ions of the N + implantation area can only diffuse in a certain fixed area pointed by an arrow, and a certain width is ensured. After the implantation is completed, the photoresist layer 213 is removed.
Furthermore, when the injection is performed obliquely, the included angle between the injection direction and the normal of the surface of the substrate is 20-60 degrees, so that the width of the N + injection region is ensured.
In step S150, a first barrier layer is formed on the surfaces of the gate conductor layer and the body region. Furthermore, the first barrier layer is concave on the surface of the body region.
As shown in fig. 4d, a first barrier layer 221 is formed on the surface of the gate conductor layer 212 and the body region 203, specifically, a deposition layer is deposited on the surface of the semiconductor structure, and then an etching process is used to form the first barrier layer. For example, the first barrier layer 221 is formed by depositing a silicon oxide layer by using a chemical vapor deposition process and then forming an etching process; or by forming a silicon oxide layer first, then forming a silicon nitride layer, and then using an etching process, the cross section of the formation structure in the source end region is as shown in fig. 4 d. The deposited layer is etched, for example by dry etching, to form a first barrier layer 221, the first barrier layer 221 having a concave shape at the surface of the body region 203, and an opening above the body region 203 having a funnel shape with a wider diameter. The first barrier layer 221 is thicker on both sidewalls of the gate conductor layer 212 above the body region 203, while the portion of the surface of the body region 203 between the sidewalls is thinner, which is not enough to block the subsequent implantation, i.e., the thickness of the first barrier layer 221 formed on both sidewalls of the gate conductor layer 212 on both sides of the opening is greater than the thickness of the first barrier layer 221 formed at the recess in the middle of the two sidewalls. A thin layer of deposition on the surfaces of the gate conductor layer 212 and the body region 203 may protect the semiconductor structure. Here a first etch of the deposited layer, forms a first barrier layer 221. Further, the width of the bottom of the recess of the first barrier layer in the shape of a Chinese character 'ao' is the same as the width of the gap between the two N + implantation regions, so as to define the width of the second type implantation region to be implanted later.
In step S160, ions are implanted between the first-type implant regions at both ends of the body region via the first barrier layer to form a second-type implant region.
As shown in fig. 4e, a second-type implantation region is implanted under the recess of the recessed first barrier layer 221 through the first barrier layer 221 by self-alignment to form a second-type implantation region between the first-type implantation regions, wherein the second-type implantation region is a P + implantation region, i.e., a P + body contact region. The width of the recess of the first barrier layer 221 above the body region 203 is equal to the distance between the first type implant regions, and the second type implant regions are adjacent to two first type implant regions located at both ends of the body region 203, respectively. The first type implantation region has a first doping type, and the second type implantation region has a second doping type. The material of the first sidewall 221 may be, but is not limited to, silicon dioxide or silicon nitride. The thin first barrier layer 221 remained on the surface of the semiconductor structure in the previous step not only protects and isolates the structure, but also does not affect the implantation of the implanted region.
In step S170, the first barrier layer is partially etched to expose the second type implantation region and a portion of the first type implantation region, so as to form a second barrier layer.
As shown in fig. 4f, the first blocking layer 221 is etched again by using a dry etching process, the blocking layers on the surfaces of the body region 203 and the gate conductor layer 212 are removed, so that the second-type implantation region and a part of the first-type implantation region are exposed, and the remaining non-etched blocking layer forms a second blocking layer 261. By adjusting the isotropic and anisotropic etching rates, the first barrier layers 221 on the surface of the gate conductor layer 212 and the surface of the second-type implantation region are completely etched, and the first barrier layers 221 on both sidewalls of the gate conductor layer 212 on both sides of the opening are partially etched to form the second barrier layer 261.
The first barrier layer 221 has a relatively thick thickness on the sidewalls of the two sides of the opening, and during the etching process, anisotropic etching and isotropic etching are simultaneously used, so that the finished barrier layer only has a certain thickness on the sidewalls of the two sides of the opening. By adjusting the isotropic and anisotropic etching rates, the width of the formed second barrier layer 261 is, for example, 0.2um, which is easily realized in the existing 180nm process.
Further, the second blocking layer 261 is two mutually independent sidewalls formed in the opening and located on two sidewalls of the gate conductor layer 212 on two sides of the opening. The height of the surface of the sidewall 261 is equal to the height of the edge of the gate conductor layer 212 located at both sides thereof. In addition, the thickness of the first barrier layer 221 formed on both sidewalls is greater than the thickness of the second barrier layer 261 formed on both sidewalls.
In the step, the deposition layer is etched for the second time, the first etching forms the first barrier layer 221, the second etching forms the second barrier layer 261, namely, the first barrier layer is etched step by step to form the second barrier layer 261, so that the material of the deposition layer is saved, and the cost is saved. In the conventional scheme, after the second type injection region is injected, the first barrier layer needs to be removed, and then the second barrier layer needs to be formed by re-deposition and etching, so that raw materials are wasted. In the embodiment, the deposited layer is not completely etched when being etched for the first time to form the first barrier layer, so that one layer is reserved, namely, the semiconductor structure is protected, the injection cannot be influenced, the etching can be performed on the basis of the original first barrier layer during the second etching, the re-deposition is not needed, and the process steps are saved.
Compared with the traditional manufacturing process, the manufacturing method of the embodiment simplifies the processes of forming the N + injection region and forming the second barrier layer, so that the process steps are simpler and easier to operate, the cost is greatly saved, and the operation complexity is reduced. The manufactured LDMOS structure is more reliable, the size optimization of the device can be realized, the size of the device is reduced, and the on-resistance is reduced.
In summary, the photoresist layer is used as a mask, and the N + injection region is formed by oblique injection, so that the width of the N + injection region is reduced, the process complexity is reduced, and the use of a plurality of masks and photoresist layers is reduced. By taking an N-type LDMOS device with a 180nm technology as a reference, the total width of the injection region obtained in the embodiment can be reduced to 0.6um, the size of the formed device is greatly reduced, and the source-drain on-resistance is reduced.
The process of fig. 4g and 4h is similar to the conventional LDMOS process.
Further, the method for manufacturing a lateral double-diffused transistor of the present embodiment further includes: a metal silicide layer is formed between the second barrier layers 261 and on the exposed surface of the gate conductor layer 212.
As shown in fig. 4g, a metal silicide layer 271 is formed, wherein the metal silicide layer 271(silicide) is typically TiSi2 (titanium silicide) thin film, and is formed by depositing a polysilicon layer on the surface of the source end region after removing the mask, depositing a metal layer (typically Ti, Co or Ni) on the surface of the polysilicon layer and the gate structure by sputtering, and then performing rapid temperature rise annealing (RTA) to react the polysilicon surface and the deposited metal to form a metal silicide, so as to isolate and protect the semiconductor structure and prevent it from reacting with other deposited layers.
The manufacturing method further includes: and forming a dielectric layer on the surfaces of the metal silicide layer and the second barrier layer, wherein a through hole is formed in the dielectric layer above the region corresponding to the second type injection region and is communicated with the metal silicide layer.
As shown in fig. 4h, a dielectric layer 281 is deposited, which dielectric layer 281 is used to provide isolation, and the cross-section of the deposited structure in the source end region is shown. A dielectric layer 281 is deposited on the surface of the metal silicide layer 271 and the second blocking layer 261, and the dielectric layer 281 is used to provide isolation protection and may be, but not limited to, silicon nitride.
Then, a via hole is etched by a hole reticle to form a via hole penetrating to the surface of the metal silicide layer 271 (metal silicide layer) corresponding to the source region, the drain region and the gate structure, and the cross section of the formation structure in the source region is as shown in the figure. For example, a via 282 is formed by etching the dielectric layer 281 through to the surface of the metal silicide layer corresponding to the second-type implantation region, and then a metal contact is formed by leading out the source electrode through the via 282, wherein the diameter of the via 282 is equivalent to the width of the second-type implantation region, or the area of the via is equivalent to the area of the surface of the second-type implantation region. The dielectric layer 281 is etched by using a hole photolithography mask, and due to the existence of the metal silicide layer 271, the N + source region is communicated with the P + body contact region and is led out through the through hole 282, so that the arrangement of metal wires is saved.
The manufacturing method further includes: and respectively forming a metal contact leading-out drain electrode, a grid electrode and a source electrode in the drain terminal region, the surface of the grid conductor layer and the through hole.
The source electrode, the drain electrode and the gate electrode are respectively led out by forming metal contacts. Thus, the fabrication of the LDMOS of this embodiment is completed. In general, in practical applications, the substrate electrode and the source electrode are commonly connected, and therefore, in the present embodiment, the substrate electrode and the source electrode are collectively referred to as the source electrode.
The first doping type is P type, and the second doping type is N type; or the first doping type is N type, and the second doping type is P type. The N-type dopant ions include, but are not limited to, phosphorous ions or arsenic ions, and the P-type dopant ions include, but are not limited to, boron ions.
According to the manufacturing method of the embodiment, the size of the injection region of the source end region of the formed LDMOS is reduced, so that the whole size of the device is reduced, the on-resistance is reduced, the performance of the device is improved, and the manufacturing process is simple, easy to operate and convenient to implement.
It should be noted that the above description is mainly a schematic cross-sectional structure of the source region of the LDMOS device in the prior art and at each stage in the forming process, and the structure of the drain region of the device can be understood by referring to the common general knowledge in the prior art, which is not described in detail herein.
Further, the above embodiments of the present invention are described with reference to an N-type LDMOS device and a method for manufacturing the same, but the present invention is not limited thereto, and is also applicable to the manufacture of a P-type LDMOS device. In addition, the 180nm process is taken as an example in the present invention, but the present invention is also applicable to other process nodes, and is not limited herein.
Fig. 5a to 5f are schematic cross-sectional views of a source end region at various stages in a method for manufacturing a lateral double-diffused transistor according to another embodiment of the present invention.
The process steps in fig. 5 a-5 c are the same as in fig. 4 a-4 c and will not be described herein and will be apparent to one skilled in the art.
The difference of this embodiment is that, in fig. 5d, a first barrier layer 321 is formed, where the first barrier layer 321 is a sidewall formed on sidewalls on two sides of an opening above the body region 203, and has a thicker thickness, and a width of a gap between the sidewalls is an implantation width of the second type implantation region, and then a P + implantation region is formed by implantation.
In fig. 5e, the first barrier layer 321 needs to be removed first, then an oxide layer and the like are deposited again, and a second barrier layer 361 is formed by etching, where the second barrier layer 361 is also a sidewall. From the process steps of fig. 5e to 5f, reference may be made to the process steps of fig. 4 f-4 h.
The LDMOS structure obtained by the embodiment has the advantages of small size, simple process steps, small on-resistance and improved device performance.
In summary, the method for manufacturing a lateral double diffused transistor according to the embodiment of the invention includes forming a drift region in a substrate; forming a gate oxide layer and a gate conductor layer on the surface of the drift region; etching the gate conductor layer and the gate oxide layer in the source end region through the patterned photoresist, and injecting to form a body region; obliquely injecting the photoresist in the body region by using the photoresist as a mask to form a first type injection region; forming a first barrier layer on the surfaces of the gate conductor layer and the body region; forming second-type implantation regions between the first-type implantation regions via the first barrier layer; and partially etching the first barrier layer to expose the second type injection region and part of the first type injection region to form a second barrier layer, obliquely injecting photoresist as a mask to form the first type injection region, controlling the injection width of the injection region, and then etching the first barrier layer step by step, so that the size of the injection region can be reduced, the size of a device is reduced, the source-drain on-resistance is effectively reduced, raw materials can be saved, the waste of barrier layer materials is avoided, the cost is saved, the whole manufacturing process greatly simplifies the process steps, reduces the operation difficulty, and the on-resistance of the device is reduced while the supply flow is simplified.
In addition, in the manufacturing process of the LDMOS device in which the channel region is formed by using the Shielded Gate Trench (SGT) process, part or all of the steps in the manufacturing method of the LDMOS device provided in the above embodiment may also be applied to form the extraction of the source electrode with a small size, that is, the distance between the polysilicon layer in the Gate structure above the source end region is reduced, the size of the formed device may also be reduced, and the source-drain on-resistance is reduced.
Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (12)
1. A method of fabricating a lateral double diffused transistor, comprising:
forming a drift region on top of a substrate;
forming a gate oxide layer and a gate conductor layer which are stacked in sequence on the surface of the drift region, wherein the gate conductor layer defines a drain end region and a source end region which are separated from each other;
etching the grid conductor layer and the grid oxide layer in the source end region through a patterned photoresist layer to form an opening, and injecting ions into the drift region through the opening to form a body region;
injecting ions into the openings from the top two ends of the body region obliquely by taking the photoresist layer as a mask to form a first type injection region;
forming a first barrier layer on the surfaces of the gate conductor layer and the body region; and
and implanting ions between the first type implantation regions at two ends of the body region through the first barrier layer to form a second type implantation region.
2. The method of manufacturing of claim 1, wherein the first barrier layer is reentrant at the body surface.
3. The method of manufacturing of claim 2, wherein the forming the second type implant region further comprises:
and partially etching the first barrier layer to expose the second type injection region and part of the first type injection region so as to form a second barrier layer.
4. The method of manufacturing of claim 1, wherein a width of the first type implant region within the body region is defined according to a thickness of the photoresist layer.
5. The manufacturing method according to claim 1, wherein, in the oblique injection, an angle between an injection direction and a normal to the surface of the substrate is 20 to 60 °.
6. The method of manufacturing of claim 2 wherein said first barrier layer has a recess width over said body region equal to the distance between said first type implant regions, said second type implant regions being contiguous with two of said first type implant regions respectively located at either end of said body region.
7. The manufacturing method according to claim 3, wherein the second barrier layer is formed in the opening and is formed on two sidewalls of the gate conductor layer on two sides of the opening, wherein the two sidewalls are independent of each other.
8. The manufacturing method according to claim 7, wherein a thickness of the first barrier layer formed on both sidewalls of the gate conductor layer on both sides of the opening is larger than a thickness of the first barrier layer formed at a notch between the both sidewalls.
9. The manufacturing method according to claim 7, wherein the first barrier layer is etched using a dry etching process.
10. The manufacturing method according to claim 9, wherein the first barrier layer on the surface of the gate conductor layer and the surface of the second-type implantation region is completely etched and the first barrier layer on the two sidewalls is partially etched by adjusting the isotropic and anisotropic etch rates to form the second barrier layer.
11. The manufacturing method according to claim 1, wherein the manufacturing method further comprises:
forming a metal silicide layer between the second barrier layers and on the exposed surface of the gate conductor layer;
forming a dielectric layer on the surfaces of the metal silicide layer and the second barrier layer, wherein a through hole is formed in the dielectric layer above a region corresponding to the second type injection region and is communicated with the metal silicide layer;
and respectively forming a metal contact leading-out drain electrode, a grid electrode and a source electrode in the drain end region, the surface of the grid conductor layer and the through hole.
12. The method of manufacturing of claim 1, wherein the first type implant region has a first doping type, the second type implant region has a second doping type, the first doping type is P-type, the second doping type is N-type; or, the first doping type is an N type, and the second doping type is a P type.
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| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
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