CN117080078A - Method for preparing MOS device based on composite film layer self-alignment process and device - Google Patents
Method for preparing MOS device based on composite film layer self-alignment process and device Download PDFInfo
- Publication number
- CN117080078A CN117080078A CN202311337100.9A CN202311337100A CN117080078A CN 117080078 A CN117080078 A CN 117080078A CN 202311337100 A CN202311337100 A CN 202311337100A CN 117080078 A CN117080078 A CN 117080078A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon dioxide
- photoresist
- etching
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 81
- 230000008569 process Effects 0.000 title claims abstract description 43
- 239000002131 composite material Substances 0.000 title claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 156
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 78
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 78
- 238000005530 etching Methods 0.000 claims abstract description 64
- 239000000463 material Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 28
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000011049 filling Methods 0.000 claims abstract description 12
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 64
- 239000007943 implant Substances 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 16
- 238000004528 spin coating Methods 0.000 claims description 14
- 238000002513 implantation Methods 0.000 claims description 6
- 229910016570 AlCu Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- NEXSMEBSBIABKL-UHFFFAOYSA-N hexamethyldisilane Chemical compound C[Si](C)(C)[Si](C)(C)C NEXSMEBSBIABKL-UHFFFAOYSA-N 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 6
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 238000012876 topography Methods 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 136
- 238000010586 diagram Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 210000004027 cell Anatomy 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002318 adhesion promoter Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000011197 physicochemical method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- KFZUDNZQQCWGKF-UHFFFAOYSA-M sodium;4-methylbenzenesulfinate Chemical compound [Na+].CC1=CC=C(S([O-])=O)C=C1 KFZUDNZQQCWGKF-UHFFFAOYSA-M 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 210000000225 synapse Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The application provides a method for preparing a Metal Oxide Semiconductor (MOS) device based on a composite film layer self-alignment process and the device, wherein the method comprises the following steps: sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked; etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region; cutting the PWAll area into two disconnected parts by etching, and filling the cut parts by P-type materials; and removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process. Through setting up shielding layer and mask layer, through compound film layer self-alignment technology, solved the inaccurate problem of overlay technology, realized preparing the minimum MOS device of channel length, on the other hand, avoided the great aspect ratio of traditional self-alignment mask to bring the sculpture topography problem.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a method for preparing a MOS device based on a composite film layer self-alignment process and the device.
Background
The Vertical Double-diffusion metal oxide semiconductor field effect transistor (VDMOS) has high input impedance, fast switch response speed, and smart utilization of excellent characteristics of substrate materials, such as strong critical breakdown field of SiC materials, can be used for high-voltage devices, and is widely applied to various fields of industrial control, inverters, new energy charging piles and the like.
In general, the device of the VDMOS is prepared by sequentially forming a PWAll region, an N+ region, a P+ region and the like through repeated mask and photoetching alignment and ion implantation, however, the preparation of a short channel device is limited by the limit of a machine table of a photoetching machine, in addition, the operation difficulty of the photoetching process is greatly challenged by repeated photoetching alignment process, the problems of inaccurate alignment, large alignment deviation and the like are easy to occur, the preparation of the MOS device is challenged, and on the other hand, the non-composite film structure adopted by the traditional self-aligned mask has a larger depth-to-width ratio, and the control of etching morphology and CD (critical dimension) is problematic for the dry process.
Disclosure of Invention
In view of the foregoing, the present application has been developed to provide a method and device for fabricating a MOS device based on a composite film self-aligned process that overcomes or at least partially solves the foregoing, comprising:
a method for preparing a MOS device based on a composite film layer self-alignment process comprises the following steps:
sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked;
etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region;
cutting the PWAll area into two disconnected parts by etching, and filling the cut parts by P-type materials;
and removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process.
Further, the step of etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape and performing ion implantation to form a PWell region and an n+ region includes:
spin-coating photoresist on the top of the first silicon dioxide layer according to a preset etching shape;
removing the first silicon dioxide layer and the polysilicon layer which are not in the photoresist protection by etching;
removing the photoresist and forming a PWAll region through ion implantation;
and removing the first silicon dioxide layer, depositing a second silicon dioxide layer, carrying out back etching on the second silicon dioxide layer, and carrying out ion implantation to form an N+ region.
Further, the step of spin-coating photoresist on top of the first silicon dioxide layer according to a preset etching shape includes:
firstly spin-coating hexamethyldisilane on the top of the first silicon dioxide layer, and then spin-coating photoresist;
removing the edge photoresist for 2mm, and performing soft baking at 110 ℃;
the exposure was performed through PW plate.
Further, the step of removing the photoresist and forming a PWell region by ion implantation includes:
removing surface photoresist by a dry photoresist removing method, and removing photoresist residues by a wet photoresist removing method;
the PWell region is formed by five ion implants, where the energy of the first implant: 450keV, dose: 4E14, angle: 0 °, temperature: 500 ℃; energy of the second implant: 380keV, dose: 4E13, angle: 0 °, temperature: 500 ℃ C:: energy of the third implant: 260keV, dose: 3.6E12, angle: 0 °, temperature: 500 ℃; energy of the fourth implant: 160keV, dose: 1.5E12, angle: 0 °, temperature: 500 ℃.
Further, the step of removing the first silicon dioxide layer and depositing a second silicon dioxide layer, carrying out back etching on the second silicon dioxide layer and carrying out ion implantation to form an N+ region comprises the following steps:
removing the first silicon dioxide layer and depositing a second silicon dioxide layer according to a preset channel length;
protecting the second silicon dioxide layer below the ion implantation position when the PWAll region is formed through photoresist exposure, and carrying out back etching on the exposed part of the second silicon dioxide layer;
and removing the photoresist and performing N+ implantation to form an N+ region.
Further, the step of removing the photoresist and performing n+ implantation to form an n+ region includes:
removing the photoresist by a wet photoresist removing process;
and performing ion implantation step by step for a plurality of times through a preset N+ layout to form an N+ region.
Further, the step of cutting the PWell region into two non-connected parts by etching and filling the cut parts by P-type material includes:
removing all materials on the top of the silicon carbide epitaxial wafer, and depositing a third silicon dioxide layer;
protecting a preset area through photoresist exposure, and etching the exposed position to enable the PWAll area to form two parts which are completely disconnected;
and filling the groove etched in the PWAll region by growing a P-type doped wide bandgap semiconductor in situ.
Further, the step of removing all materials on the top of the silicon carbide epitaxial wafer and forming a MOS device through a device manufacturing process comprises the following steps:
removing all materials on the top of the silicon carbide epitaxial wafer;
and sequentially preparing a gate oxide layer, gate Poly metal, an ILD dielectric isolation layer, source contact metal, a passivation layer, a PI layer and a metal layer on the back.
Further, the step of sputtering a preset metal to generate a metal layer comprises the following steps:
sequentially sputtering 100nm Ti and 50nm TiN;
AlCu at 4000nm was sputtered, with a Cu content of 0.5%.
A MOS device prepared by the method of any one of the preceding claims.
The application has the following advantages:
in the embodiment of the application, compared with the problems of inaccurate alignment and large alignment deviation of the multiple alignment processes in the prior art, the application provides a solution for preparing an MOS device by taking silicon nitride, polysilicon and silicon dioxide as composite film layers through a self-alignment process, which comprises the following steps: sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked; etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region; cutting the PWAll area into two disconnected parts by etching, and filling the cut parts by P-type materials; and removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process. Through setting up shielding layer and mask layer, through compound film layer self-alignment technology, solved the inaccurate problem of overlay technology, realized preparing the minimum MOS device of channel length, on the other hand, avoided the great aspect ratio of traditional self-alignment mask to bring the sculpture topography problem.
Drawings
For a clearer description of the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art;
fig. 1 is a flowchart of steps in a method for manufacturing a MOS device based on a composite film self-aligned process according to an embodiment of the present application;
fig. 2-20 are block diagrams of MOS devices in the process of manufacturing the MOS devices according to the method for manufacturing a MOS device based on a composite film self-aligned process according to an embodiment of the present application;
FIG. 21 is a block diagram of an N+ layout of a method for fabricating a MOS device based on a composite film self-aligned process according to an embodiment of the present application;
FIG. 22 is a block diagram of a layout CT version of a method for fabricating a MOS device based on a composite film self-aligned process according to an embodiment of the present application;
fig. 23 is a schematic structural diagram of a MOS device according to an embodiment of the present application;
fig. 24 is a block diagram of a MOS device and an internal circuit configuration of the device according to an embodiment of the present application.
Detailed Description
In order that the manner in which the above recited objects, features and advantages of the present application are obtained will become more readily apparent, a more particular description of the application briefly described above will be rendered by reference to the appended drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The inventors found by analyzing the prior art that: in the prior art, p+ injection is added between two VDMOS device cells, the PWAll area is completely opened, the N+ area of two semicircular cells is exposed, the size of a source electrode contact hole of the structure is large, the preparation of an integrated device is not facilitated, and an elimination method cannot be considered for channel effect of SiC device ion injection.
Referring to fig. 1, a method for manufacturing a MOS device based on a composite film self-alignment process according to an embodiment of the present application is shown;
the method comprises the following steps:
s110, sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked;
s120, etching the polycrystalline silicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region;
s130, cutting the PWAll area into two unconnected parts by etching, and filling the cut parts by P-type materials;
and S140, removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process.
In the embodiment of the application, compared with the problems of inaccurate alignment and large alignment deviation of the multiple alignment processes in the prior art, the application provides a solution for preparing an MOS device by taking silicon nitride, polysilicon and silicon dioxide as composite film layers through a self-alignment process, which comprises the following steps: sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked; etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region; cutting the PWAll area into two disconnected parts by etching, and filling the cut parts by P-type materials; and removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process. Through setting up shielding layer and mask layer, through compound film layer self-alignment technology, solved the inaccurate problem of overlay technology, realized preparing the minimum MOS device of channel length, on the other hand, avoided the great aspect ratio of traditional self-alignment mask to bring the sculpture topography problem.
Next, a method of manufacturing a MOS device based on the composite film self-alignment process in the present exemplary embodiment will be further described.
Sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer as described in the step S110; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked.
It should be noted that the use of silicon nitride as the implanted shield layer prevents channeling and the dry etch endpoint is easy to grasp, the polysilicon layer and the silicon dioxide layer act as mask layers for the self-aligned process.
In one embodimentSelecting a silicon carbide epitaxial wafer, wherein the epitaxial concentration is as follows: 1e16cm -3 Epitaxial thickness: 10um, followed by cleaning by RCA standard to remove contamination and surface native oxide, followed by full JFET implantation in the active area, followed by deposition of 50nm silicon nitride, 1.2 um polysilicon, 0.6 um silicon dioxide, where silicon nitride and silicon dioxide can be obtained by PECVD deposition, the polysilicon being prepared by LPCVD process, the post deposition structure being shown in fig. 2.
Sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer as described in the step S120; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked.
In one embodiment of the present application, the step S120 of depositing a shielding layer and a mask layer sequentially on a silicon carbide epitaxial wafer may be further described in conjunction with the following description; the mask layer is a specific process of sequentially stacking a polysilicon layer and a first silicon dioxide layer.
Spin-coating photoresist on the top of the first silicon dioxide layer according to a preset etching shape;
removing the first silicon dioxide layer and the polysilicon layer which are not in the photoresist protection by etching as follows;
the silicon dioxide layer and the polysilicon layer of the composite mask layer except the photoresist protection are etched by dry etching, wherein the etching gas of the silicon dioxide is CF 4 ，CHF 3 The main gas of polysilicon etching is Cl 2 The etching end point is to judge and stop etching by detecting the change of light intensity in the etching process, the etching end point of the etching is the surface of the silicon nitride layer, and compared with the traditional silicon dioxide, the used silicon nitride is not easy to etch, the over etching amount is well controlled, the effect of retaining the shielding layer is good, and the etched structure is shown in figure 4.
Removing the photoresist and forming a PWAll region by ion implantation as follows;
and removing the first silicon dioxide layer, depositing a second silicon dioxide layer, carrying out back etching on the second silicon dioxide layer, and carrying out ion implantation to form an N+ region.
In one embodiment of the present application, the specific process of "spin coating photoresist on top of the first silicon dioxide layer according to a predetermined etching shape" may be further described in conjunction with the following description.
The method comprises the following steps of firstly spin-coating hexamethyldisilane on the top of the first silicon dioxide layer, and then spin-coating photoresist;
removing the edge photoresist by 2mm, and performing soft baking at 110 ℃;
the exposure was performed by PW plate as described in the following steps.
In one embodiment, hexamethyldisilane is spin-coated as an adhesion promoter on the semiconductor surface, wherein the coating temperature is 110 ℃, then 1.3um Photoresist (PR) is spin-coated, and EBR removes the edge photoresist 2mm, then 110 ℃ soft bake is performed for 1min, then PW plate exposure is performed, and after development, as shown in FIG. 3, wherein the gumming developer is a core source micro KS-S150-2C2D model device, spin-coating hexamethyldisilane and spin-coating, EBR edge removing, and soft bake are all performed in the device, and the lithographic device is a Nikon I series model of NSR-2005I8A lithography machine.
In one embodiment of the present application, a specific process of removing the photoresist and forming the PWell region by ion implantation may be further described in conjunction with the following description.
Removing surface photoresist by dry photoresist removal and removing photoresist residues by wet photoresist removal;
the PWell region is formed by five ion implants, with the energy of the first implant as follows: 450keV, dose: 4E14, angle: 0 °, temperature: 500 ℃; energy of the second implant: 380keV, dose: 4E13, angle: 0 °, temperature: 500 ℃ C:: energy of the third implant: 260keV, dose: 3.6E12, angle: 0 °, temperature: 500 ℃; energy of the fourth implant: 160keV, dose: 1.5E12, angle: 0 °, temperature: 500 ℃.
In a specific implementation, the photoresist on the upper surface layer is removed by a dry photoresist removing device, then the photoresist residue is completely removed by SPM 10min, 120deg.C+DHF10 min, 23deg.C+Sc110 min, 60deg.C+Sc210 min and 70deg.C wet cleaning, and then the doping of P+ (PWAll) is realized by ion implantation for a plurality of times by a new implantation machine with the model of Impheat-II. Multiple step box implants result in a p+ (PWell) region with a uniform doping profile as shown in fig. 5.
In one embodiment of the present application, the specific process of "removing the first silicon dioxide layer and depositing the second silicon dioxide layer, etching back the second silicon dioxide layer and performing ion implantation to form an n+ region" may be further described in conjunction with the following description.
Removing the first silicon dioxide layer and depositing a second silicon dioxide layer according to a preset channel length;
in a specific implementation, the first silicon dioxide mask layer above the polysilicon is removed by using a BOE etching solution, where the rate of etching silicon dioxide by the BOE etching solution is about 2500A/min, and the removed structure is shown in FIG. 6. A second silicon dioxide layer of 0.55 μm was deposited by PECVD as a mask layer as shown in figure 7.
The second silicon dioxide layer below the ion implantation position when the PWAll area is formed is protected through photoresist exposure, and the exposed part of the second silicon dioxide layer is etched back;
in one embodiment, the second silicon dioxide layer mask below the original p+ implant location is protected by exposure to a photoresist mask, with the remaining locations exposed, as shown in fig. 8. The exposed second silicon dioxide layer is etched by the P5000 dry etching equipment, the reserved area is the channel position of the MOS device, as shown in figure 9, the etching excess is about 50nm due to the certain over etching amount of the dry etching, the obtained channel length is about 0.5 mu m, the limitation of the channel length of the MOS device on the alignment precision and deviation of a photoetching machine can be broken through by the self-alignment process, and the MOS device with extremely small channel length can be prepared.
And removing the photoresist and performing N+ implantation to form an N+ region as described in the following steps.
In one embodiment of the present application, the specific process of "removing the photoresist and performing an n+ implant to form an n+ region" may be further described in conjunction with the following description.
Removing the photoresist by a wet photoresist removing process as follows; the structure is shown in fig. 10.
And as described in the following steps, performing ion implantation step by step for a plurality of times through a preset N+ layout to form an N+ region.
It should be noted that, the size reduction of the MOS device can be realized through the new n+ layout overlay, the n+ layout is shown in fig. 21, and the source contact position of the n+ layout is moved backward, so that the transverse size of the MOS device can be effectively reduced, and the obtained structure is shown in fig. 11.
The PWell region is cut into two unconnected parts by etching and the cut parts are filled with P-type material, as described in step S130.
In an embodiment of the present application, the specific process of "cutting the PWell area into two unconnected parts by etching and filling the cut parts by P-type material" in step S130 may be further described in conjunction with the following description.
Removing all materials on the top of the silicon carbide epitaxial wafer, and depositing a third silicon dioxide layer;
in one embodiment, the polysilicon layer is removed by a silicon etchant (35% nitric acid, 15% hydrofluoric acid, 15% acetic acid mixture), the upper silicon nitride layer is removed by hot phosphoric acid etching, a 50nm carbon film is sputtered by a CS-200z carbon film sputtering machine of the Aifa family model, the carbon film is annealed for 30min at 1600 ℃ in an Ar atmosphere by a c.actator 150-50 machine of Centrotherm, and the activated structure is obtained by removing the carbon film by a dry photoresist remover and cleaning by a wet method, as shown in FIG. 12.
A third silicon dioxide layer of 2 μm was deposited by PECVD as a mask for the PWell area as shown in fig. 13.
Protecting a preset area through photoresist exposure, and etching the exposed position to form two parts of a PWAll area which are completely disconnected;
in one embodiment, a 1.3um photoresist is applied to the third silicon dioxide layer, and the resulting structure is shown in fig. 14 after exposure and development.
The exposed PWAll area is etched through the device with the model number of SPTS Omega LPX synapse, the etching depth is about 1um, the etching angle is not lower than 87 degrees, the PWAll area originally connected by the two cells is completely disconnected, and the structure is shown in fig. 15.
And filling the groove etched in the PWAll region by growing a P-type doped wide bandgap semiconductor in situ as described in the following steps.
As an example, a P-doped wide bandgap semiconductor such as diamond is grown in situ by PECVD or LPCVD equipment, or an intrinsic P-type wide bandgap material such as beta-TeO is grown in situ by some physicochemical method such as MOCVD, PLD, ALD, MBE 2 ZnO, niO, etc., fills the etched trenches in the PWell region, as shown in fig. 16.
And as shown in the step S140, removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a process of forming a device.
It should be noted that, in the process of forming the device, the source contact portion of the MOS device formed in step S130 is further processed, and the source contact portion is added to the MOS device, so as to form a complete MOS device, as shown in fig. 23.
In an embodiment of the present application, the specific process of "removing all materials on top of the silicon carbide epitaxial wafer and sequentially depositing the dielectric isolation layer and the metal layer to form the MOS device" in step S140 may be further described in conjunction with the following description.
Removing all materials on the top of the silicon carbide epitaxial wafer as follows;
in one embodiment, photoresist is removed by a wet photoresist removal process, and excess P-type material over the photoresist is removed. The masked third silicon dioxide layer is then etched away by BOE etching, as shown in fig. 17.
Sequentially preparing a gate oxide layer, gate Poly metal, an ILD dielectric isolation layer, source contact metal, a passivation layer, a PI layer and a metal layer on the back;
in one embodiment, the ILD dielectric spacer is deposited by PECVD, wherein the ILD is composed of 0.2um USG+0.8um BPSG, and the deposited machines are AMAT P5000 as the application material machine, and the structure is shown in FIG. 18.
The ILD dielectric isolation layer above the PWAL region is etched by the front etching of AMAT P5000 as the model of the application material, the contact hole is exposed, and a CT plate (source contact opening) of the novel design layout is used for opening, wherein the CT plate structure is shown in fig. 22, an N+ region is not required to be exposed in the transverse direction, and even the opening of the CT plate above P+ is smaller than P+ in size, as shown in fig. 19.
In one embodiment of the present application, the specific process of "the metal layer preparation" may be further described in conjunction with the following description.
As described in the following steps, 100nm of Ti and 50nm of TiN were sputtered sequentially;
AlCu at 4000nm was sputtered as described in the following procedure, wherein the Cu content was 0.5%.
In a specific implementation, by using an AMAT end 5500 magnetron sputtering machine of the material, ti, tiN and AlCu are sputtered, ti 100nm+TiN 50nm+AlCu (0.5%) is 4000nm, wherein Ti is used as an ohmic contact metal and plays a role of an adhesion layer, tiN is used as a diffusion barrier layer to block Al infiltration, al is used as a connection metal to connect MOS cells, and a small amount of Cu is doped in Al to improve electromigration phenomenon and enhance reliability of a device, as shown in fig. 20.
In an embodiment of the application, there is also provided a MOS device fabricated by the method of any one of the above.
It should be noted that, as shown in fig. 24, when the MOS device is working in the forward direction, gate is added with a Gate voltage greater than the threshold voltage, the MOS device is in the on state, the S source is added with a forward voltage, the D drain is grounded and connected to zero potential, at this time, the emitter terminal and collector terminal and base terminal of the upper BJT device are equipotential, the emitter junction is reversed biased, the collector junction is reversed biased in the off state, and the BJT integrated above blocks the lateral crosstalk of the device during normal working.
When the MOS device works reversely, the Gate supplies zero potential or negative potential at the moment, so that the Gate of the MOS device is in a complete cut-off state, the S source electrode is supplied with negative voltage, the D drain electrode is grounded at zero potential, the BJT devices integrated at the left side and the right side are all in emission junction reverse bias, the collector junction reverse bias is in a cut-off state, and the body diode integrated in the MOS device is also in a reverse cut-off state. Therefore, the device structure can bear larger reverse voltage than a conventional device only comprising a parasitic body diode, and the device has higher reverse breakdown voltage.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The method and the device for preparing the MOS device based on the composite film self-alignment process provided by the application are described in detail, and specific examples are applied to illustrate the principle and the implementation mode of the application, and the description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The method for manufacturing the MOS device based on the composite film layer self-alignment process is characterized by comprising the following steps of:
sequentially depositing a shielding layer and a mask layer on the silicon carbide epitaxial wafer; the shielding layer is a silicon nitride layer, and the mask layer is a polysilicon layer and a first silicon dioxide layer which are sequentially stacked;
etching the polysilicon layer and the first silicon dioxide layer according to a preset etching shape, and performing ion implantation to form a PWAll region and an N+ region;
cutting the PWAll area into two disconnected parts by etching, and filling the cut parts by P-type materials;
and removing all materials on the top of the silicon carbide epitaxial wafer, and forming the MOS device through a device manufacturing process.
2. The method of claim 1, wherein the step of etching the polysilicon layer and the first silicon dioxide layer according to a predetermined etching shape and performing ion implantation to form a PWell region and an n+ region comprises:
spin-coating photoresist on the top of the first silicon dioxide layer according to a preset etching shape;
removing the first silicon dioxide layer and the polysilicon layer which are not in the photoresist protection by etching;
removing the photoresist and forming a PWAll region through ion implantation;
and removing the first silicon dioxide layer, depositing a second silicon dioxide layer, carrying out back etching on the second silicon dioxide layer, and carrying out ion implantation to form an N+ region.
3. The method of claim 2, wherein the spin coating photoresist on top of the first silicon dioxide layer according to a predetermined etch shape comprises:
firstly spin-coating hexamethyldisilane on the top of the first silicon dioxide layer, and then spin-coating photoresist;
removing the edge photoresist for 2mm, and performing soft baking at 110 ℃;
the exposure was performed through PW plate.
4. The method of claim 2, wherein the step of removing the photoresist and forming a PWell region by ion implantation comprises:
removing surface photoresist by a dry photoresist removing method, and removing photoresist residues by a wet photoresist removing method;
the PWell region is formed by 4 ion implants, where the energy of the first implant: 450keV, dose: 4E14, angle: 0 °, temperature: 500 ℃; energy of the second implant: 380keV, dose: 4E13, angle: 0 °, temperature: 500 ℃ C:: energy of the third implant: 260keV, dose: 3.6E12, angle: 0 °, temperature: 500 ℃; energy of the fourth implant: 160keV, dose: 1.5E12, angle: 0 °, temperature: 500 ℃.
5. The method of claim 2, wherein the removing the first silicon dioxide layer and depositing a second silicon dioxide layer, etching back the second silicon dioxide layer and ion implanting to form an n+ region, comprises:
removing the first silicon dioxide layer and depositing a second silicon dioxide layer according to a preset channel length;
protecting the second silicon dioxide layer below the ion implantation position when the PWAll region is formed through photoresist exposure, and carrying out back etching on the exposed part of the second silicon dioxide layer;
and removing the photoresist and performing N+ implantation to form an N+ region.
6. The method of claim 5, wherein the removing the photoresist and performing an n+ implant to form an n+ region comprises:
removing the photoresist by a wet photoresist removing process;
and performing ion implantation step by step for a plurality of times through a preset N+ layout to form an N+ region.
7. The method of claim 1, wherein the step of cutting the PWell area into two unconnected pieces by etching and filling the cut pieces with P-type material comprises:
removing all materials on the top of the silicon carbide epitaxial wafer, and depositing a third silicon dioxide layer;
protecting a preset area through photoresist exposure, and etching the exposed position to enable the PWAll area to form two parts which are completely disconnected;
and filling the groove etched in the PWAll region by growing a P-type doped wide bandgap semiconductor in situ.
8. The method of claim 1, wherein the step of removing all material on top of the silicon carbide epitaxial wafer and forming a MOS device by a process of forming a device comprises:
removing all materials on the top of the silicon carbide epitaxial wafer;
and sequentially preparing a gate oxide layer, gate Poly metal, an ILD dielectric isolation layer, source contact metal, a passivation layer, a PI layer and a metal layer on the back.
9. The method of claim 8, wherein the preparing of the metal layer comprises:
sequentially sputtering 100nm Ti and 50nm TiN;
AlCu at 4000nm was sputtered, with a Cu content of 0.5%.
10. A MOS device, characterized in that it is manufactured by the method of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311337100.9A CN117080078A (en) | 2023-10-17 | 2023-10-17 | Method for preparing MOS device based on composite film layer self-alignment process and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311337100.9A CN117080078A (en) | 2023-10-17 | 2023-10-17 | Method for preparing MOS device based on composite film layer self-alignment process and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117080078A true CN117080078A (en) | 2023-11-17 |
Family
ID=88713787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311337100.9A Pending CN117080078A (en) | 2023-10-17 | 2023-10-17 | Method for preparing MOS device based on composite film layer self-alignment process and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117080078A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100272175B1 (en) * | 1998-07-20 | 2000-11-15 | 김덕중 | Power device and method for manufacturing the same |
| CN102194699A (en) * | 2010-03-11 | 2011-09-21 | 万国半导体股份有限公司 | Shielded gate trench MOS with improved source pickup layout |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
| CN104810288A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Manufacturing method of double-diffusion metal-oxide-semiconductor (DMOS) device |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN105448722A (en) * | 2014-08-06 | 2016-03-30 | 北大方正集团有限公司 | Method for manufacturing super-junction semiconductor field effect transistor, and semiconductor device |
| CN110957227A (en) * | 2019-12-27 | 2020-04-03 | 深圳市威兆半导体有限公司 | MOSFET device and manufacturing method thereof |
| CN111987165A (en) * | 2020-08-25 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
| CN112071913A (en) * | 2020-09-08 | 2020-12-11 | 深圳基本半导体有限公司 | Silicon carbide planar gate MOSFET cell structure and manufacturing method |
| CN113270482A (en) * | 2021-05-20 | 2021-08-17 | 厦门市三安集成电路有限公司 | Preparation method of MOSFET device |
-
2023
- 2023-10-17 CN CN202311337100.9A patent/CN117080078A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100272175B1 (en) * | 1998-07-20 | 2000-11-15 | 김덕중 | Power device and method for manufacturing the same |
| CN102194699A (en) * | 2010-03-11 | 2011-09-21 | 万国半导体股份有限公司 | Shielded gate trench MOS with improved source pickup layout |
| CN103579003A (en) * | 2012-08-09 | 2014-02-12 | 北大方正集团有限公司 | Method for manufacturing super joint MOSFET |
| CN104810288A (en) * | 2014-01-26 | 2015-07-29 | 北大方正集团有限公司 | Manufacturing method of double-diffusion metal-oxide-semiconductor (DMOS) device |
| CN105448722A (en) * | 2014-08-06 | 2016-03-30 | 北大方正集团有限公司 | Method for manufacturing super-junction semiconductor field effect transistor, and semiconductor device |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN110957227A (en) * | 2019-12-27 | 2020-04-03 | 深圳市威兆半导体有限公司 | MOSFET device and manufacturing method thereof |
| CN111987165A (en) * | 2020-08-25 | 2020-11-24 | 杰华特微电子（杭州）有限公司 | Method for manufacturing lateral double-diffused transistor |
| CN112071913A (en) * | 2020-09-08 | 2020-12-11 | 深圳基本半导体有限公司 | Silicon carbide planar gate MOSFET cell structure and manufacturing method |
| CN113270482A (en) * | 2021-05-20 | 2021-08-17 | 厦门市三安集成电路有限公司 | Preparation method of MOSFET device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6020246A (en) | Forming a self-aligned epitaxial base bipolar transistor | |
| US4824796A (en) | Process for manufacturing semiconductor BICMOS device | |
| US6110787A (en) | Method for fabricating a MOS device | |
| EP0139165B1 (en) | Method of making a trench isolated integrated circuit device | |
| US8222114B2 (en) | Manufacturing approach for collector and a buried layer of bipolar transistor | |
| JPH0362024B2 (en) | ||
| US7785974B2 (en) | Methods of employing a thin oxide mask for high dose implants | |
| JP2010500765A (en) | JFET with built-in back gate in either SOI or bulk silicon | |
| JPS6324616A (en) | Manufacture of semiconductor device and the semiconductor device manufactured | |
| WO1991003841A1 (en) | Element, method of fabricating the same, semiconductor element and method of fabricating the same | |
| TWI480951B (en) | Wide trench termination structure for semiconductor device | |
| TWI564942B (en) | Novel method for isolation with buried n+ layer | |
| US5344786A (en) | Method of fabricating self-aligned heterojunction bipolar transistors | |
| JPH0622240B2 (en) | Method for manufacturing bipolar transistor device | |
| CN114899101A (en) | Semiconductor device and method for manufacturing the same | |
| KR100597768B1 (en) | Method for fabricating gate spacer of semiconductor device | |
| KR100606935B1 (en) | method for fabrication Semiconductor device | |
| US7291536B1 (en) | Fabricating a self-aligned bipolar transistor having increased manufacturability | |
| JP2597631B2 (en) | Semiconductor device and method of manufacturing the same | |
| US6746928B1 (en) | Method for opening a semiconductor region for fabricating an HBT | |
| CN117080078A (en) | Method for preparing MOS device based on composite film layer self-alignment process and device | |
| CN109300982A (en) | High-frequency triode and preparation method thereof | |
| TW200401449A (en) | Method for improved alignment tolerance in a bipolar transistor and related structure | |
| EP1298719A2 (en) | Method for manufacturing and structure of semiconductor device with shallow trench collector contact region | |
| CN210040207U (en) | Structure of middle-high voltage trench-forming power metal oxide semiconductor field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |