CN105244369A - Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same - Google Patents
Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same Download PDFInfo
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- CN105244369A CN105244369A CN201510589211.8A CN201510589211A CN105244369A CN 105244369 A CN105244369 A CN 105244369A CN 201510589211 A CN201510589211 A CN 201510589211A CN 105244369 A CN105244369 A CN 105244369A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 18
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- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
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- 238000009792 diffusion process Methods 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention provides a super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and a device formed by using the same. According to the preparation method, a drift region is formed on the surface of a semiconductor substrate through epitaxy; the drift region is etched under the masking of a mask film until the bottom layer of the semiconductor substrate is exposed, so that the drift region can be separated out; and an epitaxy groove filling technology is utilized to insert column regions of a second conductivity type into an interval space of the drift region, so that a P/N column region interlaced super junction drift region can be formed. According to the preparation method of the invention, a region in an N-type silicon epitaxial layer, where a P-type drift region is required to be formed, is etched, so that grooves are formed; a P type impurity silicon material is grown in the grooves through epitaxy until the grooves are filled, so that P column regions can be formed. The method can replace a technique process in the prior art. According to the technologic process in the prior art, N-type epitaxial layers and injection P type ions are alternately arranged repeatedly, and P type doping introduction is adopted. Thus, with the preparation method of the invention adopted, the process for preparing a super junction VDMOSFET can be simplified, and the production cost of the super junction MOSFET can be reduced.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of hyperconjugation VDMOS FET (vertical bilateral diffusion field-effect tranisistor) preparation method and the device that utilizes the method to be formed.
Background technology
In applied power electronics, in order to reduce power consumption, require that semiconductor device can bear higher voltage in the off state, there is lower conducting resistance in the on-state, conventional power MOSFET (mos field effect transistor), usual employing VDMOSFET (vertical double-diffused MOS FET) structure, in order to satisfied height is withstand voltage, need reduce drift region concentration or increase drift region thickness, but conducting resistance also can increase thereupon, its conducting resistance and puncture voltage are the relation of 2.5 powers.The drift region that super node MOSFET adopts pn post plot structure alternately to be formed replaces the N-drift region in VDMOSFET, solves the contradiction between conducting resistance and puncture voltage, makes its conducting resistance and puncture voltage hold the relation of 1.32 powers.Therefore, compared with the power MOSFET of routine, super node MOSFET has very large advantage in puncture voltage and conducting resistance.
But for the device of this structure of super node MOSFET, wherein P post region lateral dimension in superjunction region is very little, but longitudinal size relatively very dark (generally at about 50um), technique is difficult to make.By repeatedly mutually to be replaced by growth N-type epitaxy layer and implanting p-type ion in N-type substrate and P type adulterates and injects during the making of the P type drift region of current super node MOSFET.Namely first in N-type epitaxy layer, photoetching P district, implanting p-type ion, then removes photoresist, and regrow N-type epitaxy layer, the step of photoetching P district and implanting p-type ion, until P district longitudinal size reaches requirement, finally carries out the making that the doping of P type can complete P post region drift region again.This method needs repeatedly epitaxial growth and ion implantation, so technique is loaded down with trivial details, production cost is higher.
Summary of the invention
The present invention is intended at least solve the technical problem existed in prior art, the device especially innovatively proposing a kind of hyperconjugation VDMOS FET preparation method and utilize the method to be formed.
In order to realize above-mentioned purpose of the present invention, according to a first aspect of the invention, the invention provides a kind of hyperconjugation VDMOS FET preparation method, comprise the following steps:
S1, provides the Semiconductor substrate of the first conduction type, is formed and the drift region of described Semiconductor substrate with doping type in described semiconductor substrate surface extension;
S2, photoetching, pass through deep etching, drift region is etched until expose described semiconductor substrate layer when mask is sheltered, thus drift region is separated, utilize extension to fill out post district that groove technique inserts the second conduction type in the clearance space of described drift region, form the superjunction drift region that P/N post district is interlaced, described first conductivity type is the one in N-type or P type, and the second conduction type is the another kind in N-type or P type;
S3, forms grid oxide layer and grid material on surface, described superjunction drift region, and forms grid structure by photoetching process;
S4, adopt self-registered technology between two grid structures, carry out the ion implantation of the second conduction type, and carry out high annealing described second conductive type ion is pushed ahead below described grid structure and the first conduction type depletion layer, form the well region of the second conduction type;
S5, forms the source region of the first conduction type be connected with described first conduction type depletion layer in the well region of described second conduction type by ion implantation technology and annealing process;
S6, the body structure surface formed in step S5 forms dielectric layer;
S7, photoetching, etch media layer, exposes the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type, forms electrode and prepares region;
S8, the electrode formed in step S7 is prepared in region and dielectric layer surface deposit metal electrodes, described metal electrode is connected simultaneously, formation source electrode with the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type;
S9, in N-type silicon substrate, growing metal layer forms the drain electrode of hyperconjugation VDMOS FET.
The super-junction structure manufacturing process that the present invention combines with multistep extension and multistep ion implantation compares, and the method adopting this deep etching and extension to fill out groove to combine, directly can control the doping content of filler, is more convenient to the charge balance keeping N/P post district.
In the preferred embodiment of the present invention, described first conductivity type is N-type, and the second conduction type is P type.
With the first conduction type for N-type is described, the present invention goes out groove by needing the region etch forming P type drift region in N-type silicon epitaxy layer, then in the trench the silicon materials of epitaxial p type impurity until groove is filled formation P post region, replace in prior art by N-type epitaxy layer and implanting p-type ion repeatedly mutually alternately and P type adulterate and drive in the technical process of the P post region formed, thus simplify the technique preparing hyperconjugation VDMOS FET, reduce the production cost of super node MOSFET.
In the preferred embodiment of the present invention, the technique forming superjunction drift region in step S2 comprises following 2 steps:
S21, carries out deep etching by mask layer to epitaxial loayer, until penetrate N-epitaxial loayer, and etching depth 40-60um, width 6.0-8.0um;
S22, carries out extension and fills out groove, and the doping content forming the second conductivity type columns district is 3-5e10
15cm
-3.
Thus one-time process just forms enough dark groove, simplifies preparation technology's flow process,
In another kind of preferred implementation of the present invention, adopt self-registered technology in described grid structure, ion implantation comprises following 2 steps in step s 4 which:
S41, carries out boron ion implantation, and implantation dosage is 3-5e10
15cm
-2, Implantation Energy is 100-200Kev;
S42, carries out boron ion implantation, and implantation dosage is 0.5-2e10
15cm
-2, Implantation Energy is 150-200Kev.
In another preferred implementation of the present invention, the angle that step S41 intermediate ion injects is 5 degree; The angle that step S42 intermediate ion injects is 0 degree.
In order to realize above-mentioned purpose of the present invention, according to a second aspect of the invention, the invention provides a kind of hyperconjugation VDMOS FET utilizing method of the present invention to prepare, it comprises following structure:
The Semiconductor substrate of the first conduction type;
The interlaced superjunction drift region in first conductivity type columns district and the second conductivity type columns district, described superjunction drift region is positioned at described semiconductor substrate surface;
The well region of the second conduction type, is formed at surface, described superjunction drift region and covers and extend described second conductivity type columns district;
The source region of the first conduction type, described source region is formed in the well region of described second conduction type;
The contact zone of the second conduction type, described contact zone is formed between the source region of described second conduction type well region and described first conduction type type;
Grid structure, be formed at surface, described superjunction drift region and cover described first conductivity type columns district, and cover the part in the well region of second conduction type adjacent with described first conductivity type columns district and the source region of the first conduction type, described grid structure is coated with dielectric layer;
Electrode prepares region, runs through the first conduction type source region, the second conduction type contact zone;
Source metal electrode, described source metal electrode is covered in described electrode and prepares region and described dielectric layer surface, connects described first conduction type source region, the second conduction type contact zone and the second conduction type well region simultaneously.
The present invention goes out groove by needing the region etch forming drift region in silicon epitaxy layer, and then epitaxial silicon material forms post district until groove is filled in the trench, thus simplifies the technique preparing hyperconjugation VDMOS FET, reduces the production cost of super node MOSFET.
In the preferred embodiment of the present invention, described grid structure comprises: be formed at the grid oxide layer on surface, described drift region and be formed at the polysilicon layer on described grid oxide layer surface.
In another kind of preferred implementation of the present invention, described first conductive type semiconductor substrate and described superjunction drift region material are silicon.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is drift region, the source schematic diagram going out N-type in a kind of preferred embodiment of the present invention at N+ type Semiconductor substrate Epitaxial growth;
Fig. 2 is the schematic diagram going out P post region in a kind of preferred embodiment of the present invention at N-epitaxial loayer deep etching;
Fig. 3 is the schematic diagram growing grid oxic horizon, polysilicon layer, mask layer in a kind of preferred embodiment of the present invention on superjunction epitaxial layer region;
Fig. 4 is the schematic diagram etching mask window and ion implantation formation P well region in a kind of preferred embodiment of the present invention in mask layer and polysilicon layer;
Fig. 5 is that a kind of preferred embodiment intermediate ion of the present invention injects the schematic diagram forming N well region;
Fig. 6 grows insulating medium layer in a kind of preferred embodiment of the present invention on the polysilicon layer, and photoetching, etching formation contact hole and growing metal layer form the schematic diagram of source drain.
Reference numeral:
101 Semiconductor substrate; 102 epitaxial loayers; 103 first time mask layer; 104P post district; 105N post district;
106 grid oxic horizons; 107 grids; 108 second time mask layers; 109P well region;
Diffusion region, 110N+ source; 111 dielectric layers; 112 source electrodes; 113 drain electrodes.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In describing the invention, it will be appreciated that, term " longitudinal direction ", " transverse direction ", " on ", D score, "front", "rear", "left", "right", " vertically ", " level ", " top ", " end " " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.
In describing the invention, unless otherwise prescribed and limit, it should be noted that, term " installation ", " being connected ", " connection " should be interpreted broadly, such as, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be directly be connected, also indirectly can be connected by intermediary, for the ordinary skill in the art, the concrete meaning of above-mentioned term can be understood as the case may be.
The invention provides a kind of hyperconjugation VDMOS FET, as shown in Figure 6, be only the size giving each region of signal in figure, concrete size can design according to the requirement of device parameters.As can be seen from Fig. 6, this hyperconjugation VDMOS FET comprises the semi-conducting material (Semiconductor substrate) of the first conduction type, this semi-conducting material can be any semi-conducting material of preparation MOSFET, can be specifically but be not limited to silicon, germanium, SiGe, carborundum, GaAs.
In the present embodiment, the first conductivity type is N-type, and the second conduction type is P type.Or the first conductivity type is P type, the second conduction type is N-type.
As shown in Figure 6, have superjunction drift region at semiconductor substrate surface, this superjunction drift region is by the first conductivity type columns district and the second conductivity type columns district is interlaced is formed.The well region of the second conduction type is formed at surface, superjunction drift region and covers and extend the second conductivity type columns district.The source region of the first conduction type is formed in the well region of the second conduction type.The contact zone of the second conduction type between the source region being formed at the second conduction type well region and the first conduction type type.And grid structure, this grid structure is formed at surface, superjunction drift region and covers described first conductivity type columns district, and be covered in the part in the well region of the second adjacent conduction type of the first conductivity type columns district and the source region of the first conduction type, grid structure is coated with dielectric layer, and dielectric layer can be but be not limited to adopt silicon dioxide or other the high-κ medium of thermal oxide growth.This hyperconjugation VDMOS FET also comprises and runs through the first conduction type source region, the second conduction type contact zone and be formed with electrode and prepare region, source metal electrode is covered in electrode and prepares region and dielectric layer surface, connects the first conduction type source region, the second conduction type contact zone and the second conduction type well region simultaneously.
In order to realize hyperconjugation VDMOS FET structure of the present invention, present invention also offers a kind of hyperconjugation VDMOS FET preparation method, comprising the following steps:
S1, provides the Semiconductor substrate of the first conduction type, is formed and the epitaxial loayer (drift region) of Semiconductor substrate with doping type in this semiconductor substrate surface extension; Such as at N+ substrate epitaxial N type semiconductor material, under this substrate, form N-type drift region.
S2, photoetching, corresponding mask layer is formed in N-type drift region, pass through deep etching, drift region is etched when mask is sheltered, groove penetrates described N-epi region until exposing semiconductor substrate layer, thus drift region is separated, utilize extension to fill out post district that groove technique inserts the second conduction type in the clearance space of described drift region, form the superjunction drift region that P/N post district is interlaced, extension infiltrates the silicon materials of p type impurity until groove is filled in the groove, recover the drift region, P Xing Zhu district be etched away, described first conductivity type is the one in N-type or P type, second conduction type is the another kind in N-type or P type.
S3, form grid oxide layer and grid material on surface, superjunction drift region, mask layer, etches corresponding mask window; And form grid structure by photoetching process;
S4, adopt self-registered technology between two grid structures, carry out the ion implantation of the second conduction type, and carry out high annealing described second conductive type ion is pushed ahead below described grid structure and the first conduction type depletion layer, form the well region of the second conduction type, in the present embodiment, the concept of depletion layer and the position position that is concept general in this area and usually exists.
S5, forms the source region of the first conduction type be connected with described first conduction type depletion layer in the well region of described second conduction type by ion implantation technology and annealing process, remove mask layer; ;
S6, the body structure surface formed in step S5 forms dielectric layer;
S7, photoetching, etch media layer, forms contact hole, exposes the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type, forms electrode and prepares region;
S8, the electrode formed in step S7 is prepared in region and dielectric layer surface deposit metal electrodes, described metal electrode is connected simultaneously, formation source electrode with the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type.
S9, in N-type silicon substrate, growing metal layer forms the drain electrode of hyperconjugation VDMOS FET.
In the present embodiment, concrete doping type, the selection of dopant, and doping process all can select existing technology, therefore not to repeat here.With the first conduction type for N-type is described, the present invention goes out groove by needing the region etch forming P type drift region in N-type silicon epitaxy layer, then in the trench the silicon materials of epitaxial p type impurity until groove is filled formation P post region, replace in prior art by N-type epitaxy layer and implanting p-type ion repeatedly mutually alternately and P type adulterate and drive in the technical process of the P post region formed, thus simplify the technique preparing hyperconjugation VDMOS FET, reduce the production cost of super node MOSFET.
In the preferred embodiment of the present invention, the technique forming superjunction drift region in step S2 comprises following 2 steps:
S21, carries out deep etching by mask layer to epitaxial loayer, until penetrate N-epitaxial loayer, carries out deep etching, etching depth 40.0-60.0um, width 6.0-8.0um, and the etching depth comparatively figure of merit is 54.6um, and the width comparatively figure of merit is 7.4um;
S22, carries out extension and fills out groove, and the doping content forming the second conductivity type columns district is 3-5e10
15cm
-3, be preferably 3.6e10
15cm
-3.
Thus one-time process just forms enough dark groove, simplifies preparation technology's flow process.
In the present embodiment, step S4 intermediate ion injects and comprises following 2 steps:
S41, carries out boron ion implantation, and implantation dosage is 3-5e10
15cm
-2, Implantation Energy is 100-200Kev;
S42, carries out boron ion implantation, and implantation dosage is 0.5-2e10
15cm
-2, Implantation Energy is 150-250Kev.
In another preferred implementation of the present invention, the angle that step S41 intermediate ion injects is 5 degree; The angle that step S42 intermediate ion injects is 0 degree.
In the preferred embodiment of the present invention, grid structure comprises the grid oxide layer being formed at surface, drift region and the polysilicon layer being formed at grid oxide layer surface.First conductive type semiconductor substrate and superjunction drift region material are silicon.
In preferably implementing at one of the present invention, the specific implementation method preparing hyperconjugation VDMOS FET is as follows:
As shown in Figure 1, first on N+ type silicon substrate 101, grow N-type epitaxial loayer 102, this N-type silicon epitaxy layer 102 is monocrystalline silicon, and the doping content of this N-type silicon epitaxy layer 102 is 3.3 × 10
15cm
-3, thickness is 56um.Then on N-type silicon epitaxy layer 102, grown silicon nitride is as sacrificial oxide layer, and Fig. 1 is not shown, and then removes sacrificial oxide layer, to reach the object on clean N-type epitaxy layer 102 surface.
Form the detailed process in P Xing Zhu district as follows: at epitaxial loayer 102 superficial growth silicon nitride as first time mask layer 103, etch corresponding etching window, as shown in Figure 2.Carry out deep etching by mask layer to epitaxial loayer, until penetrate N-epitaxial loayer, then extension infiltrates doping content is in the trench 3.6 × 10
15cm
-3the silicon materials of p type impurity until groove is filled, form P post region 104 and N post district 105, adopt the phosphoric acid corrosion that concentration is 86% (percentage by weight), temperature is 165 DEG C to fall silicon nitride layer in order to remove mask layer.
Then, N/P post district 104,105 after surface is cleaned adopts the technique growth grid oxic horizon 106 of dry oxidation, this grid oxic horizon 104 thickness is 0.2um, then growing polycrystalline silicon 107 on grid oxic horizon 106, its thickness is 0.4um, then in polysilicon surface grown silicon nitride as second time mask layer 108, its thickness is 0.1um, as shown in Figure 3.Then with need to form the polysilicon layer 107 corresponding to P well region and the relevant position in mask layer 108 etches window, and not etching grid oxide layer 108, as shown in Figure 4.
In the present embodiment, P well region 109 ion implantation detailed process is as follows: adopt self-registered technology to carry out boron ion implantation in described grid structure 103 layers, implantation dosage is 4e10
15cm
-3, Implantation Energy is 150Kev, and the angle of ion implantation is 5 degree.Carry out second time boron ion implantation, implantation dosage is 1e10
15cm
-3, implantation dosage is 200Kev, and the angle of ion implantation is 0 degree.After completing above-mentioned ion implantation, make boron ion be advanced into certain depth below grid structure finally by high annealing, form P trap 109 as shown in Figure 4.
Diffusion region 110, N+ source ion implantation detailed process is as follows: utilize the difference that boron phosphorus spreads, carry out phosphonium ion injection, and implantation dosage is 5e10
17cm
-3, Implantation Energy is 100KeV, and ion implantation angle is 0 degree, forms diffusion region, N+ source, as shown in Figure 5.
Finally, the specific practice of the source electrode forming hyperconjugation VDMOS FET and the drain electrode that forms hyperconjugation VDMOS FET in step 9 is: as shown in Figure 5, first on polysilicon layer 108 and in described window, grow insulating medium layer 111, polysilicon layer 107 is wrapped the insulating medium layer 111 in photoetching, etching window and the P post region 104 exposed between two N-type silicon source regions 110 and two N-type silicon source regions 110 forms contact hole; Then on insulating medium layer 111 and contact aerial growing metal layer formed source electrode 112, this metal level is aluminium (98.5%) silicon (1%) copper (0.5%) alloy (percentage by weight); And on N+ type substrate 101 growing metal layer, formed drain electrode 113, as shown in Figure 6.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention, those having ordinary skill in the art will appreciate that: can carry out multiple change, amendment, replacement and modification to these embodiments when not departing from principle of the present invention and aim, scope of the present invention is by claim and equivalents thereof.
Claims (8)
1. a hyperconjugation VDMOS FET preparation method, is characterized in that, comprises the following steps:
S1, provides the Semiconductor substrate of the first conduction type, is formed and the drift region of described Semiconductor substrate with doping type in described semiconductor substrate surface extension;
S2, photoetching, pass through deep etching, drift region is etched until expose described semiconductor substrate layer when mask is sheltered, thus drift region is separated, utilize extension to fill out post district that groove technique inserts the second conduction type in the clearance space of described drift region, form the superjunction drift region that P/N post district is interlaced, described first conductivity type is the one in N-type or P type, and the second conduction type is the another kind in N-type or P type;
S3, forms grid oxide layer and grid material on surface, described superjunction drift region, and forms grid structure by photoetching process;
S4, adopt self-registered technology between two grid structures, carry out the ion implantation of the second conduction type, and carry out high annealing described second conductive type ion is pushed ahead below described grid structure and the first conduction type depletion layer, form the well region of the second conduction type;
S5, forms the source region of the first conduction type be connected with described first conduction type depletion layer in the well region of described second conduction type by ion implantation technology and annealing process;
S6, the body structure surface formed in step S5 forms dielectric layer;
S7, photoetching, etch media layer, exposes the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type, forms electrode and prepares region;
S8, the electrode formed in step S7 is prepared in region and dielectric layer surface deposit metal electrodes, described metal electrode is connected simultaneously, formation source electrode with the well region of the source region of described first conduction type, the contact zone of the second conduction type and the second conduction type;
S9, in N-type silicon substrate, growing metal layer forms the drain electrode of hyperconjugation VDMOS FET.
2. hyperconjugation VDMOS FET preparation method according to claim 1, is characterized in that, described first conductivity type is N-type, and the second conduction type is P type.
3. hyperconjugation VDMOS FET preparation method according to claim 1 and 2, is characterized in that, the technique forming superjunction drift region in step S2 comprises following 2 steps:
S21, carries out deep etching, etching depth 40.0-60.0um, width 6.0-8.0um;
S22, carries out extension and fills out groove, and the doping content forming the second conductivity type columns district is 3-5e10
15cm
-3.
4. hyperconjugation VDMOS FET preparation method according to claim 1 and 2, is characterized in that, step S4 intermediate ion injects and comprises following 2 steps:
S41, carries out boron ion implantation, and implantation dosage is 3-5e10
15cm
-2, Implantation Energy is 100-200Kev;
S42, carries out boron ion implantation, and implantation dosage is 0.5-2e10
15cm
-2, Implantation Energy is 150-250Kev.
5. hyperconjugation VDMOS FET preparation method according to claim 4, is characterized in that, the angle that step S41 intermediate ion injects is 0-5 degree; The angle that step S42 intermediate ion injects is 0-5 degree.
6. the hyperconjugation VDMOS FET utilizing the hyperconjugation VDMOS FET preparation method described in claim 1 to prepare, is characterized in that, comprise following structure:
The Semiconductor substrate of the first conduction type;
The interlaced superjunction drift region in first conductivity type columns district and the second conductivity type columns district, described superjunction drift region is positioned at described semiconductor substrate surface;
The well region of the second conduction type, is formed at surface, described superjunction drift region and covers and extend described second conductivity type columns district;
The source region of the first conduction type, described source region is formed in the well region of described second conduction type;
The contact zone of the second conduction type, described contact zone is formed between the source region of described second conduction type well region and described first conduction type type;
Grid structure, be formed at surface, described superjunction drift region and cover described first conductivity type columns district, and cover the part in the well region of second conduction type adjacent with described first conductivity type columns district and the source region of the first conduction type, described grid structure is coated with dielectric layer;
Electrode prepares region, runs through the first conduction type source region, the second conduction type contact zone;
Source metal electrode, described source metal electrode is covered in described electrode and prepares region and described dielectric layer surface, connects described first conduction type source region, the second conduction type contact zone and the second conduction type well region simultaneously.
7. hyperconjugation VDMOS FET according to claim 6, is characterized in that: described grid structure comprises: be formed at the grid oxide layer on surface, described drift region and be formed at the polysilicon layer on described grid oxide layer surface.
8. hyperconjugation VDMOS FET according to claim 6, is characterized in that: described first conductive type semiconductor substrate and described superjunction drift region material are silicon.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107346738A (en) * | 2016-05-04 | 2017-11-14 | 北大方正集团有限公司 | The preparation method of super junction power device |
| CN108831927A (en) * | 2018-06-12 | 2018-11-16 | 北京世港晟华科技有限公司 | Super-junction metal oxide semiconductor field effect transistor and its manufacturing method |
| CN109037333A (en) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | Silicone carbide metal oxide semiconductor field effect transistor and its manufacturing method |
| CN109509792A (en) * | 2018-10-12 | 2019-03-22 | 龙腾半导体有限公司 | Optimize the super node MOSFET domain structure and manufacturing method of EMI |
| CN110176401A (en) * | 2019-06-13 | 2019-08-27 | 深圳市锐骏半导体股份有限公司 | A method of reducing VDMOS production cost |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
| WO2024051282A1 (en) * | 2022-09-05 | 2024-03-14 | 苏州华太电子技术股份有限公司 | Igbt device manufacturing method and igbt device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969069A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| US20130175607A1 (en) * | 2012-01-05 | 2013-07-11 | Tsung-Hsiung LEE | Semiconductor device and fabricating method thereof |
| CN103227113A (en) * | 2012-01-25 | 2013-07-31 | 瑞萨电子株式会社 | Method of manufacturing vertical planar power MOSFET and method of manufacturing trench-gate power MOSFET |
| CN103681779A (en) * | 2012-09-11 | 2014-03-26 | 无锡华润上华半导体有限公司 | Field effect transistor structure and manufacturing method thereof |
-
2015
- 2015-09-16 CN CN201510589211.8A patent/CN105244369A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969069A (en) * | 2010-08-06 | 2011-02-09 | 浙江大学 | Edge terminal structure of high-voltage power semiconductor device |
| US20130175607A1 (en) * | 2012-01-05 | 2013-07-11 | Tsung-Hsiung LEE | Semiconductor device and fabricating method thereof |
| CN103227113A (en) * | 2012-01-25 | 2013-07-31 | 瑞萨电子株式会社 | Method of manufacturing vertical planar power MOSFET and method of manufacturing trench-gate power MOSFET |
| CN103681779A (en) * | 2012-09-11 | 2014-03-26 | 无锡华润上华半导体有限公司 | Field effect transistor structure and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 王彩琳编著: "《电力半导体新器件及其制造技术》", 30 June 2015, 机械工业出版社出版社 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107346738A (en) * | 2016-05-04 | 2017-11-14 | 北大方正集团有限公司 | The preparation method of super junction power device |
| CN107346738B (en) * | 2016-05-04 | 2020-03-06 | 北大方正集团有限公司 | Manufacturing method of super junction power device |
| CN109037333A (en) * | 2017-06-12 | 2018-12-18 | 中兴通讯股份有限公司 | Silicone carbide metal oxide semiconductor field effect transistor and its manufacturing method |
| CN109037333B (en) * | 2017-06-12 | 2021-04-30 | 中兴通讯股份有限公司 | Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN108831927A (en) * | 2018-06-12 | 2018-11-16 | 北京世港晟华科技有限公司 | Super-junction metal oxide semiconductor field effect transistor and its manufacturing method |
| CN109509792A (en) * | 2018-10-12 | 2019-03-22 | 龙腾半导体有限公司 | Optimize the super node MOSFET domain structure and manufacturing method of EMI |
| CN110176401A (en) * | 2019-06-13 | 2019-08-27 | 深圳市锐骏半导体股份有限公司 | A method of reducing VDMOS production cost |
| CN110176401B (en) * | 2019-06-13 | 2022-08-30 | 深圳市锐骏半导体股份有限公司 | Method for reducing production cost of VDMOS |
| WO2024051282A1 (en) * | 2022-09-05 | 2024-03-14 | 苏州华太电子技术股份有限公司 | Igbt device manufacturing method and igbt device |
| CN117080078A (en) * | 2023-10-17 | 2023-11-17 | 深圳基本半导体有限公司 | Method for preparing MOS device based on composite film layer self-alignment process and device |
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