WO2024051282A1

WO2024051282A1 - Igbt device manufacturing method and igbt device

Info

Publication number: WO2024051282A1
Application number: PCT/CN2023/102560
Authority: WO
Inventors: 刘倩; 祁金伟
Original assignee: 苏州华太电子技术股份有限公司
Priority date: 2022-09-05
Filing date: 2023-06-27
Publication date: 2024-03-14
Also published as: CN116525435B; CN116525435A

Abstract

Embodiments of the present application provide an IGBT device manufacturing method and an IGBT device. The manufacturing method comprises: forming an epitaxial layer of a second doping type on a substrate; trenching the upper surface of the epitaxial layer downwards to form pillar region trenches; filling the pillar region trenches with a material of a first doping type; trenching to form first gate trenches, wherein the first gate trenches extend downwards from the upper surface of the material of the first doping type, and the regions of the material of the first doping type which are not trenched serve as pillar regions; forming a first gate oxide layer in the first gate trenches; forming first gates on the first gate oxide layer; and forming a well region of the first doping type in the upper part of the epitaxial layer, wherein the bottom of the well region is higher than the tops of the pillar regions, the part of the epitaxial layer located below the well region serves as a drift region, and the well region and the pillar regions are separated by the drift region and the first gate oxide layer. The embodiments of the present application solve the technical problem that conventional IGBT device manufacturing methods have complex processes and high manufacturing costs.

Description

Preparation method of IGBT device and IGBT device

Technical field

The present application relates to the field of semiconductor technology, specifically, to a preparation method of an IGBT device and an IGBT device.

Background technique

The structure of the traditional SJ-IGBT device is shown in Figure 1. 1 is the P-collector region, 2 is the N-drift region, 3 is the P-type super junction region, 4 is the second epitaxy, and 5 is the gate oxide layer. , 6 is the gate, 7 is the Pwell, 8 is the N+ emitter, 9 is the dielectric layer, 10 is the emitter metal, 11 is the P+ collector, and 12 is the collector metal.

In the preparation steps of the super junction structure in the traditional preparation method of IGBT devices, there are two steps of growing the epitaxial layer. The first doping type pillar region is formed in the first grown epitaxial layer; since the first generated The upper surface of the epitaxial layer is dug downward to form a column region trench; then, the column region trench is filled with a first doping type material to form a column region. After the pillar region is formed, a second epitaxial layer needs to be grown, and then a trench is dug downward from the upper surface of the second epitaxial layer to form a gate trench. The depth of the gate trench is larger than that of the second epitaxial layer. The depth is shallow. That is, the gate trench does not penetrate the bottom of the second epitaxial layer. After that, a gate oxide layer is formed in the gate trench, and a gate electrode is formed on the gate oxide layer. Impurities of the first doping type are injected or diffused into the upper surface of the second epitaxial layer to form a well region of the first doping type, and the lower surface of the well region is higher than the gate trench. In this way, the second epitaxial layer realizes that the pillar region and the well region are not in direct contact, but are separated by the second epitaxial layer. The existence of the second epitaxial layer makes the preparation method of the super junction structure complicated and the preparation cost high.

The above information disclosed in the Background is only for enhancement of understanding of the context of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Contents of the invention

Embodiments of the present application provide a method for preparing an IGBT device and an IGBT device, so as to solve the technical problem of the traditional IGBT device preparation method having complicated processes and high manufacturing costs.

The embodiment of the present application provides a method for preparing an IGBT device, including the following steps:

A method for preparing an IGBT device, including the following steps:

forming an epitaxial layer of a second doping type on the first doping type substrate;

Digging downward from the upper surface of the epitaxial layer to form trenches in the pillar area;

The trench in the pillar region is filled with the material of the first doping type;

Digging to form a first gate trench extending downward from the upper surface of the first doped type material, wherein the first doped type material that has not been dug out serves as a pillar region;

forming a first gate oxide layer in the first gate trench;

forming a first gate electrode on the first gate oxide layer;

A first doping type well region is formed in an upper part of the epitaxial layer, the bottom of the well region is higher than the top of the pillar region and the part of the epitaxial layer located below the well region serves as a drift region, so that the well region (6) The well region and the pillar region are arranged adjacent to each other up and down, and are separated by the drift region and the first gate oxide layer.

The embodiment of the present application also provides an IGBT device, including:

a first doped type collector;

A second doping type drift region is formed above the collector;

A well region of a first doping type is formed above the drift region, and the well region and the drift region are arranged adjacent to each other;

A first gate trench penetrates the well region and extends downward into the drift region;

A first gate oxide layer is formed in the first gate trench and the lower end of the first gate oxide layer extends into the drift region;

A first doping type pillar region is formed in the drift region, an upper part of the pillar region is connected to the first gate oxide layer, and the pillar region and the well region are connected by the drift region and The first gate oxide layer is separated;

A first gate electrode is formed on the first gate oxide layer.

Due to the adoption of the above technical solutions, the embodiments of the present application have the following technical effects:

Only one step of growing the epitaxial layer is required, growing the epitaxial layer only on the substrate. That corresponds to the first growth of the epitaxial layer in the preparation steps of the traditional superjunction structure. Digging downward from the upper surface of the epitaxial layer to form a pillar area trench; filling the pillar area trench with the first doping type material. After that, trenching is performed to form a first gate trench, which extends downward from the upper surface of the first doped type material, and the first doped type material that has not been dug out serves as a pillar region. That is, the position of the first gate trench is located above the pillar region. On the one hand, the position of the first gate trench is specifically limited. On the other hand, there is no longer any gap between the first gate trench and the pillar region. other structures. Afterwards, a first gate oxide layer and a first gate electrode are formed. After the first gate is formed, a well region is formed. The range of the well region is strictly limited. The bottom of the well region is higher than the top of the pillar region. The part of the epitaxial layer located below the well region serves as a drift region. In this way, the well region is directly formed. Above the drift region, the well region 6 and the drift region 2 are arranged adjacent to each other. At the same time, it is also required that the well region and the pillar region are separated by the drift region and the first gate oxide layer, and there is no direct contact between the well region and the pillar region.

Description of the drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic structural diagram of a traditional super junction IGBT device in the background technology;

Figure 2 is a flow chart of a method for manufacturing an IGBT device according to an embodiment of the present application;

Figure 3 is a schematic structural diagram of an implementation of the IGBT device according to the embodiment of the present application;

Figure 4 is a schematic structural diagram of another implementation of the IGBT device according to the embodiment of the present application;

Figure 5 is a schematic structural diagram of another embodiment of the IGBT device according to the embodiment of the present application;

Figure 6 is the breakdown voltage curve of the IGBT device shown in Figure 3;

Figure 7 is a transfer characteristic curve diagram of the IGBT device shown in Figure 3;

Figure 8 is the output characteristic curve of the IGBT device shown in Figure 3;

Figure 9 is the turn-off curve of the IGBT device shown in Figure 3;

Figure 10 is a turn-on curve diagram of the IGBT device shown in Figure 4.

Reference signs:

In background technology:

1 is the P-collector region, 2 is the N-drift region, 3 is the P-type super junction region, 4 is the second epitaxy, 5 is the gate oxide layer, 6 is the gate, 7 is Pwell, 8 is the N+ emitter , 9 is the dielectric layer, 10 is the emitter metal, 11 is the P+ collector, 12 is the collector metal;

In the specific implementation mode of this application:

Collector region 1, drift region 2, pillar region 3, first gate oxide layer 41, first gate electrode 51, second gate oxide layer 42, second gate electrode 52, well region 6, emitter 7, dielectric layer 8 , emitter metal 9, collector 10, collector metal 11.

Detailed ways

In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application. This is not an exhaustive list of all embodiments. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments of this application can be combined with each other.

Embodiment 1

The preparation method of the IGBT device according to the embodiment of the present application, as shown in Figures 2 to 5, includes the following steps:

Step S1: Form an epitaxial layer of a second doping type on a substrate of a first doping type. The specific method is to grow an epitaxial layer of the second doping type on the upper surface of the substrate of the first doping type;

Step S2: Dig trenches downward from the upper surface of the epitaxial layer to form trenches in the pillar area;

Step S3: Fill the trench in the column area with the first doping type material;

Step S4: Dig a trench to form a first gate trench. The first gate trench extends downward from the upper surface of the first doped type material. Part of the first doped type material is dug out, and some of the first doped type material is not dug out. Remove the first doping type material as column region 3;

Step S5: Form the first gate oxide layer 41 in the first gate trench; the specific method is to form the first gate oxide layer 41 in the first gate trench. A first gate oxide layer is grown on the inner bottom and sidewalls of the gate trench;

Step S6: Form the first gate 51 on the first gate oxide layer;

Step S7: Form a first doping type well region 6 in the upper part of the epitaxial layer, the bottom of the well region 6 is higher than the top of the pillar region and the part of the epitaxial layer below the well region serves as a drift region, so that the well region 6 and the drift region 2 are arranged adjacent to each other up and down, and the well region 6 and the pillar region 3 are separated by the drift region 2 and the first gate oxide layer 41; that is, the well region 6 and the drift region 2 are directly There is no contact between the well region 6 and the pillar region 3.

The preparation method of the IGBT device in the embodiment of the present application only requires one step of growing the epitaxial layer, and only the epitaxial layer is grown on the substrate. That corresponds to the first growth of the epitaxial layer in the preparation steps of the traditional superjunction structure. Digging downward from the upper surface of the epitaxial layer to form a pillar area trench; filling the pillar area trench with the first doping type material. After that, trenching is performed to form a first gate trench. The first gate trench extends downward from the upper surface of the first doped type material, and the first doped type material that has not been dug out serves as a pillar region. That is, the position of the first gate trench is located above the pillar region. On the one hand, the position of the first gate trench is specifically limited. On the other hand, there is no longer any gap between the first gate trench and the pillar region. other structures. Afterwards, a first gate oxide layer and a first gate electrode are formed. After the first gate is formed, a well region is formed. The range of the well region is strictly limited. The bottom of the well region is higher than the top of the column region. The part of the epitaxial layer located below the well region serves as the drift region. In this way, the well region is directly formed on the drift region. Above the well region 6 and the drift region 2 are arranged adjacently up and down. The well region and the drift region are in direct contact with no other structures between them. At the same time, it is also required that the well region and the pillar region are separated by the drift region and the first gate oxide layer, and there is no direct contact between the well region and the pillar region.

The pillar region and the well region are separated by the first gate oxide layer and the drift region, thereby achieving separation between the upper part of the pillar region of the first doping type and the well region of the first doping type. By controlling the depth of the first gate trench, the first gate oxide layer being directly connected to the pillar area, and controlling the size of the pillar area and the first gate oxide layer, isolation between the pillar area and the well area is achieved without the need for separate The realization of the epitaxial layer makes the steps of the preparation method of the IGBT device simple, the structure of the prepared IGBT device is simpler, and it also makes the cost of the IGBT device lower.

In implementation, as shown in Figures 2 to 4, the preparation method of the IGBT device also includes the following steps:

forming an emitter 7 of a second doping type on the well region 6 of the first doping type;

Form a dielectric layer 8, which is located on the first gate electrode 51 and the first gate oxide layer 41;

The emitter metal 9 is formed. The emitter metal 9 is located in the dielectric layer and the part of the emitter 7 that is not covered by the dielectric layer. The dielectric layer 8 realizes the connection between the first gate and the emitter metal 9 insulation;

The part of the substrate located below the drift region serves as the collector 1 of the first doping type;

A collector metal 11 is formed, which is located under the collector electrode 1 .

In this way, the structure of the IGBT device is prepared.

It should be noted that in Figures 3, 4 and 5, the emitter 7 is a separate layer. The form of the emitter may also be formed in the well region, with the emitter located in part of the area on both sides of the first gate, and in part of the area on both sides of the subsequently prepared second gate.

It should be noted that in order to realize that the well region and the pillar region are separated by the drift region and the first gate oxide layer, there are specific requirements for the corresponding relationship between the first gate trench and the pillar region, which will be described below in two cases.

The first case: in the step of forming the first gate trench, when one first gate trench corresponds to one of the pillar regions:

Correspondingly, the first gate trench is located above the pillar region;

In the lateral direction of the IGBT device, the size of the first gate trench is larger than the size of the pillar region 3, and the center surface of the first gate trench along its extension direction and the center surface of the pillar area along its extension direction Overlapping, correspondingly, the size of the first gate oxide layer is larger than the size of the pillar region 3, and the central plane of the first gate oxide layer along its extending direction coincides with the central plane of the pillar region along its extending direction;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.

The upper end surface of the pillar region is only connected to the outer bottom of the first gate trench.

Correspondingly, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the pillar region 3 , and the size of the first gate oxide layer 41 is greater than or equal to the size of the pillar region 3 ;

Among them, the width direction of the IGBT device is the extension direction of a single pillar region in the IGBT device.

In both the lateral direction and the width direction of the IGBT device, the upper end surface of the pillar region can be connected only to the outer bottom of the corresponding first gate trench.

The second case: in the step of forming the first gate trench, when one pillar region corresponds to two first gate trenches:

Correspondingly, in the lateral direction of the IGBT device, the two first gate trenches are respectively located on both sides of the pillar region, and a first gate trench remains between the two first gate trenches. The doping type material is a part of the pillar area. Correspondingly, the two first gate oxide layers are respectively located on both sides of the pillar area, and a first gate oxide layer remains between the two first gate oxide layers. The doped type material is part of the pillar area;

In the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the pillar region 3. Correspondingly, the size of the first gate oxide layer 41 is greater than or equal to the size of the pillar region 3. size;

In this way, in the lateral direction and width direction of the IGBT device, the upper end of the pillar region can realize a partial connection with the two corresponding first gate oxide layers, and the pillar region is located between the two first gate oxide layers. Then, the upper part of the pillar region and the well region are separated by the first gate oxide layer and the drift region.

Specifically, the dielectric layer also covers the top of the part between the two first gate oxide layers in the pillar area. The pillar area is in contact with the first gate oxide layer, the drift area, and the dielectric layer. There is no direct connection between the pillar area and the well area. touch.

In the implementation, in the step of digging downward from the upper surface of the epitaxial layer to form the pillar area trench, there is a preset distance between the bottom of the pillar area trench and the lower surface of the epitaxial layer. Correspondingly, there is a preset distance between the bottom of the column area and the lower surface of the drift area.

In this way, there is a preset distance between the lower end of the column area and the lower surface of the drift area. Achieved the first doping The lower end, left end and right end of the impurity-type pillar region are all drift regions of the second doping type. The upper part of the pillar region is separated from the well region by the first gate oxide layer and the drift region, thereby achieving separation between the upper part of the pillar region of the first doping type and the well region of the first doping type. That is, the floating arrangement of the pillar region 3 of the first doping type is achieved.

As an optional method, the step of digging includes a trenching process. A trenching process forms a first gate trench and a second gate trench. The second gate trench is formed from an upper surface of the epitaxial layer. The surface extends downward; wherein, in the lateral direction of the IGBT device, the size of the first gate trench is larger than the size of the second gate trench. Wherein, the second gate trench is above between the two pillar regions.

The first gate trench and the second gate trench are formed through one trenching process. Since the size of the first gate trench is larger than the size of the second gate trench in the lateral direction of the IGBT device, the second gate trench is formed by a single trenching process. The depth of one gate trench is greater than the depth of the second gate trench. This is determined by the trenching process.

As another optional method, the step of performing trenching includes two trenching processes, one trenching process forms the first gate trench, and the other trenching process forms the second gate trench. The electrode trench extends downward from the upper surface of the epitaxial layer, and the depth of the first gate trench is greater than or equal to or less than the depth of the second gate trench; wherein, in the lateral direction of the IGBT device, the first gate The size of the gate trench is larger than, equal to, or smaller than the size of the second gate trench. The most common situation is that the size of the first gate trench is larger than the size of the second gate trench.

Two trenching processes are used to form the first gate trench and the second gate trench respectively. The depth relationship between the first gate trench and the second gate trench can be controlled according to the actual needs of the IGBT device.

Specifically, there are multiple dielectric layers, which are respectively formed on the first gate, the first gate oxide layer and the column region between the two first gate trenches, and are formed on the second gate and the pillar region. above the second gate oxide layer.

Embodiment 2

As shown in Figure 3, Figure 4 and Figure 5, the IGBT device according to the embodiment of the present application includes:

A collector 10 of a first doping type;

The drift region 2 of the second doping type is formed on the collector electrode 10;

A first doped type well region 6 is formed on the drift region 2, and the well region 6 and the drift region 2 are arranged adjacent to each other;

A first gate trench penetrates the well region 6 and extends downward into the drift region 2;

A first gate oxide layer 41 is formed in the first gate trench and the lower end of the first gate oxide layer 41 extends into the drift region 2;

A first doping type pillar region 3 is formed in the drift region 2 , an upper part of the pillar region 3 is connected to the first gate oxide layer 41 , and the pillar region 3 is connected to the well region 6 Separated by the drift region 2 and the first gate oxide layer 41;

The first gate 51 is formed on the first gate oxide layer 41 .

In the IGBT device according to the embodiment of the present application, the well region and the drift region are arranged adjacent to each other, that is, the well region is directly formed on the drift region, and there is no other layer structure between the two layers. The first gate trench penetrates the well region and extends downward into the drift region, so that the lower end of the first gate oxide layer formed in the first gate trench extends into the drift region. The upper part of the pillar area in the drift area is connected to the first gate oxide layer, and the pillar area and the well area are separated by the drift area and the first gate oxide layer, that is, the pillar area and the well area are separated by the first gate oxide layer and the drift area. The regions are separated to achieve separation between the upper part of the first doped type pillar region and the first doped type well region. In the traditional super junction structure, an epitaxial layer of the second doping type needs to be provided between the well region of the first doping type and the drift region of the second doping type. The important role of the epitaxial layer is to transfer the first doping type in the drift region. The impurity type pillar region is separated from the first doping type well region above the epitaxial layer. In this way, the IGBT device of the embodiment of the present application realizes the pillar region and well by controlling the depth of the first gate trench, the first gate oxide layer directly connected to the pillar region, and controlling the size of the pillar region and the first gate oxide layer. The isolation between regions does not need to be achieved by setting up an epitaxial layer, which makes the structure of the IGBT device simpler and also makes the cost of the IGBT device lower.

In implementation, IGBT devices also include:

Collector metal 11 is formed under the collector;

The emitter 7 of the second doping type is formed on the well region 6, and the first gate trench penetrates the emitter and the well region; The surface is flush with the upper surface of the emitter;

A dielectric layer 8 is formed on the first gate electrode and the first gate oxide layer;

The emitter metal 9 is formed on the dielectric layer and the part of the emitter 7 that is not covered by the dielectric layer. The dielectric layer 8 realizes the insulation between the first gate and the emitter metal 9 .

It should be noted that in Figures 3, 4 and 5, the emitter is a separate layer. The emitter may also be formed in the well region, and the emitter is located in a partial region on both sides of the first gate. When the emitter is formed in the well region, the first gate trench penetrates the well region; the upper surfaces of the first gate and the second gate are flush with the upper surface of the emitter.

In implementation, as shown in FIGS. 3 , 4 and 5 , there is a preset distance between the lower end of the column area 3 and the lower surface of the drift area 2 .

In this way, there is a preset distance between the lower end of the column area and the lower surface of the drift area. It is realized that the lower end, left end and right end of the first doping type pillar region are all drift regions of the second doping type. The upper part of the pillar region and the well region are separated by the first gate oxide layer and the drift region, thereby achieving separation between the upper part of the pillar region of the first doping type and the well region of the first doping type. That is, the floating arrangement of the pillar region 3 of the first doping type is achieved.

As an optional method, the second doping type is N-type doping, and the first doping type is P-type doping.

Embodiment 3

The IGBT device of the third embodiment, based on the second embodiment, also has the following characteristics.

As shown in Figures 3 and 4, in the IGBT device of Embodiment 2, one pillar region 3 corresponds to one first gate trench, and correspondingly, one pillar region 3 corresponds to one first gate oxide layer 41 ;

The upper end surface of the pillar region is only connected to the corresponding first gate oxide layer, that is, the upper end surface of the pillar region is not in contact with the well region.

In this way, the upper part of the pillar region and the well region are isolated.

In order to realize that the upper end surface of the pillar area is only connected to the corresponding first gate oxide layer, the dimensions of the first gate trench, the first gate oxide layer, and the pillar area need to meet the following requirements:

As shown in FIGS. 3 and 4 , in the lateral direction of the IGBT device, the size of the first gate trench is larger than the size of the pillar region 3 , and correspondingly, the size of the first gate oxide layer 41 is larger than The size of the column area 3;

The central plane of the first gate trench along its extending direction coincides with the central plane of the pillar region along its extending direction. Correspondingly, the central plane of the first gate oxide layer along its extending direction coincides with the central plane of the pillar region along its extending direction. coincide. That is, in the lateral direction of the IGBT device, the first gate oxide layer and the pillar region are aligned;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device. In Figures 3 and 4, the width direction of the IGBT device is perpendicular to the paper surface.

In the width direction of the IGBT device, the size of the first gate oxide layer 41 is greater than or equal to the size of the pillar region 3. In this way, in the width direction of the IGBT device, the upper end surface of the pillar region can realize only the corresponding third The lower end face of a gate oxide layer is connected.

In this way, in the width direction of the IGBT device, the upper end surface of the pillar region can be connected only to the corresponding lower end surface of the first gate oxide layer. Therefore, in both the lateral direction and the width direction of the IGBT device, the upper end surface of the pillar region can be connected only to the corresponding lower end surface of the first oxide layer.

In implementation, as shown in Figure 3 and Figure 4, the IGBT device also includes:

A second gate trench penetrates the well region and extends downward into the drift region 2;

A second gate oxide layer 42 is formed in the second gate trench and the lower end of the second gate oxide layer 42 extends into the drift region 2;

The second gate 52 is formed on the second gate oxide layer 42;

The second gate oxide layer 42 is located between the two first gate oxide layers.

The number and position of the first gate electrodes 51 are determined according to the number and position of the pillar regions. The number of gate electrodes of the IGBT device is determined according to the device. After the number of first gate electrodes is determined, the number of second gate electrodes is also determined. Specifically, one or more second gates may be provided between the two first gates according to actual needs.

In this embodiment, in the lateral direction of the IGBT device, since the size of the first gate oxide layer 41 must be larger than the size of the pillar region 3, the sizes of the first gate trench and the first gate electrode are also correspondingly large. are restricted. The sizes of the second gate trench, the second gate oxide layer and the second gate are not limited by the pillar region. In the lateral direction of the IGBT device, generally, the size of the first gate trench will be larger than the size of the second gate trench.

If the first gate trench and the second gate trench are formed through one trenching process, the depth of the first gate trench will be greater than the depth of the second gate trench. In the current trenching process, in the same trenching process, the wider the trench is, the deeper the trench is. The depth of the first gate trench in FIG. 3 is greater than the depth of the second gate trench, and the first gate trench and the second gate trench are formed through one trenching process.

If the first gate trench and the second gate trench are formed through two trenching processes, the depth of the first gate trench may be greater than, equal to, or less than the depth of the second gate trench. The depth of the first gate trench in Figure 4 is equal to the depth of the second gate trench, and the first gate trench and the second gate trench are formed through two trenching processes.

Figure 6 is a breakdown voltage curve of the IGBT device shown in Figure 3; Figure 7 is a transfer characteristic curve of the IGBT device shown in Figure 3; Figure 8 is an output characteristic curve of the IGBT device shown in Figure 3; Figure 9 is a diagram The turn-off curve of the IGBT device shown in Figure 3 is shown; Figure 10 is the turn-on curve of the IGBT device shown in Figure 4. It can be seen from this that the various curves of the IGBT device shown in Figure 3 illustrate that the IGBT device of the present application and Traditional IGBT devices have no difference in dynamic and static parameters.

Embodiment 4

The IGBT device of the fourth embodiment, based on the second embodiment, also has the following characteristics.

As shown in Figure 5, in the IGBT device of Embodiment 2, one pillar region 3 corresponds to two adjacent first gate trenches, and the two first gate trenches corresponding to the same pillar region are separated by A part of the pillar region 3 is filled, that is, there is no material in the well region between the two first gate trenches corresponding to the same pillar region 3, but it is filled with the material in the pillar region. Correspondingly, one of the pillar regions Areas correspond to two first gate oxide layers;

The pillar area 3 is connected to the two corresponding first gate oxide layers 41 , and the space between the two first gate oxide layers 41 connected to the same pillar area is a part of the pillar area 3 .

The pillar region is not only formed in the drift region, but also a part of the pillar region is formed between the two first gate oxide layers connected to the pillar region. In this way, the upper part of the pillar region is in contact with the first gate oxide layer and the drift region, but not with the well region, thereby achieving isolation between the upper part of the pillar region and the well region.

In Embodiment 3, in the lateral direction of the IGBT device, the sizes of the first gate, the first gate oxide layer and the first gate trench are determined according to the size of the pillar region. In Embodiment 4, in the lateral direction of the IGBT device, after the size of the first gate is determined, the sizes of the corresponding first gate oxide layer and the first gate trench are also determined. After the size of the first gate oxide layer is determined and the conditions for charge balance in the super junction region are met, the size of the pillar region in the lateral direction of the IGBT device is comprehensively determined.

In implementation, as shown in Figure 5, in the lateral direction of the IGBT device, the size of the pillar region 3 is smaller than the size between the outer edges of the two first gate oxide layers connected to it;

The center plane of the column region 3 along its extension direction coincides with the center plane between the two first gate oxide layers connected to the column region 3 . That is, in the lateral direction of the IGBT device, the pillar area and the two first gate oxide layers connected to it are aligned;

Wherein, the lateral direction of the IGBT device is the arrangement direction of the pillar regions of the IGBT device.

In this way, in the lateral direction of the IGBT device, the upper end of the pillar area can realize the two corresponding The first gate oxide layer is connected to the first gate oxide layer, and the upper part of the pillar region is separated from the well region by the first gate oxide layer and the drift region.

Further, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the column region 3 , and the size of the first gate oxide layer 41 is equal to or greater than the size of the column region 3 .

In this way, in the width direction of the IGBT device, the upper part of the pillar region can be connected only to the corresponding first gate oxide layer.

In implementation, as shown in Figure 5, the IGBT device also includes:

The second gate 52 is formed on the second gate oxide layer 42;

The second gate oxide layer 42 is located between the two pillar regions in the well region and the drift region.

The number and position of the first gate electrodes 51 are determined according to the number and position of the pillar regions. The number of gate electrodes of the IGBT device is determined according to the device. After the number of first gate electrodes is determined, the number of second gate electrodes is also determined. Specifically, one or more second gates may be disposed in the well region and the drift region between the two pillar regions according to actual needs.

In implementation, in the lateral direction of the IGBT device, the first gate trench and the second gate trench have the same size, and the first gate trench and the second gate trench have the same depth.

In this embodiment, the first gate trench and the second gate trench are formed by one trenching to achieve the same size of the first gate trench and the second gate trench. The second gate trenches have the same depth.

In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "front", "back", "first", "tail", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of To facilitate the description of this application Please and simplify the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be construed as a limitation of the present application.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

In this application, unless otherwise explicitly stipulated and limited, the terms "installation", "connection" and other terms should be understood in a broad sense; taking connection as an example, it can be directly connected, or it can be indirectly connected through an intermediary, or it can be two The connection within an element or the interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

Although some alternative embodiments of the present application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are understood. Therefore, it is intended that the appended claims be construed to include alternative embodiments and all changes and modifications that fall within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A method for preparing an IGBT device, characterized in that it includes the following steps:

forming an epitaxial layer of a second doping type on the first doping type substrate;

Digging downward from the upper surface of the epitaxial layer to form trenches in the pillar area;

The trench in the pillar region is filled with the material of the first doping type;

Digging to form a first gate trench extending downward from the upper surface of the first doped type material, wherein the first doped type material that has not been dug out serves as a pillar region;

forming a first gate oxide layer in the first gate trench;

forming a first gate electrode on the first gate oxide layer;

A first doping type well region is formed in an upper part of the epitaxial layer, the bottom of the well region is higher than the top of the pillar region and the part of the epitaxial layer located below the well region serves as a drift region, so that the well region (6) and the drift region (2) are arranged adjacent to each other up and down, and the well region and the column region are separated by the drift region and the first gate oxide layer.
The method for manufacturing an IGBT device according to claim 1, wherein in the step of forming a first gate trench, one first gate trench corresponds to one of the pillar regions, and the first gate trench located above said column area;

In the lateral direction of the IGBT device, the size of the first gate trench is larger than the size of the column region (3), and the center surface of the first gate trench along its extending direction and the center surface of the column region along its extending direction The central planes coincide with each other. Correspondingly, the size of the first gate oxide layer is larger than the size of the pillar region, and the central plane of the first gate oxide layer along its extending direction coincides with the central plane of the pillar region along its extending direction;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.
The method for preparing an IGBT device according to claim 2, characterized in that, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the column region (3), correspondingly, The size of the first gate oxide layer (41) is greater than or equal to the size of the pillar region (3);

Among them, the width direction of the IGBT device is the extension direction of a single pillar region in the IGBT device.
The method for preparing an IGBT device according to claim 1, wherein the first In the step of forming a gate trench, one pillar region corresponds to two first gate trenches;

In the lateral direction of the IGBT device, the two first gate trenches are respectively located on both sides of the pillar region, and the first doping type is retained between the two first gate trenches. The material is part of the pillar area, and correspondingly, the two first gate oxide layers are respectively located on both sides of the pillar area;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.
The method for preparing an IGBT device according to claim 4, characterized in that, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the column region (3), correspondingly, The size of the first gate oxide layer (41) is greater than or equal to the size of the pillar region (3);

Among them, the width direction of the IGBT device is the extension direction of a single pillar region in the IGBT device.
The method for preparing an IGBT device according to claim 1, further comprising the following steps:

forming an emitter of a second doping type (7);

Form a dielectric layer (8), the dielectric layer is located above the first gate electrode and the first gate oxide layer;

Forming an emitter metal (9), the emitter metal (9) is located in the dielectric layer and the part of the emitter (7) not covered by the dielectric layer, and the dielectric layer (8) realizes the first gate Insulation between pole and emitter metal (9);

The part of the substrate located below the drift region serves as the collector of the first doping type (1);

A collector metal (11) is formed which is located under the collector electrode (1).
The method for preparing an IGBT device according to claim 1, wherein in the step of digging downward from the upper surface of the epitaxial layer to form a pillar area trench, the bottom of the pillar area trench and the epitaxial area have a preset distance between their lower surfaces.
The method for manufacturing an IGBT device according to claim 1, wherein the step of trenching includes one trenching process, and one trenching process forms the first gate trench and the second gate trench, and the third gate trench is formed by the trenching process. The two gate trenches extend downward from the upper surface of the epitaxial layer, and the depth of the first gate trench is greater than the depth of the second gate trench; wherein, in the lateral direction of the IGBT device, the first gate trench The size of the groove is larger than the size of the second gate trench;

Alternatively, the step of trenching includes two trenching processes, one trenching process forms a first gate trench, and another trenching process forms a second gate trench, and the second gate trench is formed from the epitaxial layer. The upper surface extends downward, and the depth of the first gate trench is greater than, equal to, or less than the depth of the second gate trench; wherein, in the lateral direction of the IGBT device, the size of the first gate trench is greater than or equal to the depth of the second gate trench. The size of the second gate trench;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.
An IGBT device, characterized by including:

a first doped type collector (10);

A second doping type drift region (2) is formed on the collector electrode (10);

A first doping type well region (6) is formed above the drift region (2), and the well region (6) and the drift region (2) are arranged adjacent to each other;

A first gate trench penetrates the well region (6) and extends downward into the drift region (2);

A first gate oxide layer (41) is formed in the first gate trench and the lower end of the first gate oxide layer (41) extends into the drift region (2);

A first doping type pillar region (3) is formed in the drift region (2), the upper part of the pillar region (3) is connected to the first gate oxide layer (41), and the pillar Region (3) and the well region (6) are separated by the drift region (2) and the first gate oxide layer (41);

A first gate electrode (51) is formed on the first gate oxide layer (41).
The IGBT device according to claim 9, further comprising:

Collector metal (11) formed under the collector;

A second doped type emitter (7), the first gate trench penetrates the well region; the upper surface of the first gate and the first gate oxide layer is flush with the upper surface of the emitter;

A dielectric layer (8) formed on the first gate electrode and the first gate oxide layer;

The emitter metal (9) is formed on the dielectric layer and the part of the emitter (7) not covered by the dielectric layer. The dielectric layer (8) realizes the first gate and the emitter metal ( 9) Insulation between.
The IGBT device according to claim 10, characterized in that there is a preset distance between the lower end of the pillar region (3) and the lower surface of the drift region (2).
The IGBT device according to claim 11, wherein one pillar region corresponds to a first gate trench, and correspondingly, one pillar region corresponds to one first gate oxide layer;

The upper end surface of the pillar area is only connected to the corresponding lower end surface of the first gate oxide layer, and the side surfaces and lower end surface of the pillar area are only connected to the drift area.
The IGBT device according to claim 12, characterized in that, in the lateral direction of the IGBT device, the size of the first gate trench is larger than the size of the column region (3), and correspondingly, the first gate trench is The size of the gate oxide layer (41) is larger than the size of the pillar region (3);

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.
The IGBT device according to claim 13, characterized in that, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the pillar region (3), and correspondingly, the size of the first gate trench is greater than or equal to the size of the pillar region (3). The size of a gate oxide layer (41) is greater than or equal to the size of the pillar region (3);

Among them, the width direction of the IGBT device is the extension direction of a single pillar region in the IGBT device.
The IGBT device according to claim 10, wherein one pillar region corresponds to two adjacent first gate trenches, and the two first gate trenches corresponding to the same pillar area are separated by A part of the pillar area is fully filled, correspondingly, one pillar area corresponds to two first gate oxide layers;

The pillar area is connected to the two corresponding first gate oxide layers, and the space between the two first gate oxide layers connected to the same pillar area is a part of the pillar area.
The IGBT device according to claim 15, characterized in that, in the lateral direction of the IGBT device, the size of the column region (3) is smaller than the size between the outer edges of the two first gate oxide layers connected thereto;

Among them, the lateral direction of the IGBT device is the arrangement direction of the column area of the IGBT device.
The IGBT device according to claim 16, characterized in that, in the width direction of the IGBT device, the size of the first gate trench is greater than or equal to the size of the column region (3), and the first gate oxide The size of the layer (41) is greater than or equal to the size of the column area (3);

Among them, the width direction of the IGBT device is the extension direction of a single pillar region in the IGBT device.