CN108376708B - Semiconductor device with voltage-resistant structure and manufacturing method thereof - Google Patents
Semiconductor device with voltage-resistant structure and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 57
- 229920005591 polysilicon Polymers 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a semiconductor device with a voltage-resistant structure and a manufacturing method thereof, relating to the technical field of semiconductor chips and comprising the following steps: the device comprises an N-type substrate, an N + region, a P-body region, a voltage-resistant oxide layer, a polysilicon region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, a device source metal and a device drain metal. The voltage-resistant oxide layers are respectively arranged on two sides of the central region of the N + region and are respectively attached to the side regions of the N + region, the voltage-resistant oxide layers are concave oxide layers, and the polycrystalline silicon regions are filled in the concave regions of the voltage-resistant oxide layers. The technical scheme relieves the technical problem of poor voltage resistance of the device structure in the prior art, effectively ensures the voltage resistance of the device, improves the saturation current of the semiconductor device, reduces the on-resistance of the device, effectively utilizes the area of the device, reduces the production cost of the device and improves the on-resistance of the semiconductor device.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a semiconductor device with a voltage-resistant structure and a manufacturing method thereof.
Background
At present, the structure of the MOS device mainly includes source metal, dielectric layer isolation, a poly-crystalline gate, a gate oxide layer, a device P-type body region, a device N + source region, a device N-type epitaxial layer, a device N-type substrate, and device drain metal. In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art: the MOS device has large on-resistance, and when the device is turned on, electrons start from the N-type source electrode, pass through the channel, the N-type epitaxial layer and the N-type substrate and finally reach the drain electrode. In order to increase the device breakdown voltage, the N-type epitaxial layer must be thick, and the thicker the N-type epitaxial layer, the greater the on-resistance of the device. If the device withstand voltage is to be improved, a terminal withstand voltage structure is usually added, and the area of the device is greatly wasted. Therefore, the prior art has the technical problem of poor voltage endurance performance of the device structure.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device having a voltage-withstanding structure and a method for fabricating the same, so as to alleviate the technical problem of poor voltage-withstanding performance of the device structure in the prior art.
In a first aspect, an embodiment of the present invention provides a semiconductor device having a voltage-resistant structure, including: the device comprises an N-type substrate, an N + region, a P-body region, a voltage-resistant oxide layer, a polysilicon region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, a device source metal and a device drain metal;
the N + region is an electronic drift region consisting of a central region, a bottom edge region and a side edge region;
the upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the voltage-resistant oxide layers are respectively arranged at two sides of the central region of the N + region, and the upper surface of the pressure-resistant oxide layer, the upper surface of the connection part of the polysilicon region and the N + source region, the upper surface of the side edge region of the N + region is provided with a device source electrode metal, the upper surface of the side edge region of the N + region is provided with a device drain electrode metal, and dielectric isolation layers are horizontally laid between the upper surface of the polysilicon gate and the device source electrode metal as well as between the device source electrode metal and the device drain electrode metal.
Furthermore, in the semiconductor device with the withstand voltage structure provided by the embodiment of the invention, the bottom of the withstand voltage oxide layer is attached to the bottom of the N + region.
Further, in the semiconductor device having a withstand voltage structure provided by the embodiment of the present invention, the distance L1 between the side edge of the withstand voltage oxide layer and the central region of the N + region is equal to the distance L2 between the bottom of the withstand voltage oxide layer and the bottom of the N + region.
Furthermore, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the thickness of the voltage-resistant oxide layer is 0.5-0.8 μm.
Furthermore, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the width of the voltage-resistant oxide layer is 2-5 μm.
Furthermore, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the depth of the concave region of the voltage-resistant oxide layer is 2-10 μm.
Furthermore, in the semiconductor device with the voltage-withstanding structure provided by the embodiment of the invention, the N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the cross-sectional width is 2-5 μm.
Further, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the N + region adopts a PTBI2T electron drift layer polymerized by a TBI material.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device having a voltage-resistant structure, including:
providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the epitaxy;
forming deep grooves on two sides of the P-epitaxial layer;
forming a pressure-resistant oxide layer inside the deep trench, wherein the pressure-resistant oxide layer is a concave oxide layer, and filling the concave region of the pressure-resistant oxide layer to form a polysilicon region;
injecting N-type ions through photoetching injection and thermal drive, forming N + areas at the central area of the N + area, the two side edges of the N + epitaxial layer and the P-epitaxial layer after the N + areas are driven in, and forming a P-body area between the two sides of the central area of the N + area and the voltage-resistant oxide layer;
forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid;
photoetching and injecting P-body regions at two sides of the polysilicon gate to form an N + source region;
forming device source metal on the upper surface of the joint of the voltage-resistant oxide layer, the polysilicon region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming a dielectric isolation layer among the device source metal, the device drain metal and the polysilicon gate.
Further, in the method for manufacturing a semiconductor device having a withstand voltage structure provided in the embodiment of the present invention, the forming of the withstand voltage oxide layer inside the deep trench specifically includes: and growing an oxide layer in the deep trench by adopting chlorine-based gas as atmosphere to form a pressure-resistant oxide layer.
The embodiment of the invention has the following beneficial effects: the semiconductor device with a voltage-resistant structure and the manufacturing method thereof provided by the embodiment of the invention comprise the following steps: the device comprises an N-type substrate, an N + region, a P-body region, a voltage-resistant oxide layer, a polysilicon region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, a device source metal and a device drain metal. The N + region is an electron drift region composed of a central region, a bottom edge region and side edge regions. The upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the voltage-resistant oxide layers are respectively arranged at two sides of the central region of the N + region, and the upper surface of the pressure-resistant oxide layer, the upper surface of the connection part of the polysilicon region and the N + source region, the upper surface of the side edge region of the N + region is provided with a device source electrode metal, the upper surface of the side edge region of the N + region is provided with a device drain electrode metal, and dielectric isolation layers are horizontally laid between the upper surface of the polysilicon gate and the device source electrode metal as well as between the device source electrode metal and the device drain electrode metal. According to the technical scheme, the withstand voltage oxide layer and the polycrystalline silicon filling technology are combined, so that the withstand voltage performance of the device is effectively guaranteed, the saturation current of the semiconductor device is improved, the on-resistance of the device is reduced, the area of the device is effectively utilized, the production cost of the device is reduced, the on-performance of the semiconductor device is improved, and the technical problem of poor withstand voltage performance of the device structure in the prior art is solved.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a cross-sectional view of a semiconductor device having a withstand voltage structure provided in an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a semiconductor device having a voltage-withstanding structure according to an embodiment of the present invention;
fig. 3 is a schematic product diagram of step S1 in the method for manufacturing a semiconductor device having a withstand voltage structure according to an embodiment of the present invention;
fig. 4 is a schematic product diagram of step S2 in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention;
fig. 5 is a schematic product diagram of step S3 in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention;
fig. 6 is a schematic product diagram of step S4 in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention;
fig. 7 is a schematic product diagram of step S5 and step S6 in the method for manufacturing a semiconductor device having a voltage-withstanding structure according to the embodiment of the present invention.
Icon:
a 1-N type substrate; a 2-N + region; 3-a voltage-resistant oxide layer; a 4-polysilicon region; a 5-N + source region; a 6-P-body region; 7-polysilicon gate; 8-a gate oxide layer; 9-dielectric layer isolation; 10-device source metal; 11-device drain metal.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the structure of the MOS device mainly includes source metal, dielectric layer isolation, a poly-crystalline gate, a gate oxide layer, a device P-type body region, a device N + source region, a device N-type epitaxial layer, a device N-type substrate, and device drain metal. In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art: the MOS device has large on-resistance, and when the device is turned on, electrons start from the N-type source electrode, pass through the channel, the N-type epitaxial layer and the N-type substrate and finally reach the drain electrode. In order to increase the device breakdown voltage, the N-type epitaxial layer must be thick, and the thicker the N-type epitaxial layer, the greater the on-resistance of the device. Based on the fact that the area of the device is greatly wasted due to the fact that a terminal voltage-resistant structure is usually increased if the voltage resistance of the device is improved, the voltage-resistant performance of the device can be effectively guaranteed, the saturation current of the semiconductor device is improved, and the on-resistance of the device is reduced.
The first embodiment is as follows:
referring to fig. 1, a cross-sectional view of a semiconductor device having a withstand voltage structure according to an embodiment of the present invention is provided. The embodiment of the invention provides a semiconductor device with a voltage-resistant structure, which comprises: the device comprises an N-type substrate 1, an N + region 2, a P-body region 6, a voltage-resistant oxide layer 3, a polysilicon region 4, an N + source region 5, a gate oxide layer 8, a polysilicon gate 7, a dielectric layer isolation 9, a device source metal 10 and a device drain metal 11. Wherein, the withstand voltage oxide layer and the polysilicon region form a withstand voltage structure of the semiconductor device. The N + region is an electron drift region composed of a central region, a bottom edge region and side edge regions. The cross section of the side area is square, the cross section of the central area is square, and the central area is positioned in the center of the side area, and the bottom area is square and positioned at the bottom of the device.
The upper part of the N-type substrate is connected with the bottom edge area of the N + area, the inner surface of the N + area extends to form a P-body area towards the central area, the pressure-resistant oxide layers are respectively arranged at two sides of the central area of the N + area and are respectively attached to the side edge areas of the N + area, the pressure-resistant oxide layers are concave oxide layers, and the polycrystalline silicon areas are filled in the concave areas of the pressure-resistant oxide layers.
In the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the width of the concave groove formed by the voltage-resistant oxide layer is 2-5 mu m. The above-mentioned voltage-resistant oxide layer can be arranged in various selection ways, such as:
in a first mode, in the semiconductor device with a withstand voltage structure provided by the embodiment of the present invention, the bottom of the withstand voltage oxide layer is attached to the bottom of the N + region. At the moment, the withstand voltage of the device depends on the thickness of the withstand voltage oxide layer and the distance between the side edge of the withstand voltage oxide layer and the central area of the N + area, the distance and the thickness are increased, and the device is ensured to have enough depletion area thickness to bear the withstand voltage.
In a second mode, in the semiconductor device with a withstand voltage structure provided by the embodiment of the present invention, the distance L1 between the side edge of the withstand voltage oxide layer and the central region of the N + region, and the distances L2 between the bottom of the withstand voltage oxide layer and the bottom of the N + region, L1 and L2 are equal to each other, so that the device can bear sufficient reverse voltage when subjected to high voltage reverse bias, thereby ensuring charge balance inside the device, and protecting the device from breakdown. Specifically, in the semiconductor device with the withstand voltage structure provided by the embodiment of the invention, the depth of the concave region of the withstand voltage oxide layer is 2-10 μm.
In the semiconductor device with a withstand voltage structure provided by the embodiment of the invention, an N + source region is arranged at the joint of the upper surface of a P-body region and a withstand voltage oxide layer, a gate oxide layer covers the upper surfaces of the joints of the N + source region, the N + region and the P-body region, a polysilicon gate is arranged above the gate oxide layer, device source metal is arranged on the upper surfaces of the joints of the withstand voltage oxide layer, the polysilicon region and the N + source region, device drain metal is arranged on the upper surface of a side edge region of the N + region, and dielectric isolation layers are horizontally laid between the upper surface of the polysilicon gate and the device source metal as well as between the device source metal and the device drain metal.
Furthermore, in the semiconductor device with the voltage-withstanding structure provided by the embodiment of the invention, the N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the cross-sectional width is 2-5 μm. Wherein the unit of the doping dose is the number of ions per square centimeter.
Further, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the N + region adopts a PTBI2T electron drift layer polymerized by a TBI material.
The semiconductor device with a voltage-resistant structure provided by the embodiment of the invention comprises: the device comprises an N-type substrate, an N + region, a P-body region, a voltage-resistant oxide layer, a polysilicon region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, a device source metal and a device drain metal. The N + region is an electron drift region composed of a central region, a bottom edge region and side edge regions. The upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the voltage-resistant oxide layers are respectively arranged at two sides of the central region of the N + region, and the upper surface of the pressure-resistant oxide layer, the upper surface of the connection part of the polysilicon region and the N + source region, the upper surface of the side edge region of the N + region is provided with a device source electrode metal, the upper surface of the side edge region of the N + region is provided with a device drain electrode metal, and dielectric isolation layers are horizontally laid between the upper surface of the polysilicon gate and the device source electrode metal as well as between the device source electrode metal and the device drain electrode metal. According to the technical scheme, the withstand voltage oxide layer and the polycrystalline silicon filling technology are combined, so that the withstand voltage performance of the device is effectively guaranteed, the saturation current of the semiconductor device is improved, the on-resistance of the device is reduced, the area of the device is effectively utilized, the production cost of the device is reduced, the on-performance of the semiconductor device is improved, and the technical problem of poor withstand voltage performance of the device structure in the prior art is solved.
Example two:
the manufacturing method of the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention comprises the following steps:
step S1: providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after epitaxy. Referring to fig. 3, in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention, a product in step S1 is schematically illustrated.
Step S2: deep trenches are formed on both sides of the P-epitaxial layer. Referring to fig. 4, in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention, a product in step S2 is schematically illustrated.
Step S3: and forming a pressure-resistant oxide layer inside the deep trench, wherein the pressure-resistant oxide layer is a concave oxide layer, and filling the concave region of the pressure-resistant oxide layer to form a polysilicon region. Referring to fig. 5, in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention, a product in step S3 is schematically illustrated. Furthermore, in the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the thickness of the voltage-resistant oxide layer is 0.5-0.8 μm, so that the voltage-resistant performance of the device is ensured, the saturation current of the semiconductor device is improved, the on-resistance of the device is reduced, the on-resistance of the semiconductor device is improved, and the area of the device is effectively utilized by the built-in voltage-resistant structure consisting of the voltage-resistant oxide layer and the polysilicon region, so that the production cost of the device is reduced. In the method for manufacturing the semiconductor device with the voltage-resistant structure, provided by the embodiment of the invention, the width of a concave groove formed by the voltage-resistant oxide layer is 2-5 microns. The above-mentioned voltage-resistant oxide layer can be arranged in various selection ways, such as:
in a first mode, in the method for manufacturing a semiconductor device with a withstand voltage structure provided by the embodiment of the invention, the bottom of the withstand voltage oxide layer is attached to the bottom of the N + region. At the moment, the withstand voltage of the device depends on the thickness of the withstand voltage oxide layer and the distance between the side edge of the withstand voltage oxide layer and the central area of the N + area, the distance and the thickness are increased, and the device is ensured to have enough depletion area thickness to bear the withstand voltage.
In a second mode, in the method for manufacturing the semiconductor device with the voltage-resistant structure provided by the embodiment of the invention, the distance L1 between the side edge of the voltage-resistant oxide layer and the central region of the N + region, and the distances L2 between the bottom of the voltage-resistant oxide layer and the bottom of the N + region, L1 and L2 are equal, so that the device can bear sufficient reverse voltage when the device is subjected to high-voltage reverse bias, thereby ensuring the charge balance inside the device, and protecting the device from breakdown. Specifically, the depth of the concave region of the voltage-resistant oxide layer is 2-10 μm.
Step S4: and injecting N-type ions through photoetching injection and thermal drive, forming N + areas at the central area of the N + area, the two side edges of the N + epitaxial layer and the P-epitaxial layer after the N + areas are driven in, and forming a P-body area between the two sides of the central area of the N + area and the voltage-resistant oxide layer. The cross section of the side area of the N + area is in a square shape; the cross section of the central area is in a straight shape and is positioned in the center of the side area; the bottom edge area is square and is positioned at the bottom of the device. Referring to fig. 6, in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention, a product in step S4 is schematically illustrated. The N + region employs a PTBI2T electron drift layer polymerized from a TBI material. Wherein the N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the cross-sectional width is 2-5 μm. Wherein the unit of the doping dose is the number of ions per square centimeter.
Step S5: and forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid. Wherein, the width of the grid oxide layer is equal to that of the polysilicon grid.
Step S6: and photoetching and injecting the P-body regions at two sides of the polysilicon gate to form an N + source region. Referring to fig. 7, in the method for manufacturing a semiconductor device having a withstand voltage structure according to the embodiment of the present invention, the product diagrams of step S5 and step S6 are shown (the N-type substrate is not shown).
Step S7: a device source metal is formed on the upper surface of the junction of the withstand voltage oxide layer, the polysilicon region and the N + source region, a device drain metal is formed on the upper surface of the side region of the N + region, and a dielectric isolation layer is horizontally laid and formed among the device source metal, the device drain metal and the polysilicon gate, which is the product in the cross-sectional view of the semiconductor device with the withstand voltage structure provided by the embodiment of the invention in fig. 1. The upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the voltage-resistant oxide layers are respectively arranged at two sides of the central region of the N + region and are respectively attached to the side edge regions of the N + region, the voltage-resistant oxide layer is a concave oxide layer, the polysilicon region is filled in the concave region of the voltage-resistant oxide layer, the upper surface of the P-body region is provided with an N + source region at the connection part with the voltage-resistant oxide layer, the grid oxide layer covers the upper surfaces of the N + source region, the N + region and the P-body region, a polysilicon grid is arranged above the grid oxide layer, the upper surface of the connection part of the voltage-resistant oxide layer and the silicon region with the N + source region is provided with device source metal, the upper surface of the side edge region of the N + region is provided with device drain metal, the upper surface of the polysilicon grid and the polysilicon grid metal are connected with the device source metal, And a dielectric isolation layer is horizontally laid between the device source electrode metal and the device drain electrode metal.
Further, in the method for manufacturing a semiconductor device with a withstand voltage structure provided by the embodiment of the present invention, the step of forming the withstand voltage oxide layer inside the deep trench in step S3 specifically includes: the oxide layer is grown in the deep groove by adopting chlorine-based gas as atmosphere to form a pressure-resistant oxide layer.
The method for manufacturing the semiconductor device with the voltage-resistant structure, provided by the embodiment of the invention, comprises the steps of firstly providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the N + epitaxial layer is formed. Secondly, forming deep grooves on two sides of the P-epitaxial layer; and forming a pressure-resistant oxide layer inside the deep trench, wherein the pressure-resistant oxide layer is a concave oxide layer, and filling the concave region of the pressure-resistant oxide layer to form a polysilicon region. And thirdly, injecting N-type ions through photoetching injection and thermal drive, forming N + areas at the central area of the N + area, the two sides of the N + epitaxial layer and the P-epitaxial layer after the N + ions are driven in, and forming a P-body area between the two sides of the central area of the N + area and the voltage-resistant oxide layer. Then, forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid; and photoetching and injecting the P-body regions at two sides of the polysilicon gate to form an N + source region. And finally, forming device source metal on the upper surface of the joint of the voltage-resistant oxide layer, the polysilicon region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming a dielectric isolation layer among the device source metal, the device drain metal and the polysilicon gate. According to the technical scheme, the withstand voltage oxide layer and the polycrystalline silicon filling technology are combined, so that the withstand voltage performance of the device is effectively guaranteed, the saturation current of the semiconductor device is improved, the on-resistance of the device is reduced, the area of the device is effectively utilized, the production cost of the device is reduced, the on-performance of the semiconductor device is improved, and the technical problem of poor withstand voltage performance of the device structure in the prior art is solved.
In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (7)
1. A semiconductor device having a withstand voltage structure, comprising: the device comprises an N-type substrate, an N + region, a P-body region, a voltage-resistant oxide layer, a polysilicon region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, a device source metal and a device drain metal;
the N + region is an electronic drift region consisting of a central region, a bottom edge region and a side edge region;
the upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form the P-body region, the voltage-resistant oxide layers are respectively arranged at two sides of the central region of the N + region and are respectively attached to the side edge regions of the N + region, the distance L1 between the side edge of the voltage-resistant oxide layer and the central region of the N + region is equal to the distance L2 between the bottom of the voltage-resistant oxide layer and the bottom of the N + region, and the depth and the thickness of the P-body region are both greater than those of the voltage-resistant oxide layers, so that the voltage-resistant oxide layers are surrounded by the P-body region and the side edge regions of the N + region; the dielectric isolation layer is horizontally laid on the upper surface of the polysilicon gate and between the upper surface of the polysilicon gate and the device source metal as well as between the device source metal and the device drain metal.
2. The semiconductor device according to claim 1, wherein a thickness of the withstand voltage oxide layer is 0.5 to 0.8 μm.
3. The semiconductor device according to claim 1, wherein a width of the withstand voltage oxide layer is 2 to 5 μm.
4. The semiconductor device according to claim 1, wherein a depth of the concave region of the withstand voltage oxide layer is 2 to 10 μm.
5. The semiconductor device according to claim 1, wherein the N + region is an N-type heavily doped region, the dopant amount is 1E 15-2E 15, and the cross-sectional width is 2-5 μm, wherein the unit of the dopant amount is the number of ions per square centimeter.
6. A method for manufacturing a semiconductor device with a voltage-resistant structure is characterized by comprising the following steps: providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the epitaxy;
forming deep grooves on two sides of the P-epitaxial layer;
forming a pressure-resistant oxide layer inside the deep trench, wherein the pressure-resistant oxide layer is a concave oxide layer, and filling a polycrystalline silicon region inside a concave region of the pressure-resistant oxide layer;
injecting N-type ions through photoetching injection and thermal drive, wherein after the N-type ions are injected, an N + area is formed on the central area of the N + area, the two sides of the N + epitaxial layer and the two sides of the P-epitaxial layer, a P-body area is formed between the two sides of the central area of the N + area and the pressure-resistant oxide layer, the distance L1 between the side of the pressure-resistant oxide layer and the central area of the N + area is equal to the distance L2 between the bottom of the pressure-resistant oxide layer and the bottom of the N + area, and the depth and the thickness of the P-body area are both greater than those of the pressure-resistant oxide layer, so that the pressure-resistant oxide layer is surrounded by the P-body area and the side areas of the N + area;
forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid;
photoetching and injecting the P-body regions at two sides of the polysilicon gate to form an N + source region;
forming device source metal on the upper surface of the joint of the pressure-resistant oxide layer, the polysilicon region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming a dielectric isolation layer among the device source metal, the device drain metal and the polysilicon gate.
7. The method according to claim 6, wherein the forming of the voltage-resistant oxide layer inside the deep trench is specifically: and growing an oxide layer in the deep groove by adopting chlorine-based gas as atmosphere to form a pressure-resistant oxide layer.
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