CN108376708A - Semiconductor devices and preparation method thereof with pressure-resistance structure - Google Patents
Semiconductor devices and preparation method thereof with pressure-resistance structure Download PDFInfo
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- CN108376708A CN108376708A CN201810150711.5A CN201810150711A CN108376708A CN 108376708 A CN108376708 A CN 108376708A CN 201810150711 A CN201810150711 A CN 201810150711A CN 108376708 A CN108376708 A CN 108376708A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 239000013078 crystal Substances 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 239000000243 solution Substances 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 2
- 238000006116 polymerization reaction Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof with pressure-resistance structure, is related to technology of semiconductor chips field, including：N-type substrate, the areas N+, P bodies area, pressure-resistant oxide layer, multi-crystal silicon area, N+ source regions, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and device drain metal.Wherein, pressure-resistant oxide layer is separately positioned on the both sides of the central area in the areas N+, and the side zones with the areas N+ fit respectively, and pressure-resistant oxide layer is spill oxide layer, and multi-crystal silicon area is filled in pressure-resistant oxide layer concave regions.The technical solution alleviates the technical issues of device architecture pressure resistance poor performance of the existing technology, the pressure-resistant performance of device has been effectively ensured, improve the saturation current of semiconductor devices, reduce the conducting resistance of device, efficiently use device area, the production cost for reducing device improves the conduction property of semiconductor devices.
Description
Technical field
The present invention relates to technology of semiconductor chips field, more particularly, to a kind of semiconductor devices with pressure-resistance structure and
Its production method.
Background technology
Currently, MOS device structure includes mainly for source metal, dielectric layer isolation, polycrystalline grid, grid oxic horizon, device
Part P-type body area, device N+ source regions, device N-type epitaxy layer, device N-type substrate and device drain metal.Realizing mistake of the present invention
Cheng Zhong, inventor have found that at least there are the following problems in the prior art：MOS device conducting resistance is big, when break-over of device, electrons
From N-type source, raceway groove, N-type epitaxy layer, N-type substrate is passed through to eventually arrive at drain electrode.To improve device pressure resistance, then N-type
Epitaxial layer has to very thick, thicker N-type epitaxy layer, and the conducting resistance of device will be bigger.To improve device pressure resistance, usually
Terminal pressure-resistance structure can be increased, greatly waste device area.Therefore, there are device architecture pressure resistance poor performances for the prior art
Technical problem.
Invention content
In view of this, the purpose of the present invention is to provide a kind of semiconductor devices with pressure-resistance structure and its making sides
Method, the technical issues of to alleviate device architecture pressure resistance poor performance of the existing technology.
In a first aspect, an embodiment of the present invention provides a kind of semiconductor devices with pressure-resistance structure, including：N-type substrate,
The areas N+, P- bodies area, pressure-resistant oxide layer, multi-crystal silicon area, N+ source regions, grid oxic horizon, polysilicon gate, dielectric layer isolation, device
Source metal and device drain metal；
The areas N+ are the electronics drift region being made of central area, bottom edge area and side zones；
The top of N-type substrate is connect with the bottom edge area in the areas N+, and the inner surface in the areas N+ extends to P- bodies area, pressure-resistant oxygen to central area
Change the both sides that floor is separately positioned on the central area in the areas N+, and the side zones with the areas N+ fit respectively, pressure-resistant oxide layer is spill
Oxide layer, multi-crystal silicon area are filled in pressure-resistant oxide layer concave regions, the upper surface in P- bodies area and pressure-resistant oxide layer connection
Equipped with N+ source regions, grid oxic horizon be covered in N+ source regions, the areas N+, P- bodies area junction upper surface, set above grid oxic horizon
There are polysilicon gate, the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction to be provided with device source metal, N+
The upper surface of the side zones in area be equipped with device drain metal, the upper surface of polysilicon gate and its between device source metal,
Equal level is equipped with buffer layer between device source metal and device drain metal.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the bottom of pressure-resistant oxide layer
The bottom in the areas Bu Yu N+ fits.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the side of pressure-resistant oxide layer
The central area distance L1 in the areas Bian Yu N+, and the bottom of pressure-resistant oxide layer are equal with the bottom distance L2 in the areas N+.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the thickness of pressure-resistant oxide layer
Degree is 0.5 ~ 0.8 μm.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the width of pressure-resistant oxide layer
Degree is 2 ~ 5 μm.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, pressure-resistant oxide layer it is recessed
The depth in shape region is 2 ~ 10 μm.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the areas N+ are that N-type is heavily doped
Miscellaneous area, dopant dose are 1E15 ~ 2E15, and cross-sectional width is 2 ~ 5 μm.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the areas N+ are used by TBI
The PTBI2T electronics drift layers of material polymerization.
Second aspect, an embodiment of the present invention provides a kind of production method of the semiconductor devices with pressure-resistance structure, packets
It includes：
N-type substrate is provided, N+ epitaxial layers are formed in the upper surface of N-type substrate, P- epitaxial layers are formed in the upper surface of N+ epitaxial layers,
Surface planarisation is carried out after extension；
Deep trench is formed in the both sides of P- epitaxial layers；
Pressure-resistant oxide layer is formed inside deep trench, pressure-resistant oxide layer is spill oxide layer, in the concave regions of pressure-resistant oxide layer
Inside filling forms multi-crystal silicon area；
It is driven by photoetching injection and heat and injects N-type ion, drive in the central area in the rear areas N+, the both sides of N+ epitaxial layers and P- epitaxial layers
Side forms the areas N+, and P- bodies area is formed between the central area both sides in the areas N+ and pressure-resistant oxide layer；
Grid oxic horizon is formed in the junction upper surface in the areas N+ and P- bodies area, deposits to form polycrystalline on the surface of grid oxic horizon
Silicon gate；
Photoetching is carried out in the both sides P- bodies area of polysilicon gate to inject to form N+ source regions；
Device source metal, the side in the areas N+ are formed in the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction
The upper surface in area forms device drain metal, the horizontal paving between device source metal, device drain metal and polysilicon gate
If forming buffer layer.
Further, in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, in depth
Trench interiors form pressure-resistant oxide layer：Oxide layer growth is carried out as atmosphere using chlorine-based gas inside deep trench,
Form pressure-resistant oxide layer.
The embodiment of the present invention brings following advantageous effect：Partly the leading with pressure-resistance structure that the embodiment of the present invention is provided
Body device and its manufacturing method, including：N-type substrate, the areas N+, P- bodies area, pressure-resistant oxide layer, multi-crystal silicon area, N+ source regions, grid oxygen
Change layer, polysilicon gate, dielectric layer isolation, device source metal and device drain metal.The areas N+ be by central area, bottom edge area and
The electronics drift region of side zones composition.The top of N-type substrate is connect with the bottom edge area in the areas N+, and the inner surface in the areas N+ prolongs to central area
It stretches for P- bodies area, pressure-resistant oxide layer is separately positioned on the both sides of the central area in the areas N+, and the side zones with the areas N+ fit respectively,
Pressure-resistant oxide layer is spill oxide layer, and multi-crystal silicon area is filled in pressure-resistant oxide layer concave regions, the upper surface in P- bodies area with it is resistance to
Press oxide layer connection to be equipped with N+ source regions, grid oxic horizon be covered in N+ source regions, the areas N+, P- bodies area junction upper surface,
Polysilicon gate is equipped with above grid oxic horizon, the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction is provided with
The upper surface of device source metal, the side zones in the areas N+ is equipped with device drain metal, the upper surface of polysilicon gate and its and device
Equal level is equipped with buffer layer between part source metal, between device source metal and device drain metal.The technical side
Case is combined by using pressure-resistant oxide layer with polysilicon filling technique, and the pressure-resistant performance of device has been effectively ensured, has improved simultaneously
The saturation current of semiconductor devices, reduces the conducting resistance of device, efficiently uses device area, reduce the production of device
Cost improves the conduction property of semiconductor devices, and the technology for alleviating device architecture pressure resistance poor performance of the existing technology is asked
Topic.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate
Appended attached drawing, is described in detail below.
Description of the drawings
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, in being described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, other drawings may also be obtained based on these drawings.
Fig. 1 is the sectional view of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure；
Fig. 2 is the flow chart of the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure；
Fig. 3 is the product of step S1 in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
Schematic diagram；
Fig. 4 is the product of step S2 in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
Schematic diagram；
Fig. 5 is the product of step S3 in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
Schematic diagram；
Fig. 6 is the product of step S4 in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
Schematic diagram；
Fig. 7 is step S5 and step in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
The product schematic diagram of S6.
Icon：
1-N type substrates；The areas 2-N+；3- pressure resistance oxide layers；The multi-crystal silicon areas 4-；5-N+ source regions；6-P- bodies area；7- polysilicon gates；
8- grid oxic horizons；9- dielectric layers are isolated；10- device source metals；11- device drain metals.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing to the present invention
Technical solution be clearly and completely described, it is clear that described embodiments are some of the embodiments of the present invention, rather than
Whole embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, shall fall within the protection scope of the present invention.
Currently, MOS device structure includes mainly for source metal, dielectric layer isolation, polycrystalline grid, grid oxic horizon, device
Part P-type body area, device N+ source regions, device N-type epitaxy layer, device N-type substrate and device drain metal.Realizing mistake of the present invention
Cheng Zhong, inventor have found that at least there are the following problems in the prior art：MOS device conducting resistance is big, when break-over of device, electrons
From N-type source, raceway groove, N-type epitaxy layer, N-type substrate is passed through to eventually arrive at drain electrode.To improve device pressure resistance, then N-type
Epitaxial layer has to very thick, thicker N-type epitaxy layer, and the conducting resistance of device will be bigger.To improve device pressure resistance, usually
Terminal pressure-resistance structure can be increased, greatly waste device area, be based on this, it is provided in an embodiment of the present invention a kind of with pressure resistance
The semiconductor devices and its manufacturing method of structure, can be effectively ensured the pressure-resistant performance of device, while improve semiconductor devices
Saturation current reduces the conducting resistance of device.
Embodiment one：
Referring to Fig. 1, the sectional view of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure.The embodiment of the present invention carries
A kind of semiconductor devices with pressure-resistance structure supplied, including：N-type substrate 1, the areas N+ 2, P- bodies area 6, pressure-resistant oxide layer 3, polycrystalline
Silicon area 4, N+ source regions 5, grid oxic horizon 8, polysilicon gate 7, dielectric layer isolation 9, device source metal 10 and device drain gold
Belong to 11.Wherein, pressure-resistant oxide layer constitutes the pressure-resistance structure of semiconductor devices with multi-crystal silicon area.The areas N+ are by central area, bottom edge
The electronics drift region in area and side zones composition.The cross section of side zones is " mouth " font, and the cross section of central area is line-styled,
Center positioned at side zones, bottom edge area are square, and are located at bottom device.
The top of N-type substrate is connect with the bottom edge area in the areas N+, and the inner surface in the areas N+ extends to P- bodies area to central area, pressure resistance
Oxide layer is separately positioned on the both sides of the central area in the areas N+, and the side zones with the areas N+ fit respectively, and pressure-resistant oxide layer is recessed
Shape oxide layer, multi-crystal silicon area are filled in pressure-resistant oxide layer concave regions, further, provided in an embodiment of the present invention with resistance to
In the semiconductor devices of laminated structure, the thickness of pressure-resistant oxide layer is 0.5 ~ 0.8 μm, ensure that the pressure-resistant performance of device,
The saturation current for improving semiconductor devices simultaneously, reduces the conducting resistance of device, improves the conduction property of semiconductor devices,
And built-in pressure-resistant oxide layer and the pressure-resistance structure of multi-crystal silicon area composition are effectively utilized device area, reduce the life of device
Produce cost.
In semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, pressure-resistant oxide layer is formed by concave groove
Width be 2 ~ 5 μm.And the setting of above-mentioned pressure-resistant oxide layer can there are many selection modes, such as：
Mode one, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the bottom of pressure-resistant oxide layer and N+
The bottom in area fits.The pressure resistance of device at this time depends on the thickness of pressure-resistant oxide layer and side and the N+ of pressure-resistant oxide layer
The distance of the central area in area increases distance and thickness, ensure that device has enough depleted region thickness to undertake pressure resistance.
Mode two, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the side of pressure-resistant oxide layer
With the central area distance L1 in the areas N+, the bottom of pressure-resistant oxide layer and the bottom distance L2 in the areas N+, L1 is equal with L2, ensures device
Enough backward voltages can be undertaken when high pressure is reverse-biased, to ensure that the charge balance of device inside, to protect device
It avoids puncturing.Specifically, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the spill of pressure-resistant oxide layer
The depth in region is 2 ~ 10 μm.
In semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, upper surface and the pressure resistance in P- bodies area aoxidize
Layer connection be equipped with N+ source regions, grid oxic horizon be covered in N+ source regions, the areas N+, P- bodies area junction upper surface, grid oxygen
Change and be equipped with polysilicon gate above layer, the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction is provided with device source
Pole metal, the upper surfaces of the side zones in the areas N+ are equipped with device drain metal, the upper surface of polysilicon gate and its with device source electrode
Equal level is equipped with buffer layer between metal, between device source metal and device drain metal.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the areas N+ are N-type heavy doping
Area, dopant dose are 1E15 ~ 2E15, and cross-sectional width is 2 ~ 5 μm.Wherein, the unit of dopant dose be ion number/square li
Rice.
Further, in the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, the areas N+ are used by TBI materials
Expect the PTBI2T electronics drift layers of polymerization.
The semiconductor devices with pressure-resistance structure that the embodiment of the present invention is provided, including：N-type substrate, the areas N+, P- bodies
Area, pressure-resistant oxide layer, multi-crystal silicon area, N+ source regions, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and
Device drain metal.The areas N+ are the electronics drift region being made of central area, bottom edge area and side zones.The top of N-type substrate and N+
The bottom edge area in area connects, and the inner surface in the areas N+ extends to P- bodies area to central area, and pressure-resistant oxide layer is separately positioned in the areas N+
The both sides in area are entreated, and the side zones with the areas N+ fit respectively, pressure-resistant oxide layer is spill oxide layer, and multi-crystal silicon area is filled in resistance to
It presses in oxide layer concave regions, the upper surface in P- bodies area is equipped with N+ source regions with pressure-resistant oxide layer connection, and grid oxic horizon covers
Be placed on N+ source regions, the areas N+, P- bodies area junction upper surface, be equipped with polysilicon gate above grid oxic horizon, pressure-resistant oxide layer,
The upper surface of multi-crystal silicon area and N+ source regions junction is provided with device source metal, and the upper surface of the side zones in the areas N+ is equipped with device
Drain metal, the upper surface of polysilicon gate and its between device source metal, device source metal and device drain metal
Between level be equipped with buffer layer.The technical solution is mutually tied by using pressure-resistant oxide layer and polysilicon filling technique
It closes, the pressure-resistant performance of device has been effectively ensured, while improving the saturation current of semiconductor devices, has reduced the electric conduction of device
Resistance, efficiently uses device area, reduces the production cost of device, improve the conduction property of semiconductor devices, alleviate existing
Existing for technology the technical issues of device architecture pressure resistance poor performance.
Embodiment two：
A kind of manufacturing method of semiconductor devices with pressure-resistance structure provided in an embodiment of the present invention, includes the following steps：
Step S1：N-type substrate is provided, N+ epitaxial layers are formed in the upper surface of N-type substrate, P- is formed in the upper surface of N+ epitaxial layers
Epitaxial layer carries out surface planarisation after extension.Referring to Fig. 3, the semiconductor device provided in an embodiment of the present invention with pressure-resistance structure
In the production method of part, the product schematic diagram of step S1.
Step S2：Deep trench is formed in the both sides of P- epitaxial layers.It is provided in an embodiment of the present invention that there is pressure resistance referring to Fig. 4
In the production method of the semiconductor devices of structure, the product schematic diagram of step S2.
Step S3：Pressure-resistant oxide layer is formed inside deep trench, pressure-resistant oxide layer is spill oxide layer, in pressure-resistant oxide layer
Concave regions inside filling form multi-crystal silicon area.Referring to Fig. 5, the semiconductor provided in an embodiment of the present invention with pressure-resistance structure
In the production method of device, the product schematic diagram of step S3.Further, provided in an embodiment of the present invention with pressure-resistance structure
In semiconductor devices, the thickness of pressure-resistant oxide layer is 0.5 ~ 0.8 μm, ensure that the pressure-resistant performance of device, improves simultaneously
The saturation current of semiconductor devices, reduces the conducting resistance of device, improves the conduction property of semiconductor devices, and built-in
The pressure-resistance structure of pressure-resistant oxide layer and multi-crystal silicon area composition be effectively utilized device area, reduce the production cost of device.
In the production method of semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, pressure-resistant oxide layer is formed by concave
The width of slot is 2 ~ 5 μm.And the setting of above-mentioned pressure-resistant oxide layer can there are many selection modes, such as：
Mode one, in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, pressure-resistant oxide layer
The bottom of bottom and the areas N+ fit.The pressure resistance of device at this time depends on the thickness of pressure-resistant oxide layer and pressure-resistant oxide layer
Side at a distance from the central area in the areas N+, increase distance and thickness, ensure that device has enough depleted region thickness to hold
Load pressure resistance.
Mode two, in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, pressure-resistant oxygen
Change the central area distance L1 of the side and the areas N+ of floor, the bottom of pressure-resistant oxide layer and the bottom distance L2 in the areas N+, L1 and L2 phases
Deng, ensure that device can undertake enough backward voltages when high pressure is reverse-biased, to ensure that the charge balance of device inside, from
And device is protected to avoid puncturing.Specifically, the depth of the concave regions of pressure-resistant oxide layer is 2 ~ 10 μm.
Step S4：It is driven by photoetching injection and heat and injects N-type ion, drive in the central area, N+ epitaxial layers and P- in the rear areas N+
The two sides of epitaxial layer form the areas N+, and P- bodies area is formed between the central area both sides in the areas N+ and pressure-resistant oxide layer.The side in the areas N+
The cross section in area is " mouth " font；The cross section of central area is line-styled, is located at the center of side zones；Bottom edge area is pros
Shape is located at bottom device.Referring to Fig. 6, the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
In, the product schematic diagram of step S4.The areas N+ use the PTBI2T electronics drift layers being polymerize by TBI materials.Wherein, the areas N+ are N-type
Heavily doped region, dopant dose are 1E15 ~ 2E15, and cross-sectional width is 2 ~ 5 μm.Wherein, the unit of dopant dose is ion number/flat
Square centimetre.
Step S5：Grid oxic horizon is formed in the junction upper surface in the areas N+ and P- bodies area, on the surface of grid oxic horizon
Deposition forms polysilicon gate.Wherein, the width of grid oxic horizon and the width of polysilicon gate are equal.
Step S6：Photoetching is carried out in the both sides P- bodies area of polysilicon gate to inject to form N+ source regions.Referring to Fig. 7, the present invention
In the production method for the semiconductor devices with pressure-resistance structure that embodiment provides, the product schematic diagram of step S5 and step S6
（N-type substrate is not shown）.
Step S7：Device source metal is formed in the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction,
The upper surface of the side zones in the areas N+ forms device drain metal, in device source metal, device drain metal and polysilicon gate
Between horizontal be laid with form buffer layer, as Fig. 1 semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure
Sectional view in product.Pressure-resistant oxide layer constitutes the pressure-resistance structure of semiconductor devices, the top of N-type substrate with multi-crystal silicon area
It is connect with the bottom edge area in the areas N+, the inner surface in the areas N+ extends to P- bodies area to central area, and pressure-resistant oxide layer is separately positioned on the areas N+
Central area both sides, and the side zones with the areas N+ fit respectively, and pressure-resistant oxide layer is spill oxide layer, multi-crystal silicon area filling
In pressure-resistant oxide layer concave regions, the upper surface in P- bodies area is equipped with N+ source regions, gate oxidation with pressure-resistant oxide layer connection
Floor be covered in N+ source regions, the areas N+, P- bodies area junction upper surface, polysilicon gate, pressure-resistant oxygen are equipped with above grid oxic horizon
Change layer, multi-crystal silicon area and the upper surface of N+ source regions junction and be provided with device source metal, the upper surface of the side zones in the areas N+ is set
There is a device drain metal, the upper surface of polysilicon gate and its between device source metal, the leakage of device source metal and device
Level is equipped with buffer layer between the metal of pole.
Further, in the production method of the semiconductor devices provided in an embodiment of the present invention with pressure-resistance structure, step
The pressure-resistant oxide layer that formed inside deep trench in S3 is specially：Oxygen is carried out as atmosphere using chlorine-based gas inside deep trench
Change layer growth, forms pressure-resistant oxide layer, which eliminates metal ion and movable charge in pressure-resistant oxide layer, into one
Step ensure that the conduction property of device.
The manufacturing method for the semiconductor devices with pressure-resistance structure that the embodiment of the present invention is provided provides N-type lining first
Bottom forms N+ epitaxial layers in the upper surface of N-type substrate, forms P- epitaxial layers in the upper surface of N+ epitaxial layers, table is carried out after extension
Face planarizes.Secondly, deep trench is formed in the both sides of P- epitaxial layers；Pressure-resistant oxide layer, pressure resistance oxidation are formed inside deep trench
Layer is spill oxide layer, is filled inside the concave regions of pressure-resistant oxide layer and forms multi-crystal silicon area.Again, by photoetching injection and
Heat drives injection N-type ion, drives in the central area in the rear areas N+, the two sides areas formation N+ of N+ epitaxial layers and P- epitaxial layers, the areas N+
P- bodies area is formed between central area both sides and pressure-resistant oxide layer.Then, grid are formed in the junction upper surface in the areas N+ and P- bodies area
Pole oxide layer deposits to form polysilicon gate on the surface of grid oxic horizon；Light is carried out in the both sides P- bodies area of polysilicon gate
It carves injection and forms N+ source regions.Finally, device source electrode is formed in the upper surface of pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction
Metal forms device drain metal, in device source metal, device drain metal and polycrystalline in the upper surface of the side zones in the areas N+
Horizontal be laid with forms buffer layer between silicon gate.The technical solution is by using pressure-resistant oxide layer and polysilicon filling technique
It is combined, the pressure-resistant performance of device has been effectively ensured, while improving the saturation current of semiconductor devices, reduce leading for device
Be powered resistance, efficiently uses device area, reduces the production cost of device, improves the conduction property of semiconductor devices, alleviate
The technical issues of device architecture pressure resistance poor performance of the existing technology.
In the description of the embodiment of the present invention unless specifically defined or limited otherwise, term " installation ", " connects " connected "
Connect " it shall be understood in a broad sense, for example, it may be being fixedly connected, it may be a detachable connection, or be integrally connected；It can be machine
Tool connects, and can also be electrical connection；It can be directly connected, can also can be indirectly connected through an intermediary two members
Connection inside part.For the ordinary skill in the art, it can understand above-mentioned term in the present invention with concrete condition
Concrete meaning.
In the description of the present invention, it should be noted that term "center", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, merely to
Convenient for the description present invention and simplify description, do not indicate or imply the indicated device or element must have a particular orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" third " is used for description purposes only, and is not understood to indicate or imply relative importance.
Finally it should be noted that：Embodiment described above, only specific implementation mode of the invention, to illustrate the present invention
Technical solution, rather than its limitations, scope of protection of the present invention is not limited thereto, although with reference to the foregoing embodiments to this hair
It is bright to be described in detail, it will be understood by those of ordinary skill in the art that：Any one skilled in the art
In the technical scope disclosed by the present invention, it can still modify to the technical solution recorded in previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of technical solution of the embodiment of the present invention, should all cover the protection in the present invention
Within the scope of.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of semiconductor devices with pressure-resistance structure, which is characterized in that including：N-type substrate, the areas N+, P- bodies area, pressure-resistant oxygen
Change layer, multi-crystal silicon area, N+ source regions, grid oxic horizon, polysilicon gate, dielectric layer isolation, device source metal and device drain
Metal；
The areas N+ are the electronics drift region being made of central area, bottom edge area and side zones；
The top of the N-type substrate is connect with the bottom edge area in the areas N+, and the inner surface in the areas N+ extends to institute to central area
The areas ShuP-Ti, the pressure resistance oxide layer are separately positioned on the both sides of the central area in the areas N+, and the side with the areas N+ respectively
Border area fits, and the pressure resistance oxide layer is spill oxide layer, and the multi-crystal silicon area is filled in the pressure-resistant oxide layer spill area
In domain, the upper surface in P- bodies area is equipped with the N+ source regions, the grid oxic horizon with the pressure-resistant oxide layer connection
Be covered in the N+ source regions, the areas N+, P- bodies area junction upper surface, be equipped with the polysilicon gate above the grid oxic horizon
Pole, the pressure resistance oxide layer, multi-crystal silicon area and the upper surface of N+ source regions junction are provided with device source metal, the N+
The upper surface of the side zones in area is golden equipped with device drain metal, the upper surface of the polysilicon gate and its with the device source electrode
Equal level is equipped with the buffer layer between category, between the device source metal and device drain metal.
2. semiconductor devices according to claim 1, which is characterized in that the bottom and the areas N+ of the pressure resistance oxide layer
Bottom fit.
3. semiconductor devices according to claim 1, which is characterized in that the side and the areas N+ of the pressure resistance oxide layer
Central area distance L1 and the pressure-resistant oxide layer bottom it is equal with the bottom distance L2 in the areas N+.
4. semiconductor devices according to claim 1, which is characterized in that the thickness of the pressure resistance oxide layer is 0.5 ~ 0.8
μm。
5. semiconductor devices according to claim 1, which is characterized in that the width of the pressure resistance oxide layer is 2 ~ 5 μm.
6. semiconductor devices according to claim 3, which is characterized in that the depth of the concave regions of the pressure resistance oxide layer
It is 2 ~ 10 μm.
7. semiconductor devices according to claim 1, which is characterized in that the areas N+ are N-type heavily doped region, dopant dose
For 1E15 ~ 2E15, cross-sectional width is 2 ~ 5 μm.
8. semiconductor devices according to claim 1, which is characterized in that the areas N+ are used to be polymerize by TBI materials
PTBI2T electronics drift layers.
9. a kind of production method of the semiconductor devices with pressure-resistance structure, which is characterized in that including：
N-type substrate is provided, N+ epitaxial layers is formed in the upper surface of the N-type substrate, is formed outside P- in the upper surface of N+ epitaxial layers
Prolong layer, surface planarisation is carried out after extension；
Deep trench is formed in the both sides of P- epitaxial layers；
Pressure-resistant oxide layer is formed inside the deep trench, the pressure resistance oxide layer is spill oxide layer, in the pressure resistance oxidation
Filling forms multi-crystal silicon area inside the concave regions of layer；
It is driven by photoetching injection and heat and injects N-type ion, drive in the central area in the rear areas N+, the both sides of N+ epitaxial layers and P- epitaxial layers
Side forms the areas N+, and P- bodies area is formed between the central area both sides in the areas N+ and pressure-resistant oxide layer；
Grid oxic horizon is formed in the junction upper surface in the areas N+ and P- bodies area, is deposited on the surface of grid oxic horizon
Form polysilicon gate；
The P- bodies area described in the both sides of polysilicon gate carries out photoetching and injects to form N+ source regions；
Device source metal is formed in the upper surface of the pressure-resistant oxide layer, multi-crystal silicon area and N+ source regions junction, in institute
The upper surface for stating the side zones in the areas N+ forms device drain metal, in the device source metal, device drain metal and polycrystalline
Horizontal be laid with forms buffer layer between silicon gate.
10. manufacturing method according to claim 9, which is characterized in that described to form pressure-resistant oxygen inside the deep trench
Changing layer is specially：Oxide layer growth is carried out as atmosphere using chlorine-based gas inside the deep trench, forms pressure-resistant oxide layer.
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| CN110212017A (en) * | 2019-05-15 | 2019-09-06 | 电子科技大学 | A kind of lateral resistance to pressure area of the superjunction trough of belt with resistive field plate |
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