CN108365010B - VDMOS device with super junction structure and manufacturing method thereof - Google Patents
VDMOS device with super junction structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a VDMOS device with a super junction structure and a manufacturing method thereof, relating to the technical field of semiconductor integrated circuits and comprising the following steps: the device comprises an N-type substrate, an N + region, a P-body region, a PN alternating super junction region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, device source electrode metal and device drain electrode metal. The inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super-junction regions are positioned on two sides of the central region of the N + region and between the N + region and the P-body region, and an N + source region is arranged at the connection position of the upper surface of the P-body region and the PN alternating super-junction regions. According to the technical scheme, the PN alternating super junction region with the multilayer structure is adopted, the voltage withstanding capability in the unit area of the VDMOS device is improved, the highly-doped N + region is introduced into the epitaxial layer at the interval between the drain electrode and the source electrode of the traditional MOS device, the resistivity of the epitaxial layer is reduced, the on-resistance of the VDMOS device is further reduced, and the technical problems of poor structure voltage withstanding degree and large on-resistance in the prior art are further solved.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a VDMOS device with a super junction structure and a manufacturing method thereof.
Background
The vertical double-diffused metal-oxide-semiconductor transistor has the advantages of a bipolar transistor and a common MOS device, and the VDMOS is an ideal power device no matter in switching application or linear application. The VDMOS is mainly used for motor speed regulation, inverters, uninterrupted power supplies, electronic switches, high-fidelity acoustics, automobile electric appliances, electronic ballasts and the like. The VDMOS is classified into an enhancement type VDMOS and a depletion type VDMOS. With the development of the semiconductor design field and the semiconductor process field, the current VDMOS device has been developed toward the low-cost and high-performance field, and how to compress the cost as much as possible on the premise of ensuring high performance becomes a main subject of each design company and foundry.
At present, the structure of the MOS device mainly includes source metal, dielectric layer isolation, a poly-crystalline gate, a gate oxide layer, a device P-type body region, a device N + source region, a device N-type epitaxial layer, a device N-type substrate, and device drain metal. In the process of implementing the invention, the inventor finds that at least the following problems exist in the prior art: the MOS device has large on-resistance, and when the device is turned on, electrons start from the N-type source electrode, pass through the channel, the N-type epitaxial layer and the N-type substrate and finally reach the drain electrode. In order to increase the device breakdown voltage, the N-type epitaxial layer must be thick, and the thicker the N-type epitaxial layer, the greater the on-resistance of the device. If the device withstand voltage is to be improved, a terminal withstand voltage structure is usually added, and the area of the device is greatly wasted. Therefore, the prior art has the technical problems of poor withstand voltage degree and large on-resistance of the device structure.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a VDMOS device having a super junction structure and a manufacturing method thereof, so as to alleviate the technical problems of poor withstand voltage degree and large on-resistance of the device structure in the prior art.
In a first aspect, an embodiment of the present invention provides a VDMOS device having a super junction structure, including: the device comprises an N-type substrate, an N + region, a P-body region, a PN alternating super junction region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, device source electrode metal and device drain electrode metal;
the N + region is an electronic drift region consisting of a central region, a bottom edge region and a side edge region;
the upper part of the N-type substrate is connected with a bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super junction region is positioned on two sides of the central region of the N + region and between the N + region and the P-body region, the N + source region is arranged at the position where the upper surface of the P-body region is connected with the PN alternating super junction region, the grid oxide layer covers the upper surfaces of the connecting positions of the N + source region, the N + region and the P-body region, a polysilicon grid is arranged above the grid oxide layer, device source metal is arranged on the upper surface of the connecting position of the PN alternating super junction region and the N + source region, device drain metal is arranged on the upper surface of the side edge region of the N + region, and dielectric layer isolation is horizontally laid between the upper surface of the polysilicon grid and the device source metal and between the device source metal and the device drain metal;
the PN alternating super junction region is formed by alternately arranging P + layers and N + layers at intervals in the transverse direction, and the upper surface and the lower surface of the PN alternating super junction region are both the P + layers.
Further, in the VDMOS device having the super junction structure provided in the embodiment of the present invention, the PN alternating super junction region is formed by three P + layers and two N + layers which are arranged laterally at intervals, and the upper and lower surfaces are both P + layers;
the P + layer is respectively a first P + layer, a second P + layer and a third P + layer from top to bottom, the N + layer is respectively a first N + layer and a second N + layer, the first N + layer is positioned between the first P + layer and the second P + layer, and the second N + layer is positioned between the second P + layer and the third P + layer.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the doping concentrations of the first P + layer, the second P + layer and the third P + layer decrease in sequence, the doping amount of the first P + layer is 4E 15-5E 15, the doping amount of the second P + layer is 3E 15-4E 15, and the doping amount of the third P + layer is 2E 15-3E 15.
Further, in the VDMOS device having the super junction structure provided by the embodiment of the present invention, the dopant amounts of the first N + layer and the second N + layer are both 2E 15.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the section width is 2-5 μm.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the cross-sectional width of the PN alternating super junction region is 5-10 μm.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the present invention, the thickness of each P + layer or N + layer in the PN alternating super junction region is 2 to 3 μm.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a VDMOS device having a super junction structure, including:
providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the epitaxy;
forming deep grooves on two sides of the P-epitaxial layer, wherein the bottoms of the deep grooves extend to the upper surface of the N + epitaxial layer;
forming a PN alternating super junction region in the deep trench;
injecting N-type ions through photoetching injection and thermal drive, forming N + areas at the central area of the N + area, the two side edges of the N + epitaxial layer and the P-epitaxial layer after the N + areas are injected, and forming a P-body area between the two sides of the central area of the N + area and the PN alternating super junction area;
forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid;
photoetching and injecting P-body regions at two sides of the polysilicon gate to form an N + source region;
forming device source metal on the upper surface of the connecting part of the PN alternating super junction region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming dielectric layer isolation among the device source metal, the device drain metal and the polysilicon gate.
Further, in the method for manufacturing a VDMOS device having a super junction structure provided in the embodiment of the present invention, after performing surface planarization after the epitaxy, the method further includes: a rapid annealing step;
the temperature range of the rapid annealing step is 1050-1100 ℃, and the atmosphere is hydrogen or nitrogen.
The embodiment of the invention has the following beneficial effects: the VDMOS device with the super junction structure and the manufacturing method thereof provided by the embodiment of the invention comprise the following steps: the device comprises an N-type substrate, an N + region, a P-body region, a PN alternating super junction region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, device source electrode metal and device drain electrode metal. The N + region is an electron drift region composed of a central region, a bottom edge region and side edge regions. The upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super junction region is positioned on two sides of the central region of the N + region and between the N + region and the P-body region, the N + source region is arranged at the position where the upper surface of the P-body region is connected with the PN alternating super junction region, the grid oxide layer covers the upper surfaces of the connecting positions of the N + source region, the N + region and the P-body region, a polycrystalline silicon grid is arranged above the grid oxide layer, device source metal is arranged on the upper surface of the connecting position of the PN alternating super junction region and the N + source region, device drain metal is arranged on the upper surface of the side edge region of the N + region, and dielectric layer isolation is horizontally laid between the upper surface of the polycrystalline silicon grid and the device source metal and between the device drain metal. The PN alternating super junction region is formed by alternately arranging P + layers and N + layers at intervals in the transverse direction, and the upper surface and the lower surface of the PN alternating super junction region are both the P + layers. This technical scheme is through adopting multilayer structure's PN super junction area in turn, the withstand voltage ability in VDMOS device unit area has been improved, with the inside highly doped N + district that introduces of spaced epitaxial layer between the drain electrode of traditional MOS device and the source electrode, the resistivity of epitaxial layer has been reduced, and then saturation current has been improved, VDMOS device on-resistance has been reduced, the structure volume of device has been reduced when having guaranteed device voltage resistance, the manufacturing cost of device has been reduced, and then it is poor to have alleviated the structure withstand voltage degree that prior art exists, the technical problem that on-resistance is big.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a cross-sectional view of a VDMOS device having a super junction structure according to an embodiment of the present invention;
fig. 2 is a top view of a VDMOS device having a super junction structure according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing a VDMOS device having a super junction structure according to an embodiment of the present invention;
fig. 4 is a schematic product diagram of step S1 in the method for manufacturing a VDMOS device having a super junction structure according to the embodiment of the present invention;
fig. 5 is a schematic product diagram of step S2 in a method for manufacturing a VDMOS device having a super junction structure according to an embodiment of the present invention;
fig. 6 is a schematic product diagram of step S3 in a method for manufacturing a VDMOS device having a super junction structure according to an embodiment of the present invention;
fig. 7 is a schematic product diagram of step S4 in the method for manufacturing a VDMOS device having a super junction structure according to the embodiment of the present invention;
fig. 8 is a schematic product diagram of steps S5 and S6 in the method for manufacturing a VDMOS device having a super junction structure according to the embodiment of the present invention.
Icon:
a 1-N + region; 2 a-a first P + layer; 2 b-a second P + layer; 2 c-a third P + layer; 3 a-a first N + layer; 3 b-a second N + layer; a 4-N + source region; a 5-P-body region; 6-polysilicon gate; 7-a gate oxide layer; 8-dielectric layer isolation; 9-device source metal; 10-device drain metal.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
At present, the structure of the MOS device mainly includes source metal, dielectric layer isolation, a poly-crystalline gate, a gate oxide layer, a device P-type body region, a device N + source region, a device N-type epitaxial layer, a device N-type substrate, and device drain metal. The traditional MOS device has large on-resistance, and when the device is turned on, electrons start from an N-type source electrode, pass through a channel, an N-type epitaxial layer and an N-type substrate and finally reach a drain electrode. In order to increase the device breakdown voltage, the N-type epitaxial layer must be thick, and the thicker the N-type epitaxial layer, the greater the on-resistance of the device. Based on the VDMOS device with the super junction structure and the manufacturing method thereof, the voltage withstanding capability of the VDMOS device in unit area can be improved, the saturation current is improved, and the on-resistance of the VDMOS device is reduced.
The first embodiment is as follows:
referring to fig. 1 and fig. 2, embodiments of the present invention provide a cross-sectional view and a top view of a VDMOS device having a super junction structure. The VDMOS device with the super junction structure provided by the embodiment of the invention comprises: an N-type substrate (not shown in the figure), an N + region 1, a P-body region 5, a PN alternating super junction region, an N + source region 4, a grid oxide layer 7, a polysilicon grid 6, a dielectric layer isolation 8, a device source electrode metal 9 and a device drain electrode metal 10. The N + region is an electron drift region composed of a central region, a bottom edge region and a side edge region. The cross section of the side area is square, the cross section of the central area is square, and the central area is positioned in the center of the side area, and the bottom area is square and positioned at the bottom of the device. The bottom edge region is a highly doped epitaxial layer, the side edge region is a longitudinal N + region formed by implantation and diffusion, and further, the epitaxial layer concentration of the bottom edge region can be higher than that of the longitudinal implantation diffusion formed side edge region. According to the technical scheme, the highly-doped N + region is introduced into the epitaxial layer at the interval between the drain electrode and the source electrode of the traditional MOS device, so that the resistivity of the epitaxial layer is reduced, and the on-resistance of the VDMOS device is further reduced.
The upper part of the N-type substrate is connected with a bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super junction region is positioned on two sides of the central region of the N + region and between the N + region and the P-body region, the N + source region is arranged at the joint of the upper surface of the P-body region and the PN alternating super junction region, the grid oxide layer covers the upper surface of the joint of the N + source region, the N + region and the P-body region, a polysilicon grid is arranged above the grid oxide layer, and the width of the grid oxide layer is equal to that of the polysilicon grid. Device source electrode metal is arranged on the upper surface of the joint of the PN alternating super junction region and the N + source region, device drain electrode metal is arranged on the upper surface of the side region of the N + region, and dielectric layers are horizontally laid between the upper surface of the polysilicon gate and the device source electrode metal and between the device source electrode metal and the device drain electrode metal for isolation.
The PN alternating super junction region is formed by alternately arranging P + layers and N + layers at intervals in the transverse direction, and the upper surface and the lower surface of the PN alternating super junction region are both the P + layers.
Further, in the VDMOS device having the super junction structure provided in the embodiment of the present invention, the PN alternating super junction region is formed by three P + layers and two N + layers which are arranged laterally at intervals, and the upper and lower surfaces are both P + layers.
The P + layer is respectively a first P + layer 2a, a second P + layer 2b and a third P + layer 2c from top to bottom, the N + layer is respectively a first N + layer 3a and a second N + layer 3b, the first N + layer is positioned between the first P + layer and the second P + layer, and the second N + layer is positioned between the second P + layer and the third P + layer.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the doping concentrations of the first P + layer, the second P + layer and the third P + layer decrease in sequence, the doping amount of the first P + layer is 4E 15-5E 15, the doping amount of the second P + layer is 3E 15-4E 15, and the doping amount of the third P + layer is 2E 15-3E 15. Wherein the unit of the doping dose is the number of ions per square centimeter.
Further, in the VDMOS device having the super junction structure provided by the embodiment of the present invention, the dopant amounts of the first N + layer and the second N + layer are both 2E 15.
Further, in the VDMOS device having the super junction structure provided by the embodiment of the present invention, the N + region employs a PTBI2T electron drift layer polymerized by a TBI material.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the section width is 2-5 μm.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the invention, the cross-sectional width of the PN alternating super junction region is 5-10 μm.
Further, in the VDMOS device with the super junction structure provided by the embodiment of the present invention, the thickness of each P + layer or N + layer in the PN alternating super junction region is 2 to 3 μm.
The VDMOS device with the super junction structure provided by the embodiment of the invention comprises: the device comprises an N-type substrate, an N + region, a P-body region, a PN alternating super junction region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, device source electrode metal and device drain electrode metal. The N + region is an electron drift region composed of a central region, a bottom edge region and side edge regions. The upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super junction region is positioned on two sides of the central region of the N + region and between the N + region and the P-body region, the N + source region is arranged at the position where the upper surface of the P-body region is connected with the PN alternating super junction region, the grid oxide layer covers the upper surfaces of the connecting positions of the N + source region, the N + region and the P-body region, a polycrystalline silicon grid is arranged above the grid oxide layer, device source metal is arranged on the upper surface of the connecting position of the PN alternating super junction region and the N + source region, device drain metal is arranged on the upper surface of the side edge region of the N + region, and dielectric layer isolation is horizontally laid between the upper surface of the polycrystalline silicon grid and the device source metal and between the device drain metal. The PN alternating super junction region is formed by alternately arranging P + layers and N + layers at intervals in the transverse direction, and the upper surface and the lower surface of the PN alternating super junction region are both the P + layers. According to the technical scheme, through the adoption of the PN alternating super junction region with the multilayer structure, the voltage withstanding capability in unit area of the VDMOS device is improved, the saturation current is improved, the conduction resistance of the VDMOS device is reduced, the structural volume of the device is reduced while the voltage withstanding performance of the device is ensured, the production cost of the device is reduced, and the technical problems of poor structure voltage withstanding degree and large conduction resistance in the prior art are further solved.
Example two:
referring to fig. 3, a flowchart of a method for manufacturing a VDMOS device having a super junction structure according to an embodiment of the present invention is provided. The embodiment of the invention provides a manufacturing method of a VDMOS device with a super junction structure, which comprises the following steps:
step S1: providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after epitaxy. Referring to fig. 4, in the method for manufacturing a VDMOS device having a super junction structure provided by the embodiment of the present invention, a product schematic diagram of step S1 is shown.
Step S2: and forming deep grooves on two sides of the P-epitaxial layer, wherein the bottoms of the deep grooves extend to the upper surface of the N + epitaxial layer. Referring to fig. 5, in the method for manufacturing a VDMOS device having a super junction structure provided by the embodiment of the present invention, a product schematic diagram of step S2 is shown.
Step S3: forming PN alternating super junction regions inside the deep trenches. Referring to fig. 6, in the method for manufacturing a VDMOS device having a super junction structure provided by the embodiment of the present invention, a product schematic diagram of step S3 is shown. The PN alternating super junction region is formed by transversely alternately arranging three P + layers and two N + layers at intervals, and the upper surface and the lower surface of the PN alternating super junction region are both P + layers. The P + layer is respectively a first P + layer, a second P + layer and a third P + layer from top to bottom, the N + layer is respectively a first N + layer and a second N + layer, the first N + layer is positioned between the first P + layer and the second P + layer, and the second N + layer is positioned between the second P + layer and the third P + layer. The doping concentrations of the first P + layer, the second P + layer and the third P + layer are sequentially reduced in a descending mode, the doping amount of the first P + layer is 4E 15-5E 15, the doping amount of the second P + layer is 3E 15-4E 15, and the doping amount of the third P + layer is 2E 15-3E 15. The dopant amounts of the first N + layer and the second N + layer are both 2E 15. The cross-sectional width of the PN alternating super junction region is 5-10 mu m. The thickness of each P + layer or N + layer in the PN alternating super junction region is 2-3 mu m. Wherein the unit of the doping dose is the number of ions per square centimeter.
Step S4: and injecting N-type ions through photoetching injection and thermal drive, wherein after the N-type ions are injected, a central area of the N + area, an N + epitaxial layer and two side edges of the P-epitaxial layer form an N + area, the N + area is an electronic drift area consisting of the central area, a bottom edge area and side edge areas, and a P-body area is formed between two sides of the central area of the N + area and the PN alternating super junction area. Referring to fig. 7, in the method for manufacturing a VDMOS device having a super junction structure provided by the embodiment of the present invention, a product schematic diagram of step S4 is shown. The N + region employs a PTBI2T electron drift layer polymerized from a TBI material. The N + region is an N-type heavily doped region, the doping amount is 1E 15-2E 15, and the cross section width is 2-5 mu m. The bottom edge region is a highly doped epitaxial layer, the side edge region is a longitudinal N + region formed by implantation and diffusion, and further, the epitaxial layer concentration of the bottom edge region can be higher than that of the longitudinal implantation diffusion formed side edge region. According to the technical scheme, the highly-doped N + region is introduced into the epitaxial layer at the interval between the drain electrode and the source electrode of the traditional MOS device, so that the resistivity of the epitaxial layer is reduced, and the on-resistance of the VDMOS device is further reduced.
Step S5: and forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid. Wherein, the width of the grid oxide layer is equal to that of the polysilicon grid.
Step S6: and photoetching and injecting the P-body regions at two sides of the polysilicon gate to form an N + source region. Referring to fig. 8, in the method for manufacturing a VDMOS device having a super junction structure according to the embodiment of the present invention, the product schematic diagrams of step S5 and step S6 are shown (the N-type substrate is not shown).
Step S7: forming device source metal on the upper surface of the junction of the PN alternating super junction region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming dielectric layer isolation among the device source metal, the device drain metal and the polysilicon gate, namely the product in the cross-sectional view of the VDMOS device with the super junction structure provided by the embodiment of the invention in the figure 1, wherein the upper part of an N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form a P-body region, the PN alternating super junction region is positioned at two sides of the central region of the N + region, between the N + region and the P-body region, the N + source region is arranged at the junction of the upper surface of the P-body region and the PN alternating super junction region, the gate oxide layer covers the upper surface of the junction of the N + source region, the N + region and the P-body region, and the polysilicon gate oxide layer is arranged above the gate oxide layer, device source electrode metal is arranged on the upper surface of the joint of the PN alternating super junction region and the N + source region, device drain electrode metal is arranged on the upper surface of the side region of the N + region, and dielectric layers are horizontally laid between the upper surface of the polysilicon gate and the device source electrode metal and between the device source electrode metal and the device drain electrode metal for isolation. The PN alternating super junction region is formed by alternately arranging P + layers and N + layers at intervals in the transverse direction, and the upper surface and the lower surface of the PN alternating super junction region are both the P + layers.
Further, in the method for manufacturing a VDMOS device having a super junction structure provided in the embodiment of the present invention, after performing surface planarization after the epitaxy, the method further includes: step S8: and a rapid annealing step, wherein the temperature range of the rapid annealing step is 1050-1100 ℃, and the atmosphere is hydrogen or nitrogen.
The manufacturing method of the VDMOS device with the super junction structure, provided by the embodiment of the invention, comprises the steps of providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the N + epitaxial layer is formed; forming deep grooves on two sides of the P-epitaxial layer, wherein the bottoms of the deep grooves extend to the upper surface of the N + epitaxial layer; forming a PN alternating super junction region in the deep trench; injecting N-type ions through photoetching injection and thermal drive, forming N + areas at the central area of the N + area, the two side edges of the N + epitaxial layer and the P-epitaxial layer after the N + areas are injected, and forming a P-body area between the two sides of the central area of the N + area and the PN alternating super junction area; forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid; photoetching and injecting P-body regions at two sides of the polysilicon gate to form an N + source region; forming device source metal on the upper surface of the connecting part of the PN alternating super junction region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying and forming dielectric layer isolation among the device source metal, the device drain metal and the polysilicon gate. This technical scheme is through adopting multilayer structure's PN super junction area in turn, the withstand voltage ability in VDMOS device unit area has been improved, with the inside highly doped N + district that introduces of spaced epitaxial layer between the drain electrode of traditional MOS device and the source electrode, the resistivity of epitaxial layer has been reduced, and then saturation current has been improved, VDMOS device on-resistance has been reduced, the structure volume of device has been reduced when having guaranteed device voltage resistance, the manufacturing cost of device has been reduced, and then it is poor to have alleviated the structure withstand voltage degree that prior art exists, the technical problem that on-resistance is big.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. A manufacturing method of a VDMOS device with a super junction structure is characterized by comprising the following steps:
providing an N-type substrate, forming an N + epitaxial layer on the upper surface of the N-type substrate, forming a P-epitaxial layer on the upper surface of the N + epitaxial layer, and flattening the surface after the epitaxy;
forming deep grooves on two sides of the P-epitaxial layer, wherein the bottoms of the deep grooves extend to the upper surface of the N + epitaxial layer;
forming a PN alternating super junction region inside the deep trench;
injecting N-type ions through photoetching injection and thermal drive, and after the N-type ions are injected, forming an N + region together by the middle part of a P-epitaxial layer, two side edges of the P-epitaxial layer and the N + epitaxial layer, wherein the middle part of the P-epitaxial layer is equivalent to the central region of the N + region, the N + epitaxial layer is equivalent to the bottom edge region of the N + region, and a P-body region is formed between two sides of the central region of the N + region and a PN alternating super junction region;
forming a grid oxide layer on the upper surface of the connection part of the N + region and the P-body region, and depositing on the surface of the grid oxide layer to form a polysilicon grid;
photoetching and injecting the P-body regions at two sides of the polysilicon gate to form an N + source region;
forming device source metal on the upper surface of the connecting part of the PN alternating super junction region and the N + source region, forming device drain metal on the upper surface of the side region of the N + region, and horizontally laying the device source metal, the device drain metal and the polysilicon gate to form dielectric layer isolation.
2. The method of manufacturing of claim 1, further comprising, after said post-epitaxy surface planarization: a rapid annealing step;
the temperature range of the rapid annealing step is 1050-1100 ℃, and the atmosphere is hydrogen or nitrogen.
3. The manufacturing method of claim 1, wherein the manufacturing method is implemented based on a VDMOS device with a super junction structure, and the VDMOS device with the super junction structure comprises: the device comprises an N-type substrate, an N + region, a P-body region, a PN alternating super junction region, an N + source region, a grid oxide layer, a polysilicon grid, a dielectric layer isolation, device source electrode metal and device drain electrode metal;
the N + region is an electronic drift region consisting of a central region, a bottom edge region and a side edge region;
the upper part of the N-type substrate is connected with the bottom edge region of the N + region, the inner surface of the N + region extends to the central region to form the P-body region, the PN alternating super-junction area is positioned on two sides of the central area of the N + area and between the side area of the N + area and the P-body area, the N + source region is arranged at the joint of the upper surface of the P-body region and the PN alternating super junction region, the grid oxide layer covers the upper surface of the junction of the N + source region, the N + region and the P-body region, the polysilicon gate is arranged above the gate oxide layer, device source metal is arranged on the upper surface of the joint of the PN alternating super junction region and the N + source region, device drain metal is arranged on the upper surface of the side edge region of the N + region, and the dielectric layer isolation is horizontally laid between the upper surface of the polysilicon gate and the device source metal as well as between the device source metal and the device drain metal;
the PN alternating super junction region is formed by longitudinally alternately arranging P + layers and N + layers at intervals, and the upper surface and the lower surface of the PN alternating super junction region are both P + layers.
4. The manufacturing method of claim 3, wherein the PN alternating super junction region is formed by longitudinally alternately arranging three P + layers and two N + layers, and the upper surface and the lower surface are both P + layers;
the P + layer is respectively a first P + layer, a second P + layer and a third P + layer from top to bottom, the N + layer is respectively a first N + layer and a second N + layer, the first N + layer is positioned between the first P + layer and the second P + layer, and the second N + layer is positioned between the second P + layer and the third P + layer.
5. The method of claim 4, wherein the doping concentrations of the first P + layer, the second P + layer and the third P + layer decrease in sequence, the doping amount of the first P + layer is 4E 15-5E 15, the doping amount of the second P + layer is 3E 15-4E 15, the doping amount of the third P + layer is 2E 15-3E 15, and the unit of the doping amount is the number of ions per square centimeter.
6. The method of claim 4, wherein the dopant amount of each of the first N + layer and the second N + layer is 2E15, and the unit of the dopant amount is ion number/square centimeter.
7. The method of claim 3, wherein the N + region is an N-type heavily doped region, the dopant amount is 1E 15-2E 15, the unit of the dopant amount is the number of ions per square centimeter, and the cross-sectional width is 2-5 μm.
8. The manufacturing method of claim 3, wherein the cross-sectional width of the PN junction region is 5-10 μm.
9. The manufacturing method of claim 3, wherein the thickness of each P + layer or N + layer in the PN alternating super junction region is 2-3 μm.
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