CN114267717B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN114267717B CN114267717B CN202111408155.5A CN202111408155A CN114267717B CN 114267717 B CN114267717 B CN 114267717B CN 202111408155 A CN202111408155 A CN 202111408155A CN 114267717 B CN114267717 B CN 114267717B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 210000000746 body region Anatomy 0.000 claims abstract description 89
- 239000002344 surface layer Substances 0.000 claims abstract description 67
- 239000010410 layer Substances 0.000 claims description 91
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 55
- 229920005591 polysilicon Polymers 0.000 claims description 46
- 238000002955 isolation Methods 0.000 claims description 22
- 239000013078 crystal Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims 1
- -1 phosphorus ion Chemical class 0.000 claims 1
- 230000005669 field effect Effects 0.000 abstract description 16
- 238000002360 preparation method Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Abstract
The invention relates to a semiconductor device and a preparation method thereof, a resistor structure with a first end and a second end is arranged on a first surface layer of a drift region, at least two grid source structures which are in one-to-one correspondence with each body region are arranged, a grid region of each grid source structure covers a channel formed by the body region and extends to cover the body region, two adjacent grid source structures comprise a first grid source structure and a second grid source structure, the grid region of the first grid source structure is connected with the first end, a drain region of the first grid source structure is connected with the second end electrically, a resistor is connected between the grid region and the drain region of the first grid source structure in parallel, and a field effect transistor formed by the second grid source structure is connected in parallel in the field effect transistor formed by the first grid source structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
Generally, after the high-voltage MOSFET is sealed with the control chip in a plastic package, a large resistor and a field effect transistor are integrated in the control chip to provide a current path, so as to provide a gate driving voltage for the high-voltage MOSFET, so that the high-voltage MOSFET is turned on.
At present, control chips are produced in wafer factories with the size of 8 inches and above, the manufacturing cost of the unit area of the chip is high, and the integrated devices in the control chips are more, so that the adjustment influence on the resistance value of the resistor is larger, and the scheme economy and the practicability of integrating the resistor in the control chips are not high.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor device capable of improving the economical efficiency and practicality of the control chip.
A semiconductor device, comprising:
a drift region having a first conductivity type;
the resistor structure is arranged on the first surface layer of the drift region and comprises a first end and a second end which are opposite;
a plurality of body regions arranged at intervals, respectively positioned on the first surface layer of the drift region and provided with a channel, wherein the body regions have a second conductivity type which is opposite to the first conductivity type;
the gate-source structures are respectively arranged in one-to-one correspondence with the body regions, each gate-source structure comprises a gate region and a source region which are adjacently arranged, each source region is arranged on the surface of the body region far away from the drift region, and each gate region covers the channel and extends to the body region; the adjacent two gate-source structures comprise a first gate-source structure and a second gate-source structure, and the gate region of the first gate-source structure is electrically connected with the first end;
and the drain electrode region is positioned on a second surface layer of the drift region and is electrically connected with the second end, and the second surface layer is arranged opposite to the first surface layer.
In one embodiment, the semiconductor device further comprises a third gate-source structure, the gate region of the third gate-source structure being electrically connected with the gate region of the second gate-source structure.
In one embodiment, the semiconductor device further includes:
and the isolation layer is positioned on the first surface layer of the drift region and is respectively arranged between the gate source structures.
In one embodiment, the semiconductor device further includes:
at least one isolation structure is arranged on the first surface layer of the drift region, is positioned between the body regions and is arranged between the body regions.
In one embodiment, the resistive structure comprises:
the first oxide layer is positioned on the first surface layer of the drift region;
and the polycrystalline silicon strip is positioned on the surface of the first oxide layer, which is far away from the drift region, and a first contact and a second contact are arranged on the extending direction of the polycrystalline silicon strip, wherein the first contact is used as the first end, and the second contact is used as the second end.
In one embodiment, the polysilicon strips include a plurality of strips arranged in an array, and each strip is connected in series or in parallel, wherein the width of each strip ranges from 1um to 4um, and the distance between two adjacent strips ranges from 1um to 3um.
In one embodiment, the second contact is located at an end of the polysilicon strip, and the resistor structure further includes:
and the insulating layer covers the first oxide layer and the polysilicon strips and exposes the second contact.
In one embodiment, the resistor structure further comprises:
and the conductive layer covers the second contact and is electrically connected with the drain electrode region.
In one embodiment, the source region is disposed adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.
In one embodiment, the resistor structure is disposed at an edge region of the semiconductor device and at least partially covers the body region, and the resistor structure is insulated from the body region.
In one embodiment, the body region comprises:
a doped well located on the first surface layer of the drift region and having a second conductivity type;
and the junction terminal extension region is positioned on the first surface layer of the drift region and overlapped with the doped well.
A method of fabricating a semiconductor device, comprising:
providing a substrate with a first doping type, and forming a drift region on the substrate, wherein the drift region has the first conductivity type;
forming a resistor structure on the first surface layer of the drift region, wherein the resistor structure comprises a first end and a second end which are opposite;
forming a plurality of body regions which are arranged at intervals on the first surface layer of the drift region, wherein the body regions are provided with channels and have a second conductivity type, and the second conductivity type is opposite to the first conductivity type;
forming at least two gate-source structures corresponding to the body regions one by one on the first surface layer of the drift region, wherein the gate-source structures comprise gate regions and source regions which are adjacently arranged, the source regions are arranged on the surface of the body region, which is far away from the drift region, and the gate regions cover the channels and extend to cover the body region; the adjacent two gate-source structures comprise a first gate-source structure and a second gate-source structure, and the gate region of the first gate-source structure is electrically connected with the first end;
and forming a drain region on a second surface layer of the drift region, wherein the drain region is electrically connected with the second end, and the second surface layer is opposite to the first surface layer.
In one embodiment, the method further comprises:
and forming at least one isolation structure on the first surface layer of the drift region by adopting an ion implantation process, wherein the isolation structure is positioned between the body regions and is arranged between the body regions.
In one embodiment, forming the resistive structure on the first surface layer of the drift region includes:
thermally oxidizing and growing a first oxide layer on the first surface layer of the drift region;
depositing a polysilicon layer on the first oxide layer, and respectively injecting P31 ions, N+ ions and P+ ions into the polysilicon layer, wherein the injection energy of the P31 ions is 40kev-80kev, and the dosage is 5E14/cm2-5E15/cm2;
and carrying out photoetching and dry etching on the polycrystalline silicon layer to obtain polycrystalline silicon strips, wherein the polycrystalline silicon strips comprise a plurality of crystal strips which are arranged in an array, the width range of each crystal strip is 1um to 4um, and the interval range of two adjacent crystal strips is 1um to 3um.
According to the semiconductor device, the resistor structure with the first end and the second end is arranged on the first surface layer of the drift region, at least two grid source structures which are in one-to-one correspondence with the body regions are arranged, the grid region of the grid source structure covers the channel formed by the body region and extends to cover the body region, the two adjacent grid source structures comprise the first grid source structure and the second grid source structure, the grid region of the first grid source structure is connected with the first end, the drain region of the first grid source structure is connected with the second end electrically, the resistor is connected between the grid region and the drain region of the first grid source structure in parallel, and the field effect transistor formed by the second grid source structure is connected in parallel in the field effect transistor formed by the first grid source structure.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment;
FIG. 2 is a partial top view of a semiconductor device according to one embodiment;
fig. 3 is an equivalent circuit diagram of a semiconductor device of an embodiment;
fig. 4 is a schematic structural view of a semiconductor device according to another embodiment;
fig. 5 is an equivalent circuit diagram of a semiconductor device of another embodiment;
fig. 6 is a top view of a semiconductor device of another embodiment;
fig. 7 is a schematic structural view of a semiconductor device according to another embodiment;
fig. 8 is a schematic structural view of a semiconductor device according to another embodiment;
fig. 9 is a schematic structural view of a semiconductor device according to another embodiment;
fig. 10 is a schematic structural view of a semiconductor device according to another embodiment;
fig. 11 is a schematic structural view of a semiconductor device according to another embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment, as shown in fig. 1, the semiconductor device may be applied to a semiconductor chip, and includes a drift region 100, a resistor structure 110, a plurality of body regions 120 arranged at intervals, at least two gate-source structures 130, and a drain region 140, where the drift region 100 has a first conductivity type; the resistor structure 110 is disposed on the first surface layer of the drift region 100, and the resistor structure 110 includes a first end and a second end opposite to each other; the body regions 120 are respectively located on the first surface layer of the drift region 100 and are formed with channels, and the body regions 120 have a second conductivity type opposite to the first conductivity type; at least two gate-source structures 130 are respectively arranged in one-to-one correspondence with each body region 120, each gate-source structure 130 comprises a gate region 1301 and a source region 1302 which are adjacently arranged, each source region 1302 is arranged on the surface of each body region 120 far away from the drift region 100, and each gate region 1301 covers a channel and extends to cover the corresponding body region 120; the two adjacent gate-source structures 130 include a first gate-source structure 131 and a second gate-source structure 132, and a gate region 1301 of the first gate-source structure 131 is electrically connected to the first terminal; the drain region 140 is located on a second surface of the drift region 100 and is electrically connected to the second terminal, and the second surface is disposed opposite to the first surface.
Wherein the conductivity types of the drift region 100 and the body region 120 are opposite. The first conductivity type and the second conductivity type are one of P-type and N-type, respectively, and the first conductivity type and the second conductivity type are different. For example, the first conductivity type is P-type and the second conductivity type is N-type; or the first conductivity type is N type and the second conductivity type is P type. Illustratively, in the present embodiment, the first conductivity type is N-type, the second conductivity type is P, i.e., the conductivity type of the drift region 100 is N-type, and the conductivity type of the body region 120110 is P-type.
Specifically, the drift region 100 may be formed by light ion implantation or doping, wherein the type of ions implanted may be selected according to actual needs.
The first surface layer of the drift region 100 may be the upper surface layer in fig. 1, the body region 120 of the first surface layer of the drift region 100 may be recessed to form a channel, as shown in fig. 2 (source region 1302 is not shown), the gate region 1301 covers the channel and extends to cover the surface of the body region 120, the source region 1302 is disposed on the surface of the body region 120 away from the drift region 100, for example, may be the upper surface of the body region 120 in fig. 1, and the source region 1302 has a first conductivity type opposite to the second conductivity type of the body region 120, such that a PN junction is formed between the source region 1302 and the body region 120, and finally forms a field effect transistor. Wherein the source region 1302 is disposed adjacent to the gate region 1301, and the source region 1302 is insulated from the gate region 1301. In addition, the gate region 1301 may cover a portion of the channel; the source region 1302 and the gate region 1301 are provided insulated.
As shown in fig. 3, the resistor structure 110 includes a first end electrically connected to the gate region 1301 of the first gate-source structure 131 and a second end connected to the drain region 140, that is, the gate region 1301 and the drain region 140 of the field-effect transistor are connected in parallel to one resistor structure 110, and the second gate-source structure 132 (gate is S and source is G) forms a field-effect transistor commonly connected to the first gate-source structure 131 (gate is S1 and source is G1) so that the field-effect transistor is connected in parallel to the field-effect transistor formed by the first gate-source structure 131, and the equivalent circuit diagram is shown with reference to fig. 3, in which the resistor R in the figure represents the resistor structure 110. Wherein a first end of the resistive structure 110 may be electrically connected to the gate region 1301 through an internal lead.
In one embodiment, the number of body regions 120 may be the same as the number of gate-source structures 130, and the number of gate-source structures 130 may be greater than two, such as three or more, where the body regions 120 also include three or more, to correspond one-to-one with the gate-source structures 130. If the first gate-source structure 131 and the second gate-source structure 132 are included in addition to other gate-source structures 130, the method is equivalent to forming other field-effect transistors sharing the drain electrode with the field-effect transistors formed by the first gate-source structure 131 and the second gate-source structure 132, and connecting the other field-effect transistors with the two field-effect transistors in parallel.
It will be appreciated that fig. 1 illustrates that the resistor structure 110 is partially overlapped on the upper surface of the body region 120, and in fact, it may be located on the first surface layer of the drift region 100 and not cover the body region 120, so as to avoid making an electrical connection with the body region 120.
In the semiconductor device of the embodiment of the invention, the resistor structure 110 having the first end and the second end is disposed on the first surface layer of the drift region 100, and at least two gate-source structures 130 corresponding to each body region 120 are disposed, the gate region 1301 of the gate-source structure 130 covers the channel formed by the body region 120 and extends to cover the body region 120, the two adjacent gate-source structures 130 include the first gate-source structure 131 and the second gate-source structure 132, the gate region 1301 of the first gate-source structure 131 is connected with the first end, the drain region 140 of the first gate-source structure 131 is connected with the second end electrically, which is equivalent to connecting a resistor in parallel between the gate region 1301 and the drain region 140 of the first gate-source structure 131, and connecting a field-effect transistor formed by the second gate-source structure 132 in parallel in the field-effect transistor formed by the first gate-source structure 131.
In one embodiment, as shown in fig. 4, the semiconductor device further includes a third gate-source structure 130, wherein a gate region 1301 of the third gate-source structure 130 is electrically connected with a gate region 1301 of the second gate-source structure 132.
It is understood that the gate region 1301 of the third gate-source structure 130 and the gate region 1301 of the second gate-source structure 132 may be connected through an internal wire, so that the gate of the third gate-source structure 130 shares the gate of the second gate-source structure 132, and the equivalent circuit is shown in fig. 5, where S2 is the source of the third gate-source structure 130.
When the number of the gate-source structures 130 is three, a top view of the semiconductor device may be shown in fig. 6, where S1 represents a source region 1302 of the first gate-source structure 131, G1 represents a gate region 1301 of the first gate-source structure 131, S represents a source region 1302 of the second gate-source structure 132, G represents a gate region 1301 of the second gate-source structure 132, and S2 is a source region 1302 of the third gate-source structure 130.
In one embodiment, as shown in fig. 7, the semiconductor device further includes at least one isolation layer 150 located on the first surface layer of the drift region 100 and respectively disposed between the gate-source structures 130.
It will be appreciated that the isolation layer 150 may be used to isolate two adjacent gate-source structures 130, which may include an oxide layer and a phosphosilicate glass layer disposed in a stack, wherein the oxide layer is located between the phosphosilicate glass layer and the drift region 100, which may partially cover the body region 120 between two adjacent gate-source structures 130.
In one embodiment, as shown in fig. 8, the semiconductor device further includes at least one isolation structure 160, where the isolation structure 160 is disposed on the first surface layer of the drift region 100 and between the body regions 120 and is spaced apart from the body regions 120.
It will be appreciated that the isolation structure 160 serves to isolate two adjacent body regions 120, preventing adjacent gate-source structures 130 from affecting one another during operation, while the arrangement does not affect the withstand voltage of the overall semiconductor device.
When the number of the gate-source structures 130 is plural, the number of the isolation structures 160 may be plural to isolate two adjacent gate-source structures 130. In one embodiment, each two adjacent isolation layers 150 may be in communication, for example, three body regions 120, so as to isolate the body region 120 located in the middle from the two adjacent body regions 120, respectively.
In one embodiment, the resistor structure 110 includes a first oxide layer 111 and polysilicon strips 112, as shown in fig. 9, wherein the first oxide layer 111 is located on a first surface layer of the drift region 100; the polysilicon strip 112 is located on the surface of the first oxide layer 111 away from the drift region 100, and a first contact and a second contact are disposed in the extension direction of the polysilicon strip 112, where the first contact is used as a first end and the second contact is used as a second end.
The polysilicon strips 112 are spaced apart from the source regions 1302 to avoid electrical connection between the polysilicon strips 112 and the source regions 1302.
It can be understood that the polysilicon strip 112 may be formed by connecting a plurality of crystal strips arranged in an array in series and parallel, or may be a single strip-shaped object having an elongated zigzag shape, an S-shaped shape, an elongated and spiral square shape, and an elongated and spiral circular shape, wherein the polysilicon strip 112 is provided with a first contact and a second contact, the positions of the first contact and the second contact can be adjusted according to actual needs, and the length of the polysilicon strip 112 between the first contact and the second contact can be determined according to the resistance value of the resistor connected to the gate region 1301 and the drain region 140. In one embodiment, the polysilicon strip 112 may be provided with a plurality of contacts capable of being externally connected, and when in use, two of the contacts may be selected as the first contact and the second contact according to actual needs.
In one embodiment, the polysilicon strips 112 include a plurality of strips arranged in an array, each strip being connected in series or parallel, wherein the width of the strip ranges from 1um to 4um, and the spacing between two adjacent strips ranges from 1um to 3um.
In one embodiment, the second contact is located at an end of the polysilicon strip 112, and the resistor structure 110 further includes an insulating layer 113, as shown in fig. 10, where the insulating layer 113 covers the first oxide layer 111 and the polysilicon strip 112, and exposes the second contact.
The insulating layer 113 may be a phosphosilicate glass material or a borophosphosilicate glass material.
It will be appreciated that to facilitate wiring, two contacts to polysilicon strip 112 may be located on first oxide layer 111 proximal and distal, respectively, to gate region 1301 of first gate-source structure 131, with a first contact located proximal to shorten the lead length when electrically connected to gate region 1301 and a second contact located distal to facilitate extraction through the lead to drain region 140.
The insulating layer 113 is used to isolate the polysilicon strip 112 to avoid the polysilicon strip 112 from contacting with other conductive layers, and expose only the second contact of the polysilicon strip 112 to facilitate the external connection of the drain region 140.
In one embodiment, the resistive structure 110 further includes a conductive layer covering the second contact and electrically connected to the drain region 140.
It will be appreciated that to facilitate the connection of polysilicon strip 112 to drain region 140, a conductive layer may be further disposed on the exposed second contact of polysilicon strip 112, and the electrical connection of polysilicon strip 112 to drain region 140 may be accomplished by the electrical connection of the conductive layer to drain region 140.
In one embodiment, the source region 1302 is disposed adjacent to the insulating layer 113 or the insulating layer 113 is at least partially embedded in the source region 1302.
It will be appreciated that to increase the compactness of the distribution of the structural layers and thus reduce the overall volume of the power device, the source region 1302 may be disposed adjacent to the insulating layer 113 or the insulating layer 113 may be at least partially embedded in the source region 1302, such that the insulating layer 113 is insulating, and thus, the source region 1302 and the polysilicon strips 112 are not shorted, and the compactness of the distribution of the structural layers is increased, thereby reducing the overall volume of the power device.
In one embodiment, the resistive structure 110 is disposed at an edge region of the semiconductor device and at least partially covers the body region 120, and the resistive structure 110 is insulated from the body region 120, thereby achieving device miniaturization.
In one embodiment, as shown in fig. 11, the body region 120 includes a doped well 121 and a junction termination extension region 122, the doped well 121 being located at a first surface layer of the drift region 100 and having a second conductivity type; junction termination extension region 122 is located on the first surface layer of drift region 100 and overlaps doped well 121 (the dashed hatched area is the overlapping area in the figure).
Specifically, the junction termination extension region 122 may be formed with a low concentration of a doped region, i.e., the junction termination extension region 122, at the edge of the main junction by implanting impurities of the same type as the main junction, the junction termination extension region 122 having the same conductivity type as the doped well 121. It will be appreciated that doping the well 121 ends will form a deeper pn junction, resulting in a greater curvature at the pn junction ends, a peak electric field at the device surface, resulting in a drop in device termination breakdown voltage, which can be improved by providing the junction termination extension region 122.
In one embodiment, the gate region 1301 is at least partially embedded in the source region 1302 in a direction parallel to the drift region 100.
It will be appreciated that the source region 1302 may have a recess in which the gate region 1301 may be at least partially disposed, wherein the gate region 1301 is insulated from the source region 1302, thus allowing for efficient use of the device area without affecting the current transfer performance when the device is on.
In one embodiment, the gate region 1301 includes a second oxide layer, a polysilicon layer, and an isolation layer 150, the second oxide layer being located on the first surface layer of the drift region 100 and extending to cover the surface of the body region 120; the polysilicon layer is positioned on the surface of the second oxide layer far away from the drift region 100; the spacer 150 is located between the polysilicon layer and the source region 1302.
Wherein the second oxide layer is used to isolate the polysilicon layer from the drift region 100 and the body region 120, and the isolation layer 150 is used to isolate the polysilicon layer from the source region 1302. The polysilicon layer may be a polysilicon material, or may be a metal, a metal nitride, a metal silicide, or the like.
In one embodiment, the drift region 100 includes a doped region having a first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on an upper surface of the doped region and may be formed by ion implantation.
The embodiment of the invention also provides a preparation method of the power device, which comprises the steps S110 to S160.
In step S110, a substrate having a first doping type is provided, and a drift region 100 is formed on the substrate, wherein the drift region 100 has the first conductivity type. Specifically, the first conductivity type may be one of P-type and N-type, and the drift region 100 is formed by doping ions. The drift region 100 may include a doped region having a first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on an upper surface of the doped region and may be formed by ion implantation.
In one embodiment, the drift region 100 may be of N conductivity type, formed by implantation of N ions, at a dose of 4E15-6E15/cm2.
In step S120, a resistor structure 110 is formed on the first surface of the drift region 100, and the resistor structure 110 includes a first end and a second end.
In step S130, the first surface layer of the drift region 100 forms a plurality of body regions 120 disposed at intervals, and the body regions 120 are formed with channels and have a second conductivity type, which is opposite to the first conductivity type.
Step S140, forming at least two gate-source structures 130 corresponding to each body region 120 one by one on the first surface layer of the drift region 100, wherein the gate-source structures 130 include a gate region 1301 and a source region 1302 disposed adjacently, the source region 1302 is disposed on the surface of the body region 120 away from the drift region 100, and the gate region 1301 covers the channel and extends to cover the body region 120; the adjacent two gate-source structures 130 include a first gate-source structure 131 and a second gate-source structure 132, and a gate region 1301 of the first gate-source structure 131 is electrically connected to the first terminal.
In step S150, a drain region 140 is formed on a second surface of the drift region 100, the drain region 140 is electrically connected to the second terminal, and the second surface is opposite to the first surface.
The descriptions of the drift region 100, the body region 120, the resistor structure 110, the gate-source structure 130, and the drain region are referred to the related descriptions in the above embodiments, and are not repeated here.
In one embodiment, the method further includes forming at least one isolation structure 160 on the first surface layer of the drift region 100 by using an ion implantation process, where the isolation structure 160 is located between the body regions 120 and is spaced apart from the body regions 120.
In one embodiment, the method further includes forming an isolation layer 150 on the first surface layer of the drift region 100, where the isolation layer 150 is disposed between the gate-source structures 130 at intervals.
In one embodiment, when the first surface layer of the drift region 100 forms the resistor structure 110, the resistor structure 110 may at least partially cover the body region 120, where the resistor structure 110 is insulated from the body region 120.
In one embodiment, when the resistor structure 110 is formed on the first surface layer of the drift region 100, the resistor structure 110 may be partially embedded in the source region 1302, so as to improve the compactness of the structural layer, thereby reducing the overall volume of the device, where the resistor structure 110 is insulated from the source region 1302.
In one embodiment, forming the resistor structure 110 on the first surface layer of the drift region 100 includes thermally oxidizing the first surface layer of the drift region 100 to grow a first oxide layer 111, depositing a polysilicon layer on the first oxide layer 111, and injecting P31 ions, n+ ions and p+ ions into the polysilicon layer, wherein the injection energy of the P31 ions is 40kev-80kev, the dosage is 5E14/cm2-5E15/cm2, and performing photolithography and dry etching on the polysilicon layer to obtain polysilicon strips 112, wherein the polysilicon strips 112 include a plurality of crystal strips arranged in an array, the width of the crystal strips ranges from 1um to 4um, and the distance between two adjacent crystal strips ranges from 1um to 3um.
Wherein the first oxide layer 111 can be grown by a thermal oxygen growth process to a thickness ofAfter the preparation of the first oxide layer 111, polysilicon deposition is performed with a thickness of +.>In one embodiment, the second contact is located at an end of the polysilicon strip 112, and forming the resistor structure 110 on the first surface layer of the drift region 100 further includes forming an insulating layer 113 on the first oxide layer 111 and the polysilicon strip 112, wherein the insulating layer 113 exposes the second contact.
In one embodiment, forming the resistor structure 110 on the first surface of the drift region 100 further includes covering the second contact with a conductive layer, and the conductive layer is electrically connected to the drain region 140.
In one embodiment, the step of forming the body region 120 on the first surface layer of the drift region 100 includes forming the doped well 121 and the junction termination extension region 122 on the first surface layer of the drift region 100, respectively, wherein the doped well 121 and the junction termination extension region 122 may be formed on the first surface layer of the drift region 100 by ion implantation, respectively.
Specifically, marking can be performed first to mark out the region where the body region is to be formed. The body region includes a doped well 121 and a junction termination extension 122, the doped well 121 may be a P-well, and may be formed by implanting B11 ions, wherein the dose is 3E13/cm2-6E13/cm2.
Junction termination extension region 122 may be grown to a thickness by first growing an oxide layer in the drift regionThe ions are then lithographically implanted to form junction termination extension 122. Thereafter, an oxide layer is grown with a thickness of +.>High temperature diffusion is carried out at 1150 ℃ or above, and main time is 300-500min. And then photoetching and etching to expose the area of the first surface layer of the drift region, which is required to prepare the other material layer, so as to prepare the other material layer further.
In addition, the contact hole for establishing the electric connection can be prepared through photoetching, etching and other processes, and the drain electrode can be prepared through back thinning, back injection and back metal processes.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (13)
1. A semiconductor device, comprising:
a drift region having a first conductivity type;
the resistor structure is arranged on the first surface layer of the drift region and comprises a first end and a second end which are opposite; the resistor structure comprises a plurality of crystal bars which are arranged in an array, and the crystal bars are connected in series or in parallel;
a plurality of body regions arranged at intervals, respectively positioned on the first surface layer of the drift region and provided with a channel, wherein the body regions have a second conductivity type which is opposite to the first conductivity type; wherein each body region forms a channel;
the gate-source structures are respectively arranged in one-to-one correspondence with the body regions, each gate-source structure comprises a gate region and a source region which are adjacently arranged, each source region is arranged on the surface of the body region far away from the drift region, and each gate region covers the channel and extends to the body region; the adjacent two gate-source structures comprise a first gate-source structure and a second gate-source structure, and the gate region of the first gate-source structure is electrically connected with the first end;
at least one isolation layer, which is positioned on the first surface layer of the drift region and is respectively arranged between the gate source structures;
and the drain electrode region is positioned on a second surface layer of the drift region and is electrically connected with the second end, and the second surface layer is arranged opposite to the first surface layer.
2. The semiconductor device of claim 1, further comprising a third gate-source structure, the gate region of the third gate-source structure being electrically connected with the gate region of the second gate-source structure.
3. The semiconductor device according to claim 1, wherein the semiconductor device further comprises:
at least one isolation structure is arranged on the first surface layer of the drift region, is positioned between the body regions and is arranged between the body regions.
4. The semiconductor device of claim 1, wherein the resistive structure comprises:
the first oxide layer is positioned on the first surface layer of the drift region;
the polysilicon strip is positioned on the surface of the first oxide layer far away from the drift region, and a first contact and a second contact are arranged on the extension direction of the polysilicon strip, wherein the first contact is used as the first end, and the second contact is used as the second end; the polycrystalline silicon strips comprise a plurality of crystal strips which are arranged in an array.
5. The semiconductor device of claim 4, wherein the width of the bars is in the range of 1um to 4um, and the pitch of two adjacent bars is in the range of 1um to 3um.
6. The semiconductor device of claim 4, wherein the second contact is located at an end of the polysilicon strip, the resistor structure further comprising:
and the insulating layer covers the first oxide layer and the polysilicon strips and exposes the second contact.
7. The semiconductor device of claim 6, wherein the resistive structure further comprises:
and the conductive layer covers the second contact and is electrically connected with the drain electrode region.
8. The semiconductor device of claim 6, wherein the source region is disposed adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.
9. The semiconductor device of claim 1, wherein the resistive structure is disposed at an edge region of the semiconductor device and at least partially covers the body region, the resistive structure being insulated from the body region.
10. The semiconductor device of claim 1, wherein the body region comprises:
a doped well located on the first surface layer of the drift region and having a second conductivity type;
and the junction terminal extension region is positioned on the first surface layer of the drift region and overlapped with the doped well.
11. A method of manufacturing a semiconductor device, comprising:
providing a substrate with a first doping type, and forming a drift region on the substrate, wherein the drift region has the first conductivity type;
forming a resistor structure on the first surface layer of the drift region, wherein the resistor structure comprises a first end and a second end which are opposite; the resistor structure comprises a plurality of crystal bars which are arranged in an array, and the crystal bars are connected in series or in parallel;
forming a plurality of body regions which are arranged at intervals on the first surface layer of the drift region, wherein the body regions are provided with channels and have a second conductivity type, and the second conductivity type is opposite to the first conductivity type; wherein each body region forms a channel;
forming at least two gate-source structures corresponding to the body regions one by one on the first surface layer of the drift region, wherein the gate-source structures comprise gate regions and source regions which are adjacently arranged, the source regions are arranged on the surface of the body region, which is far away from the drift region, and the gate regions cover the channels and extend to cover the body region; the adjacent two gate-source structures comprise a first gate-source structure and a second gate-source structure, and the gate region of the first gate-source structure is electrically connected with the first end;
forming an isolation layer between the gate source structures of the first surface layer of the drift region;
and forming a drain region on a second surface layer of the drift region, wherein the drain region is electrically connected with the second end, and the second surface layer is opposite to the first surface layer.
12. The method for manufacturing a semiconductor device according to claim 11, characterized in that the method further comprises:
and forming at least one isolation structure on the first surface layer of the drift region by adopting an ion implantation process, wherein the isolation structure is positioned between the body regions and is arranged between the body regions.
13. The method of manufacturing a semiconductor device according to claim 11, wherein forming a resistive structure in the first surface layer of the drift region comprises:
thermally oxidizing and growing a first oxide layer on the first surface layer of the drift region;
depositing a polysilicon layer on the first oxide layer, and implanting P31 ions into the polysilicon layer, wherein
The implantation energy of P31 ion is 40kev-80kev, the dosage is 5E14/cm2-5E15/cm2; wherein P31 is a phosphorus ion;
and carrying out photoetching and dry etching on the polycrystalline silicon layer to obtain polycrystalline silicon strips, wherein the polycrystalline silicon strips comprise a plurality of crystal strips which are arranged in an array, the width range of each crystal strip is 1um to 4um, and the interval range of two adjacent crystal strips is 1um to 3um.
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