CN114267716A

CN114267716A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN114267716A
Application number: CN202111400001.1A
Authority: CN
Inventors: 魏国栋; 李�杰; 李佳玲
Original assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Current assignee: SHENZHEN SI SEMICONDUCTORS CO Ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2022-04-01

Abstract

The invention relates to a semiconductor device and a preparation method thereof.A resistor structure with a first end and a second end is arranged on a first surface layer of a drift region, the first end is electrically connected with a gate region, the second end is electrically connected with a drain region, namely a resistor is connected in parallel between the gate region and the drain region.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background

Generally, after the high-voltage MOSFET and the control chip are sealed in a plastic package, a large resistor needs to be integrated in the control chip to provide a current path, and then a gate driving voltage is provided for the high-voltage MOSFET, so that the high-voltage MOSFET is turned on.

At present, most control chips are produced in a wafer factory with the size of 8 inches or more, the manufacturing cost of the chip unit area is high, and the number of integrated devices in the control chips is large, so that the adjustment influence on the resistance value of the resistor is large, and therefore the economy and the practicability of the scheme for integrating the resistor in the control chips are not high.

Disclosure of Invention

In view of this, it is necessary to provide a semiconductor device capable of improving the economy and practicality of a control chip.

A semiconductor device, comprising:

a drift region having a first conductivity type;

the body region is positioned on the first surface layer of the drift region and is provided with a channel, and the body region has a second conduction type which is opposite to the first conduction type;

the gate region is positioned on the first surface layer of the drift region, covers the channel and extends to cover the surface of the body region;

the source region is arranged on the surface, far away from the drift region, of the body region and is adjacent to the gate region;

the resistance structure is arranged on the first surface layer of the drift region and comprises a first end and a second end which are opposite, and the first end is electrically connected with the gate region;

and the drain region is positioned on a second surface layer of the drift region and is electrically connected with the second end, and the second surface layer is opposite to the first surface layer.

In one embodiment, the resistive structure comprises:

the first oxide layer is positioned on the first surface layer of the drift region;

the polycrystalline silicon strip is located on the surface, far away from the drift region, of the first oxidation layer, a first contact and a second contact are arranged in the extending direction of the polycrystalline silicon strip, the first contact serves as the first end, and the second contact serves as the second end.

In one embodiment, the polysilicon strips comprise a plurality of crystal strips arranged in an array, and the crystal strips are connected in series or in parallel.

In one embodiment, the second contact is located at an end of the polysilicon strip, and the resistor structure further includes:

and the insulating layer covers the surfaces of the first oxide layer and the polycrystalline silicon strips, which are far away from the drift region, and exposes the second contact.

In one embodiment, the source region is disposed adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.

In one embodiment, the resistor structure further comprises:

and the conducting layer covers the second contact and is electrically connected with the drain region.

In one embodiment, the body region includes:

the doped well is positioned on the first surface layer of the drift region and has a second conduction type;

and the junction terminal extension region is positioned on the first surface layer of the drift region and is overlapped with the doped well.

In one embodiment, the gate region is at least partially embedded in the source region in a direction parallel to the drift region.

A method of fabricating a semiconductor device, the method comprising:

providing a substrate with a first doping type, and forming a drift region on the substrate, wherein the drift region has a first conduction type;

forming a body region on the first surface layer of the drift region, wherein the body region has a second conductivity type, and the second conductivity type is opposite to the first conductivity type;

forming a gate region on the first surface layer of the drift region, wherein the gate region covers the channel and extends to cover the surface of the body region;

forming a source region on the first surface layer of the drift region, wherein the source region is arranged adjacent to the gate region;

forming a resistor structure on the first surface layer of the drift region, wherein the resistor structure comprises a first end and a second end which are opposite, and the first end is electrically connected with the gate region;

and forming a drain region on a second surface layer of the drift region, wherein the drain region is electrically connected with the second end, and the second surface layer is arranged opposite to the first surface layer.

In one embodiment, the forming of the resistive structure on the first surface layer of the drift region includes:

growing a first oxide layer on the first surface layer of the drift region by thermal oxidation;

depositing a polysilicon layer on the first oxide layer, and respectively injecting P31 ions, N + ions and P + ions into the polysilicon layer;

and photoetching and dry etching the polycrystalline silicon layer to obtain polycrystalline silicon strips, wherein the polycrystalline silicon strips comprise a plurality of crystal strips which are arranged in an array.

According to the semiconductor device, the resistor structure with the first end and the second end is arranged on the first surface layer of the drift region, the first end is electrically connected with the gate region, the second end is electrically connected with the drain region, and equivalently, the resistor is connected between the gate region and the drain region in parallel.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment;

FIG. 2 is a partial top view of a semiconductor device of an embodiment;

FIG. 3 is an equivalent circuit diagram of a semiconductor device of an embodiment;

fig. 4 is a schematic structural view of a semiconductor device of another embodiment;

fig. 5 is a schematic structural view of a semiconductor device of another embodiment;

fig. 6 is a schematic structural view of a semiconductor device of another embodiment;

fig. 7 is a schematic structural view of a semiconductor device of another embodiment;

fig. 8 is a partial top view of a semiconductor device of another embodiment.

Element number description:

a drift region: 100, respectively; body region: 110; a gate region: 120 of a solvent; source region: 130, 130; resistance structure: 140 of a solvent; a first oxide layer: 141, a solvent; polysilicon strips: 142; insulating layer: 143; conductive layer: 144, 144; drain region: 150; doping a well: 111; junction termination extension: 112

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.

It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment, which may be applied to a semiconductor chip, and includes a drift region 100, a body region 110, a gate region 120, a source region 130, a resistive structure 140, and a drain region 150, where the drift region 100 has a first conductivity type; the two body regions 110 are arranged at intervals on a first surface layer of the drift region 100 and have a second conductivity type, and the second conductivity type is opposite to the first conductivity type; the gate region 120 is located on the first surface layer of the drift region 100 and extends to cover the surfaces of the two body regions 110; the source region 130 is disposed at a first surface of the drift region 100 and adjacent to the gate region 120; the resistor structure 140 is disposed on a first surface layer of the drift region 100 and includes a first end and a second end opposite to the first end, and the first end is electrically connected to the gate region 120; the drain region 150 is located on a second surface layer of the drift region 100, and is electrically connected to the second end, where the second surface layer is opposite to the first surface layer.

Wherein the conductivity types of the drift region 100 and the body region 110 are opposite. The first conductive type and the second conductive type are respectively one of a P type and an N type, and the first conductive type and the second conductive type are different. For example, the first conductivity type is P-type, and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type. Illustratively, in the present embodiment, the first conductivity type is N-type, the second conductivity type is P, that is, the conductivity type of the drift region 100 is N-type, and the conductivity type of the body region 110 is P-type.

Specifically, the drift region 100 may be formed by light ion implantation or doping, wherein the type of the implanted ions may be selected according to actual needs.

The first surface layer of the drift region 100 may be the upper surface layer in fig. 1, the body region 110 in the first surface layer of the drift region 100 may be recessed to form a channel, as shown in fig. 2 (the source region 130 is not shown), the gate region 120 covers the channel and extends to cover the surface of the body region 110, the source region 130 is disposed on the surface of the body region 110 away from the drift region 100, for example, may be the upper surface of the body region 110 in fig. 1, and the source region 130 has the first conductivity type opposite to the second conductivity type of the body region 110, so that a PN junction is formed between the source region 130 and the body region 110, and finally the field effect transistor is formed. Wherein the source region 130 is disposed adjacent to the gate region 120 and the source region 130 is insulated from the gate region 120. Furthermore, the gate region 120 may cover a portion of the channel; the source region 130 and the gate region 120 are arranged insulated.

The resistor structure 140 includes a first end and a second end, the first end is electrically connected to the gate region 120, and the second end is connected to the drain region 150, that is, a resistor structure 140 is connected in parallel to the gate region 120 and the drain region 150 of the field effect transistor, and the equivalent circuit diagram can refer to fig. 3, where a resistor R in the diagram represents the resistor structure 140. Wherein the first end of the resistive structure 140 may be electrically connected to the gate region 120 through an inner lead.

It is to be understood that the resistive structure 140 is exemplarily shown in fig. 1 to partially overlap the upper surface of the body region 110, and in fact, it may be located at the first surface layer of the drift region 100 and not cover the body region 110, so as to avoid making an electrical connection with the body region 110.

In the semiconductor device according to the embodiment of the present invention, the resistor structure 140 having the first end and the second end is disposed on the first surface layer of the drift region 100, and the first end is electrically connected to the gate region 120, and the second end is electrically connected to the drain region 150, which is equivalent to that a resistor is connected in parallel between the gate region 120 and the drain region 150.

In one embodiment, resistive structure 140 at least partially covers body region 110, and resistive structure 140 is insulated from body region 110.

It is understood that to reduce the volume of the semiconductor device, resistive structure 140 may be at least partially overlying the upper surface of body region 110, wherein resistive structure 140 is disposed insulated from body region 110.

In one embodiment, the resistive structure 140 may also be partially embedded in the source region 130 to improve the compactness of the structural layer, thereby reducing the overall volume of the device, wherein the resistive structure 140 is disposed in an insulated manner from the source region 130.

In one embodiment, the resistive structure 140 may include a first oxide layer 141 and a polysilicon strip 142, as shown in FIG. 4. The first oxide layer 141 is located on a first surface layer of the drift region 100; the polysilicon strips 142 are located on the surface of the first oxide layer 141 away from the drift region 100, and first contacts and second contacts are arranged in the extending direction of the polysilicon strips 142, wherein the first contacts serve as first ends and the second contacts serve as second ends.

The first oxide layer 141 may be a silicon dioxide layer, and the polysilicon strips 142 are spaced apart from the source region 130 to prevent the polysilicon strips 142 from being electrically connected to the source region 130.

It can be understood that the polysilicon stripe may be formed by connecting a plurality of arrayed crystal stripes in series and in parallel, or may be a single stripe object having an elongated zigzag shape, an S-shape, an elongated and spiral square shape, and an elongated and spiral circular shape, where the polysilicon stripe 142 is provided with a first contact and a second contact, positions of the first contact and the second contact may be adjusted according to actual requirements, and a length of the polysilicon stripe 142 between the first contact and the second contact may be determined according to a resistance value of a resistor connected to the gate region 120 and the drain region 150. In one embodiment, the polysilicon strips 142 may be provided with a plurality of contacts for external connection, and two contacts may be selected as the first contact and the second contact according to actual needs when in use.

In one embodiment, the polysilicon strips include a plurality of strips arranged in an array, and the strips are connected in series or in parallel.

Wherein the width range of crystal bar can be 1um to 4um, and the interval range of two adjacent crystal bars is 1um to 3 um.

In one embodiment, the second contact is located at an end of the polysilicon strip 142, and the resistor structure 140 further includes an insulating layer 143, where the insulating layer 143 covers the first oxide layer 141 and a surface of the polysilicon strip 142 away from the drift region 100, and exposes the second contact.

The insulating layer can be a phosphosilicate glass material or a borophosphosilicate glass material.

It will be appreciated that, as shown in fig. 5, for ease of wiring, two contacts to the polysilicon strip 142 may be located on the first oxide layer 141, respectively, at a proximal end and a distal end with respect to the gate region 120, wherein the first contact is located at the proximal end to shorten the length of the lead when electrically connected to the gate region 120 and the second contact is located at the distal end for ease of lead-out through the lead to the drain region 150.

The insulating layer 143 is used to isolate the polysilicon strips 142 to prevent the polysilicon strips 142 from contacting the other conductive layers 144, and to expose only the second contacts of the polysilicon strips 142 to connect the drain regions 150.

In one embodiment, source region 130 is disposed adjacent insulating layer 143 or insulating layer 143 is at least partially embedded in source region 130.

It is understood that in order to improve the compactness of the distribution of the structural layers and thus reduce the overall volume of the semiconductor device, the source region 130 may be disposed adjacent to the insulating layer 143, or the insulating layer 143 may be at least partially embedded in the source region 130, so that the source region 130 and the polysilicon stripe 142 are not shorted due to the insulating property of the insulating layer 143, and the compactness of the distribution of the structural layers is improved and thus the overall volume of the semiconductor device is reduced.

In one embodiment, the resistor structure 140 may further include a conductive layer 144, as shown in fig. 6, the conductive layer 144 covers the second contact and is electrically connected to the drain region 150.

It is understood that to facilitate the connection between the polysilicon stripe 142 and the drain region 150, a conductive layer 144 may be further disposed at the exposed second contact of the polysilicon stripe 142, and the electrical connection between the polysilicon stripe 142 and the drain region 150 is realized through the electrical connection between the conductive layer 144 and the drain region 150.

In one embodiment, taking the semiconductor device in fig. 1 as an example, the body region 110 may include a doped well 111 and a junction termination extension region 112, as shown in fig. 7, the doped well 111 is located on a first surface layer of the drift region 100 and has the second conductivity type; the junction termination extension region 112 is located at the first surface layer of the drift region 100 and is overlapped with the doped well 111 (the overlapped region is shown by a dashed-line shaded region in the figure).

Specifically, the junction termination extension region 112 may be formed at the edge of the main junction by implanting impurities of the same type as the main junction, thereby forming a low concentration doped region, i.e., the junction termination extension region 112 having the same conductivity type as the doped well 111. It will be appreciated that the deeper pn junction formed at the end of the doped well 111 results in a greater curvature at the end of the pn junction and a peak electric field at the surface of the device resulting in a reduced breakdown voltage at the device termination, which can be increased by the provision of the junction termination extension 112.

In one embodiment, the gate region 120 is at least partially embedded in the source region 130 in a direction parallel to the drift region 100.

As shown in fig. 8, it is understood that the source region 130 may have a recess, and the gate region 120 may be at least partially disposed in the recess, wherein the gate region 120 and the source region 130 are disposed in an insulating manner, so that the device area may be effectively utilized without affecting the current transmission performance when the device is turned on.

In one embodiment, the gate region 120 includes a second oxide layer, a polysilicon layer and an isolation layer, the second oxide layer being located on the first surface of the drift region 100 and extending to cover the surface of the body region 110; the polysilicon layer is positioned on the surface of the second oxide layer far away from the drift region 100; the isolation layer is located between the polysilicon layer and the source region 130.

Wherein the second oxide layer is used to isolate the polysilicon layer from the drift region 100 and the body region 110, and the isolation layer is used to isolate the polysilicon layer from the source region 130. The polysilicon layer may be polysilicon material, metal nitride, metal silicide, etc.

In one embodiment, the drift region 100 includes a doped region having the first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on an upper surface of the doped region and can be formed by ion implantation.

The embodiment of the invention also provides a preparation method of the semiconductor device, which comprises the steps S110 to S160.

Step S110, a substrate with a first doping type is provided, and a drift region 100 is formed on the substrate, where the drift region 100 has a first conductivity type.

Specifically, the first conductive type may be one of a P type and an N type, and the drift region 100 is formed by doping ions. The drift region 100 may include a doped region having the first conductivity type and an epitaxial layer, wherein the epitaxial layer is also of the first conductivity type, and the epitaxial layer is located on an upper surface of the doped region and may be formed by ion implantation.

In one embodiment, the drift region 100 may be of the N conductivity type formed by implanting N ions at a dose of 4E15-6E15/cm 2.

In step S120, a body region 110 is formed on the first surface layer of the drift region 100, wherein the body region 110 has a second conductivity type, and the second conductivity type is opposite to the first conductivity type.

The second conductive type may be one of a P type and an N type, and is opposite to the first conductive type. For example, the first conductivity type is P-type, and the second conductivity type is N-type; or the first conductive type is N type, and the second conductive type is P type. Illustratively, in the present embodiment, the first conductivity type is N-type, the second conductivity type is P, that is, the conductivity type of the drift region 100 is N-type, and the conductivity type of the body region 110 is P-type.

The first surface layer of the drift region 100 may be the upper surface layer in fig. 1, and the body regions 110 in the first surface layer of the drift region 100 may be recessed to form channels, as shown in fig. 2.

In step S130, a gate region 120 is formed on the first surface of the drift region 100, and the gate region 120 covers the channel and extends to cover the surface of the body region 110.

In step S140, a source region 130 is formed on the first surface layer of the drift region 100, and the source region 130 is disposed adjacent to the gate region 120.

Wherein the source region 130 has a first conductivity type opposite to a second conductivity type of the body region 110, such that a PN junction is formed between the source region 130 and the body region 110, eventually forming a field effect transistor.

In step S150, a resistor structure 140 is formed on the first surface layer of the drift region 100, where the resistor structure 140 includes a first end and a second end, and the first end is electrically connected to the gate region 120.

Specifically, the first end may be electrically connected to the gate region 120 through an inner lead.

In step S160, a drain region 150 is formed on the second surface of the drift region 100, and the drain region 150 is electrically connected to the second end.

Wherein the source region is spaced apart from the drift region 100 by the body region 110; the drain region 150 and the second terminal may be electrically connected by an internal wiring.

In one embodiment, when the resistive structure 140 is formed on the first surface layer of the drift region 100, the resistive structure 140 may also at least partially cover the body region 110, wherein the resistive structure 140 is insulated from the body region 110.

It is understood that the resistive structure 140 may be at least partially stacked on the upper surface of the body region 110, wherein the resistive structure 140 is disposed insulated from the body region 110, which may reduce the volume of the semiconductor device.

In one embodiment, when the resistive structure 140 is formed on the first surface layer of the drift region 100, the resistive structure 140 may be partially embedded in the source region 130 to improve the compactness of the structure layer, thereby reducing the overall volume of the device, wherein the resistive structure 140 is disposed in an insulated manner from the source region 130.

In one embodiment, the forming of the resistor structure on the first surface layer of the drift region includes growing a first oxide layer on the first surface layer of the drift region by thermal oxidation, depositing a polysilicon layer on the first oxide layer, injecting P31 ions, N + ions and P + ions into the polysilicon layer, and performing photolithography and dry etching on the polysilicon layer to obtain a polysilicon strip, wherein the polysilicon strip includes a plurality of strips arranged in an array, and the strips are connected in series or in parallel.

The implantation energy of P31 ions is 40-80 kev, the dosage is 2E15/cm2-5E15/cm2, the width range of crystal bars is 1um to 4um, and the distance range of two adjacent crystal bars is 1um to 3 um.

Wherein the first oxide layer 141 can be grown thick by thermal oxidationDegree of

After the first oxide layer 141 is prepared, polysilicon deposition is performed to a thickness of

In one embodiment, the manufacturing method further includes forming an insulating layer 143 on the surfaces of the first oxide layer 141 and the polysilicon strips 142 away from the drift region 100, wherein the insulating layer 143 exposes the second contact.

It will be appreciated that two contacts to the polysilicon strips 142 may be located on the first oxide layer 141, respectively, at a proximal end and a distal end with respect to the gate region 120, wherein the first contact is located at the proximal end to shorten the length of the wire when electrically connected to the gate region 120 and the second contact is located at the distal end to facilitate lead-out through the wire to the drain region 150. The insulating layer 143 is used to isolate the polysilicon strips 142 to prevent the polysilicon strips 142 from contacting the other conductive layers 144, and to expose only the second contacts of the polysilicon strips 142 to connect the drain regions 150.

Specifically, if the insulating layer 143 is at least partially embedded in the source region 130, the insulating layer 143 may be partially formed in a pre-prepared region of the source region 130 before preparing the source region 130, and then the source region 130 is prepared; in another embodiment, after the preparation of the source region 130 is completed, a groove may be etched on the sidewall of the source region 130, so that the insulating layer 143 can be formed in the groove of the source region 130.

In one embodiment, the fabrication method further includes covering the conductive layer 144 on the second contact so as to connect the polysilicon stripe 142 with the drain region 150.

In one embodiment, the step of forming the body region 110 on the first surface layer of the drift region 100 includes forming the doped well 111 and the junction termination extension region 112 on the first surface layer of the drift region 100, respectively, wherein the doped well 111 and the junction termination extension region 112 can be formed on the first surface layer of the drift region 100 by ion implantation, respectively.

Specifically, marking may be performed first to mark the region where the body region needs to be formed. The body region includes a doped well 121 and a junction termination extension 122, the doped well 121 may be a P-well and may be formed by implanting B11 ions at a dose of 3E13/cm2-6E13/cm 2.

The junction termination extension region 122 may be formed by first growing an oxide layer in the drift region to a thickness of

The junction termination extension 122 is then formed by photolithographic implantation of ions. An oxide layer is then grown on the junction termination extension region 122 by thermal oxidation to a thickness of

High temperature diffusion at 1150 deg.c for 300-500 min. And then photoetching and corroding to expose the area of the first surface layer of the drift region of the other material layer to be prepared so as to further prepare the other material layer.

For example, a recess may be formed when forming the source region 130, such that the gate region 120 may be at least partially embedded in the recess when forming the gate region 120.

In one embodiment, the step of forming the gate region 120 on the first surface of the drift region 100 includes forming a second oxide layer on the first surface of the drift region 100, wherein the second oxide layer extends to cover the surface of the body region 110, then forming a polysilicon layer on the surface of the second oxide layer away from the drift region 100, and finally forming an isolation layer on the upper surface of the polysilicon layer.

In addition, a contact hole for establishing electric connection is prepared through the processes of photoetching, etching and the like, and the drain electrode is prepared by adopting the processes of back thinning, back injection and back metal.

In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A semiconductor device, comprising:

a drift region having a first conductivity type;

2. The semiconductor device of claim 1, wherein the resistive structure comprises:

3. The semiconductor device according to claim 2, wherein the polysilicon strips comprise a plurality of strips arranged in an array, and the strips are connected in series or in parallel.

4. The semiconductor device of claim 2, wherein the second contact is located at an end of the polysilicon strip, the resistive structure further comprising:

5. The semiconductor device of claim 4, wherein the source region is disposed adjacent to the insulating layer or the insulating layer is at least partially embedded in the source region.

6. The semiconductor device of claim 4, wherein the resistive structure further comprises:

7. The semiconductor device of claim 1, wherein the body region comprises:

8. The semiconductor device of claim 2, wherein the gate region is at least partially embedded in the source region in a direction parallel to the drift region.

9. A method of fabricating a semiconductor device, the method comprising:

10. The method of claim 9, wherein forming a resistive structure on the first surface layer of the drift region comprises: