CN113659010A - MOSFET device integrated with RC absorption structure and manufacturing method - Google Patents
MOSFET device integrated with RC absorption structure and manufacturing method Download PDFInfo
- Publication number
- CN113659010A CN113659010A CN202111054711.3A CN202111054711A CN113659010A CN 113659010 A CN113659010 A CN 113659010A CN 202111054711 A CN202111054711 A CN 202111054711A CN 113659010 A CN113659010 A CN 113659010A
- Authority
- CN
- China
- Prior art keywords
- source
- insulating medium
- main surface
- gate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010521 absorption reaction Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 88
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 68
- 238000005530 etching Methods 0.000 claims description 48
- 238000000151 deposition Methods 0.000 claims description 45
- 210000000746 body region Anatomy 0.000 claims description 29
- 150000002500 ions Chemical class 0.000 claims description 12
- 230000000873 masking effect Effects 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000001413 cellular effect Effects 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 230000010355 oscillation Effects 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 13
- 239000003990 capacitor Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 5
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to an MOSFET device with an integrated RC absorption structure and a manufacturing method thereof, and the MOSFET device comprises a plurality of device cell units which are mutually connected in parallel, wherein each device cell unit comprises a first conduction type substrate and a first conduction type drift region, an insulated deep groove is arranged in each first conduction type drift region, a groove insulating medium is filled in each insulated deep groove, source conductive polycrystalline silicon is arranged on each groove insulating medium, the surface of each source conductive polycrystalline silicon is wrapped by the insulating medium, a source resistor is arranged on each insulating medium, and each source resistor is wrapped by source metal and in ohmic contact with the source metal. The RC absorption structure is arranged between the source electrode and the drain electrode of the device, so that the MOS tube can resist high surge current in the high-frequency switching process, and can absorb voltage oscillation in the switching process of the device, thereby improving voltage oscillation dVdsDt tolerance, effective preventiondV for stopping device from oscillating due to voltagedsThe/dt-induced failure can eliminate EMI problems during switching.
Description
Technical Field
The invention relates to a power semiconductor device, in particular to a MOSFET device integrated with an RC absorption structure and a manufacturing method thereof, belonging to the technical field of power semiconductor devices.
Background
Because of its advantages of high switching speed, low switching loss, high input impedance, voltage drive, high frequency, etc., a MOSFET (metal oxide semiconductor field effect transistor) is widely used as a power switching tube in various fields such as switching power supplies, automotive electronics, motor drive, etc.;
when the MOS is used as a power switch tube, the MOS works in an ON-OFF rapid cycle switching state, and the internal parasitic capacitance C of the MOS worksdsFast charge and discharge, and high voltage oscillation dV between drain and sourcedsDt and current oscillation dIdsDt, high voltage oscillation dVdsThe superposition of/dt in the switching system becomes a main interference source of electric field coupling and magnetic field coupling, namely EMI (electromagnetic interference); therefore, improvements are needed.
Disclosure of Invention
The invention aims to provide an MOSFET device with an integrated RC absorption structure and a manufacturing method thereof aiming at the EMI phenomenon of the existing power MOSFET device in the application process, wherein the RC absorption structure is integrated between a source electrode and a drain electrode of a device cell unit, so that an MOS tube can resist high surge current and absorb voltage oscillation in the switching process in the high-frequency switching-on and switching-off process, the voltage oscillation dVds/dt tolerance is improved, the failure of the device caused by the voltage oscillation dVds/dt is effectively prevented, and the EMI problem in the switching process is eliminated.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: an integrated RC absorption structure MOSFET device, comprising a plurality of device cell units connected in parallel, wherein the device cell units comprise a first conductive type substrate and a first conductive type drift region on the first conductive type substrate, and the integrated RC absorption structure MOSFET device is characterized in that: the first conduction type drift region is internally provided with a plurality of insulating deep grooves, the insulating deep grooves penetrate through a second conduction type body region positioned on the upper portion of the first conduction type drift region from the upper surface of the first conduction type drift region and extend to the inner portion or the bottom of the first conduction type drift region, the insulating deep grooves are filled with groove insulating media, source conductive polycrystalline silicon is arranged on the groove insulating media, the surface of the source conductive polycrystalline silicon is wrapped by the insulating media, the insulating media are provided with source resistors, and the source resistors are wrapped by source metal and in ohmic contact with the source metal.
Further, a first conductive type source region is arranged in the second conductive type body region, and the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region respectively through an insulating medium;
and the lower surface of the first conduction type substrate is provided with drain metal, and the drain metal is in ohmic contact with the first conduction type substrate.
Further, the trench depth of the deep insulating trench does not exceed the bottom of the first conductivity type drift region.
Further, the source resistor comprises polysilicon, the trench insulating medium comprises silicon oxide and silicon nitride, and the insulating medium comprises borophosphosilicate glass.
Further, the device unit cell comprises a plane grid type unit cell and a groove grid type unit cell.
Further, for the planar gate type unit cell, a gate oxide layer and gate conductive polysilicon located on the gate oxide layer are further arranged on the upper surface of the first conductive type drift region, the surface of the gate conductive polysilicon is wrapped by an insulating medium and is arranged at an interval with the source conductive polysilicon, the source resistor is arranged above the source conductive polysilicon or arranged above the gate conductive polysilicon, and the gate conductive polysilicon is in ohmic contact with gate metal.
Further, for the groove gate type cellular unit, a gate groove is arranged in the second conductive type interval, a gate conductive polysilicon and a gate oxide layer positioned on the side wall of the gate groove are arranged in the gate groove, the top of the gate groove is covered by an insulating medium, the gate conductive polysilicon and the source conductive polysilicon are arranged at intervals, the source resistor is arranged above the source conductive polysilicon or arranged above the gate conductive polysilicon, and the gate conductive polysilicon is in ohmic contact with gate metal.
In order to achieve the above technical object, the present invention further provides a method for manufacturing a MOSFET device with an integrated RC absorbing structure, comprising the following steps:
a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region and a first conduction type substrate positioned below the first conduction type drift region, the upper surface of the first conduction type drift region is a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate is a second main surface of the semiconductor substrate;
b. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
c. etching the first main surface under the masking of the first hard mask window to obtain an insulated deep trench positioned in the first conductive type drift region, and removing the first hard mask window;
d. depositing an insulating medium in the first main surface of the semiconductor substrate and the insulating deep groove, etching the insulating medium, and removing the insulating medium on the first main surface to obtain a groove insulating medium in the insulating deep groove;
e. growing an oxide layer and depositing conductive polycrystalline silicon on the first main surface of the semiconductor substrate, and etching the conductive polycrystalline silicon and the oxide layer in turn to obtain a plurality of grid conductive polycrystalline silicon, source conductive polycrystalline silicon positioned among the grid conductive polycrystalline silicon and a grid oxide layer positioned below the grid conductive polycrystalline silicon;
f. implanting second conductive type ions into the first main surface of the semiconductor substrate, and annealing to obtain a second conductive type body region located in the first conductive type drift region;
g. implanting first conductive type ions into the first main surface of the semiconductor substrate to obtain a first conductive type source region located in the second conductive type body region;
h. depositing an insulating medium on the first main surface of the semiconductor substrate, and then depositing conductive polysilicon on the insulating medium;
i. selectively etching the conductive polysilicon to obtain a plurality of source resistors on the insulating medium;
j. selectively etching the insulating medium to obtain a plurality of metal contact holes;
k. depositing metal in the metal contact hole, the insulating medium layer and the source electrode resistor, and etching the metal to obtain source electrode metal and grid electrode metal;
and l, thinning the second main surface of the semiconductor, and then depositing metal to obtain drain metal positioned on the lower surface of the first conduction type substrate.
In order to achieve the above technical object, the present invention further provides a method for manufacturing a MOSFET device with an integrated RC absorbing structure, comprising the following steps:
a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region and a first conduction type substrate positioned below the first conduction type drift region, the upper surface of the first conduction type drift region is a first main surface of the semiconductor substrate, and the lower surface of the first conduction type substrate is a second main surface of the semiconductor substrate;
b. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
c. etching the first main surface under the masking of the first hard mask window to obtain an insulated deep trench positioned in the first conductive type drift region, and removing the first hard mask window;
d. depositing an insulating medium in the first main surface of the semiconductor substrate and the insulating deep groove, etching the insulating medium, and removing the insulating medium on the first main surface to obtain a groove insulating medium in the insulating deep groove;
e. depositing a hard mask layer on the first main surface of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window;
f. etching the first main surface under the masking of the second hard mask window to obtain a gate trench positioned between the insulating deep trenches, and removing the second hard mask window;
g. sequentially depositing an oxide layer and conductive polycrystalline silicon on the first main surface of the semiconductor substrate and in the gate trench, and sequentially etching the conductive polycrystalline silicon and the oxide layer to obtain gate conductive polycrystalline silicon and a gate oxide layer which are positioned in the gate trench, and simultaneously obtain source conductive polycrystalline silicon positioned above the trench insulating medium;
h. implanting second conductive type ions into the first main surface of the semiconductor substrate, and annealing to obtain a second conductive type body region located in the first conductive type drift region;
i. implanting first conductive type ions into the first main surface of the semiconductor substrate to obtain a first conductive type source region located in the second conductive type body region;
j. depositing an insulating medium on the first main surface of the semiconductor substrate, and then depositing conductive polysilicon on the insulating medium;
k. selectively etching the conductive polysilicon to obtain a plurality of source resistors on the insulating medium;
i, selectively etching the insulating medium to obtain a plurality of metal contact holes;
m, depositing metal in the metal contact hole, the insulating medium layer and the source electrode resistor, and etching the metal to obtain source electrode metal and grid electrode metal;
and n, thinning the second main surface of the semiconductor, and then depositing metal to obtain drain metal positioned on the lower surface of the first conduction type substrate.
Further, for an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Compared with the prior art, the invention has the following advantages:
1) according to the invention, the source electrode resistor in ohmic contact with the source electrode resistor is arranged at the source electrode terminal, the source electrode resistor is the absorption resistor R, the insulating deep groove is arranged in the N-type drift region at the source electrode terminal and the drain electrode terminal, the insulating deep groove is filled with the groove insulating medium, the floating source electrode conductive polycrystalline silicon is arranged above the insulating deep groove, and the source electrode conductive polycrystalline silicon-the groove insulating medium-the N-type drift region form the MIS capacitor C, so that an RC absorption structure formed by connecting the absorption resistor R and the MIS capacitor C in series is formed between the source electrode and the drain electrode;
the size of the MIS capacitor C can be adjusted according to requirements by changing the depth of the insulated deep trench, the length of the insulated deep trench and the number of the insulated deep trenches, and the size of the absorption resistor R can be adjusted according to requirements by changing the number of the source resistors, the doping concentration and the like; the MIS capacitance C is typically varied by varying the depth of the insulated deep trench, for example, when the insulated deep trench extends to the bottom of the N-type drift region, the MIS capacitance C consists of: the source electrode conductive polysilicon-groove insulating medium-N type substrate generally changes the size of the absorbing resistor R by changing the doping concentration of the conductive polysilicon in the source electrode resistor;
2) in an application circuit, the whole application circuit can generate surge pulse voltage in the switching process of a device and can impact the device, the MIS capacitor C is connected in parallel at the two ends of the drain-source capacitor Cds, the parallel capacitor capacity of the switch is equivalently increased, the voltage surge in the switching process of the device can be effectively resisted, and the voltage oscillation dV can be improvedds(ii) dt tolerance; meanwhile, due to the action of the absorption resistor R, the impedance is increased, the voltage oscillation in the switching process of the device can be effectively buffered, and the voltage oscillation dV is improveddsThe/dt tolerance effectively prevents the device from failing due to voltage oscillation, and further improves the electromagnetic interference (EMI) problem of the whole circuit.
Drawings
Fig. 1 is a schematic sectional structure in embodiment 1 of the present invention.
Fig. 2 is a schematic sectional structure in embodiment 2 of the present invention.
Fig. 3 is a schematic sectional structure in embodiment 3 of the present invention.
Fig. 4 is a schematic sectional structure in embodiment 4 of the present invention.
Fig. 5 is a schematic cross-sectional structure diagram of a semiconductor substrate according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional structure diagram of forming an insulated deep trench and a trench insulating medium in an embodiment of the invention.
Fig. 7 is a schematic cross-sectional structural view of forming source conductive polysilicon, gate conductive polysilicon and gate oxide in embodiment 1 and embodiment 2 of the present invention.
Fig. 8 is a schematic cross-sectional structural view of forming a P-type body region and an N-type source region in embodiment 1 and embodiment 2 of the present invention.
Fig. 9 is a schematic cross-sectional structural view of forming an insulating medium in example 1 and example 2 of the present invention.
Fig. 10 is a schematic cross-sectional structure diagram of forming a source resistor and a metal contact hole in embodiment 1 of the present invention.
Fig. 11 is a schematic cross-sectional structure diagram of forming a source resistor and a metal contact hole in embodiment 2 of the present invention.
Fig. 12 is a schematic cross-sectional structural view of forming a gate trench in embodiment 3 and embodiment 4 of the present invention.
Fig. 13 is a schematic cross-sectional structural view of forming source conductive polysilicon, gate conductive polysilicon and gate oxide in embodiment 3 and embodiment 4 of the present invention.
Fig. 14 is a schematic cross-sectional structural view of forming P-type body regions and N-type source regions in embodiment 3 and embodiment 4 of the present invention.
Fig. 15 is a schematic cross-sectional structural view of forming an insulating dielectric in example 3 and example 4 of the present invention.
Fig. 16 is a schematic cross-sectional structure diagram of forming a source resistor and a metal contact hole in embodiment 3 of the present invention.
Fig. 17 is a schematic cross-sectional structure diagram of forming a source resistor and a metal contact hole in embodiment 4 of the present invention.
Fig. 18 is an equivalent circuit diagram of a MOSFET device of the present invention.
Description of reference numerals: 001-first major face; 002-second major face; a 1-N type substrate; a 2-N type drift region; 3-insulating deep trenches; a 4-P type body region; 5-source conductive polysilicon; 6-grid conductive polysilicon; 7-an insulating medium; 8-source resistance; 9-trench insulating dielectric; 10 source metal; 11-drain metal; a 12-N type source region; 13-a gate trench; 14-gate oxide layer.
Detailed Description
The present invention will be further described with reference to the following specific examples.
Taking an N-type MOSFET device as an example, the first conductivity type is N-type, and the second conductivity type is P-type;
example 1: is an N-type planar gate MOSFET device;
as shown in fig. 1, a MOSFET device with an integrated RC absorption structure comprises a plurality of device unit cells connected in parallel, the unit cell of the device comprises an N-type substrate 1 and an N-type drift region 2 positioned on the N-type substrate 1, a plurality of insulated deep trenches 3 are arranged in the N-type drift region 2, the insulated deep trenches 3 extend from the upper surface of the N-type drift region 2 to the inside through a P-type body region 4 positioned at the upper part of the N-type drift region 2, and does not exceed the lower surface of the N-type drift region 2, the deep insulating trench 3 is filled with a trench insulating medium 9, the groove insulating medium 9 is provided with source electrode conductive polysilicon 5, the surface of the source electrode conductive polysilicon 5 is wrapped by an insulating medium 7, and a source electrode resistor 8 is arranged on the insulating medium 7, and the source electrode resistor 8 is wrapped by source electrode metal 10 and is in ohmic contact with the source electrode metal 10.
An N-type source region 12 is arranged in the P-type body region 4, and the source metal 10 penetrates through the insulating medium 7 and is in ohmic contact with the N-type source region 12 and the P-type body region 4 respectively; the lower surface of the N-type substrate 1 is provided with drain metal 11, and the drain metal 11 is in ohmic contact with the N-type substrate 1;
for the planar unit cell, a gate oxide layer 13 and a gate conductive polysilicon 6 located on the gate oxide layer 13 are further disposed on the upper surface of the N-type drift region 2, the surface of the gate conductive polysilicon 6 is wrapped by an insulating medium 7 and is spaced from the source conductive polysilicon 5, the source resistor 8 is disposed above the source conductive polysilicon 5, the gate conductive polysilicon 6 is in ohmic contact with the gate metal, specifically, the leading-out end of the gate conductive polysilicon 6 at the terminal is connected with the gate metal, which is well known to those skilled in the art and is not shown in the drawing.
Example 2: as in example 1, all of them were N-type planar gate MOSFET devices;
as shown in fig. 2, unlike embodiment 1, in embodiment 2, the source resistor 8 is disposed above the gate conductive polysilicon 6, and is also disposed on the insulating medium 7 and in ohmic contact with the source metal 10;
in embodiment 1 and embodiment 2 of the present invention, the source resistor includes polysilicon, the trench insulating medium includes silicon oxide and silicon nitride, and the insulating medium includes borophosphosilicate glass.
The method for manufacturing the MOSFET device integrated with the RC absorbing structure as in the above embodiments 1 and 2 includes the following steps:
as shown in fig. 5, a, providing a semiconductor substrate, where the semiconductor substrate includes an N-type drift region 2 and an N-type substrate 1 located below the N-type drift region 2, an upper surface of the N-type drift region 2 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N-type substrate 1 is a second main surface 002 of the semiconductor substrate;
b. depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
as shown in fig. 6, c, under the masking of the first hard mask window, etching the first main surface 001 to obtain the insulated deep trench 3 located in the N-type drift region 2, and removing the first hard mask window;
d. depositing an insulating medium in the first main surface 001 of the semiconductor substrate and the insulating deep trench 3, etching the insulating medium, and removing the insulating medium on the first main surface 001 to obtain a trench insulating medium 9 located in the insulating deep trench 3;
as shown in fig. 7, e, growing an oxide layer and depositing conductive polysilicon on the first main surface 001 of the semiconductor substrate, and etching the oxide layer and the conductive polysilicon in turn to obtain a plurality of gate conductive polysilicon 6, source conductive polysilicon 5 located between the gate conductive polysilicon 6, and a gate oxide layer 14 located below the gate conductive polysilicon 6;
as shown in fig. 8, f, implanting P-type ions into the first main surface 001 of the semiconductor substrate, and annealing to obtain a P-type body region 4 located in the N-type drift region 2;
g. implanting N-type ions into a first main surface 001 of the semiconductor substrate to obtain an N-type source region 17 positioned in the P-type body region 4;
as shown in fig. 9, h, depositing an insulating medium 7 on the first main surface 001 of the semiconductor substrate, and then depositing conductive polysilicon on the insulating medium 7;
as shown in fig. 10 and 11, i, selectively etching the conductive polysilicon to obtain a plurality of source resistors 8 on the insulating medium 7;
j. selectively etching the insulating medium 7 to obtain a plurality of metal contact holes;
as shown in fig. 1 and fig. 2, k, depositing metal in the metal contact hole, on the insulating dielectric layer 7 and on the source resistor 8, and etching the metal to obtain a source metal 10 and a gate metal;
and l, thinning the second main surface 002 of the semiconductor, and then depositing metal to obtain drain metal 11 positioned on the lower surface of the N-type substrate 1.
Example 3: take trench gate MOSFET as an example;
as shown in fig. 3, a MOSFET device with an integrated RC absorption structure comprises a plurality of device unit cells connected in parallel, the unit cell of the device comprises an N-type substrate 1 and an N-type drift region 2 positioned on the N-type substrate 1, a plurality of insulated deep trenches 3 are arranged in the N-type drift region 2, the insulated deep trenches 3 extend from the upper surface of the N-type drift region 2 to the inside through a P-type body region 4 positioned at the upper part of the N-type drift region 2, and does not exceed the lower surface of the N-type drift region 2, the deep insulating trench 3 is filled with a trench insulating medium 9, the groove insulating medium 9 is provided with source electrode conductive polysilicon 5, the surface of the source electrode conductive polysilicon 5 is wrapped by an insulating medium 7, and a source electrode resistor 8 is arranged on the insulating medium 7, and the source electrode resistor 8 is wrapped by source electrode metal 10 and is in ohmic contact with the source electrode metal 10.
An N-type source region 12 is arranged in the P-type body region 4, and the source metal 10 penetrates through the insulating medium 7 and is in ohmic contact with the N-type source region 12 and the P-type body region 4 respectively; the lower surface of the N-type substrate 1 is provided with drain metal 11, and the drain metal 11 is in ohmic contact with the N-type substrate 1;
for the trench type cellular unit, a gate trench 13 is arranged between the P-type body regions 4, a gate conductive polysilicon 6 and a gate oxide layer 14 positioned on the side wall of the gate trench 13 are arranged in the gate trench 13, the top of the gate trench 13 is covered by an insulating medium 7, the source resistor 8 is arranged above the source conductive polysilicon 5, the gate conductive polysilicon 6 is in ohmic contact with a gate metal, specifically, the gate conductive polysilicon 6 is connected with the gate metal at the leading-out end of the terminal, which is well known by those skilled in the art and is not shown in the figure.
Example 4: as in example 3, all of them were trench gate type MOSFET devices;
as shown in fig. 4, the difference from embodiment 3 is that the source resistor 8 is disposed above the gate conductive polysilicon 6, also disposed on the insulating medium 7, and in ohmic contact with the source metal 10.
In embodiments 3 and 4 of the present invention, the source resistor includes polysilicon, the trench insulating medium includes silicon oxide and silicon nitride, and the insulating medium includes borophosphosilicate glass; the trench gate MOSFET further includes a shield gate type trench MOSFET.
The method for manufacturing the MOSFET device integrated with the RC absorbing structure as in the above embodiments 3 and 4 includes the following steps:
as shown in fig. 5, a, providing a semiconductor substrate, where the semiconductor substrate includes an N-type drift region 2 and an N-type substrate 1 located below the N-type drift region 2, an upper surface of the N-type drift region 2 is a first main surface 001 of the semiconductor substrate, and a lower surface of the N-type substrate 1 is a second main surface 002 of the semiconductor substrate;
b. depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
as shown in fig. 6, c, under the masking of the first hard mask window, etching the first main surface 001 to obtain the insulated deep trench 3 located in the N-type drift region 2, and removing the first hard mask window;
d. depositing an insulating medium in the first main surface 001 of the semiconductor substrate and the insulating deep trench 3, etching the insulating medium, and removing the insulating medium on the first main surface 001 to obtain a trench insulating medium 9 located in the insulating deep trench 3;
as shown in fig. 12, e, depositing a hard mask layer on the first main surface 001 of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window;
f. etching the first main surface 001 under the masking of the second hard mask window 21 to obtain a gate trench 13 in the N-type drift region 2, and removing the second hard mask window;
as shown in fig. 13, g, sequentially depositing an oxide layer and conductive polysilicon on the first main surface 001 of the semiconductor substrate and in the gate trench 13, and sequentially etching the conductive polysilicon and the oxide layer to obtain gate conductive polysilicon 6 and a gate oxide layer 14 in the gate trench 13;
as shown in fig. 14, f, implanting P-type ions into the first main surface 001 of the semiconductor substrate, and annealing to obtain a P-type body region 4 located in the N-type drift region 2;
g. implanting N-type ions into a first main surface 001 of the semiconductor substrate to obtain an N-type source region 17 positioned in the P-type body region 4;
as shown in fig. 15, h, depositing an insulating medium 7 on the first main surface 001 of the semiconductor substrate, and then depositing conductive polysilicon on the insulating medium 7;
as shown in fig. 16 and 17, i, selectively etching the conductive polysilicon to obtain a plurality of source resistors 8 on the insulating medium 7;
j. selectively etching the insulating medium 7 to obtain a plurality of metal contact holes;
as shown in fig. 3 and fig. 4, k, depositing metal in the metal contact hole, on the insulating dielectric layer 7 and on the source resistor 8, and etching the metal to obtain a source metal 10 and a gate metal;
and l, thinning the second main surface 002 of the semiconductor, and then depositing metal to obtain drain metal 11 positioned on the lower surface of the N-type substrate 1.
As shown in fig. 18, the source metal 10 of the present invention is used to lead out the device source S, the drain metal 11 is used to lead out the device drain D, and the RC absorption structure connected in series between the device source and drain is composed of: the source resistor 8 is an absorption resistor R, the source conductive polysilicon 5 is arranged in a floating mode, the source conductive polysilicon 5-the trench insulating medium 9-the N-type drift region 2 form an MIS capacitor C, and when the insulated deep trench 3 extends to the bottom of the N-type drift region 2, the MIS capacitor C forms the source conductive polysilicon 5-the trench insulating medium 9-the N-type substrate 1, so that the size of the MIS capacitor C is generally adjusted by adjusting the depth of the insulated deep trench 3;
in an application circuit, the whole application circuit can generate surge pulse voltage in the switching process of a device and impact the device due to the source-drain parasitic capacitance CdsMIS capacitor C is connected in parallel at two ends, the parallel capacitance capacity of the switch is equivalently increased, the voltage surge in the switching process of the device can be effectively resisted, and the voltage oscillation dV can be improvedds(ii) dt tolerance; meanwhile, due to the action of the absorption resistor R, the impedance is increased, the voltage oscillation in the switching process of the device can be effectively buffered, and the voltage oscillation dV is improveddsThe/dt tolerance effectively prevents the device from failing due to voltage oscillation, and further improves the electromagnetic interference (EMI) problem of the whole circuit.
According to the formula: and I is Q/t C V/t, which is derived frominrush＝Cds*dVds/dt, whereininrushFor surge currents, CdsIs parasitic capacitance of source and drain, dVdsSource of/dtA rate of change of drain voltage;
subject to the same surge current IinrushUnder the conditions of (A) CdsThe greater, the dVdsThe smaller the/dt, i.e. the source-drain parasitic capacitance CdsThe larger, VdsThe smaller the oscillation amplitude and, therefore, the drain-source parasitic capacitance CdsMIS capacitor C is connected in parallel at two ends, the capacity of the parallel capacitor of the switch is equivalently increased, the voltage surge in the switching process of the device can be effectively resisted, the drain-source voltage oscillation can be reduced, and the voltage oscillation dV can be improveddsAnd the/dt tolerance is reduced, the switching noise is reduced, and the EMI performance is improved.
Claims (10)
1. MOSFET device with integrated RC-absorption structure, comprising a number of device cell units connected in parallel to each other, said device cell units comprising a substrate (1) of a first conductivity type and a drift region (2) of the first conductivity type located on the substrate (1) of the first conductivity type, characterized in that: the first conduction type drift region (2) is internally provided with a plurality of insulating deep grooves (3), the insulating deep grooves (3) penetrate through a second conduction type body region (4) on the upper portion of the first conduction type drift region (2) from the upper surface of the first conduction type drift region (2) and extend to the inner portion or the bottom of the first conduction type drift region, groove insulating media (9) are filled in the insulating deep grooves (3), source conducting polycrystalline silicon (5) is arranged on the groove insulating media (9), the surface of the source conducting polycrystalline silicon (5) is wrapped by insulating media (7), source resistors (8) are arranged on the insulating media (7), and the source resistors (8) are wrapped by source metal (10) and are in ohmic contact with the source metal (10).
2. The MOSFET device of claim 1, wherein: a first conductive type source region (12) is arranged in the second conductive type body region (4), and the source metal (10) penetrates through the insulating medium (7) and is in ohmic contact with the first conductive type source region (12) and the second conductive type body region (4) respectively;
the lower surface of the first conduction type substrate (1) is provided with drain metal (11), and the drain metal (11) is in ohmic contact with the first conduction type substrate (1).
3. The MOSFET device of claim 1, wherein: the depth of the insulating deep groove (3) does not exceed the bottom of the first conduction type drift region (2).
4. The MOSFET device of claim 1, wherein: the source resistor (8) comprises polycrystalline silicon, the trench insulating medium (9) comprises silicon oxide and silicon nitride, and the insulating medium (7) comprises boron phosphorus silicon glass.
5. The MOSFET device of claim 1, wherein: the device cell unit comprises a planar grid cell unit and a groove grid cell unit.
6. The MOSFET device of claim 5, wherein: for the planar gate type cellular unit, a gate oxide layer (13) and gate conductive polysilicon (6) positioned on the gate oxide layer (13) are further arranged on the upper surface of the first conductive type drift region (2), the surface of the gate conductive polysilicon (6) is wrapped by an insulating medium (7) and is arranged at intervals with the source conductive polysilicon (5), the source resistor (8) is arranged above the source conductive polysilicon (5) or above the gate conductive polysilicon (6), and the gate conductive polysilicon (6) is in ohmic contact with gate metal.
7. The MOSFET device of claim 5, wherein: for the groove gate type cellular unit, a gate groove (13) is arranged between the second conductive type body regions (4), gate conductive polycrystalline silicon (6) and a gate oxide layer (14) located on the side wall of the gate groove (13) are arranged in the gate groove (13), the top of the gate groove (13) is covered by an insulating medium (7), the gate conductive polycrystalline silicon (6) and the source conductive polycrystalline silicon (5) are arranged at intervals, the source resistor (8) is arranged above the source conductive polycrystalline silicon (5) or above the gate conductive polycrystalline silicon (6), and the gate conductive polycrystalline silicon (6) is in ohmic contact with gate metal.
8. The method of claim 6, further comprising the steps of:
a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region (2) and a first conduction type substrate (1) positioned below the first conduction type drift region (2), the upper surface of the first conduction type drift region (2) is a first main surface (001) of the semiconductor substrate, and the lower surface of the first conduction type substrate (1) is a second main surface (002) of the semiconductor substrate;
b. depositing a hard mask layer on a first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
c. etching the first main surface (001) under the masking of the first hard mask window to obtain an insulated deep trench (3) positioned in the first conductive type drift region (2), and removing the first hard mask window;
d. depositing an insulating medium in the first main surface (001) and the deep insulating groove (3) of the semiconductor substrate, etching the insulating medium, and removing the insulating medium on the first main surface (001) to obtain a groove insulating medium (9) in the deep insulating groove (3);
e. growing an oxide layer and depositing conductive polycrystalline silicon on the first main surface (001) of the semiconductor substrate, and etching the conductive polycrystalline silicon and the oxide layer in turn to obtain a plurality of grid conductive polycrystalline silicon (6), source conductive polycrystalline silicon (5) positioned among the grid conductive polycrystalline silicon (6) and a grid oxide layer (14) positioned below the grid conductive polycrystalline silicon (6);
f. implanting second conductivity type ions into the first main surface (001) of the semiconductor substrate, and annealing to obtain a second conductivity type body region (4) located in the first conductivity type drift region (2);
g. implanting first conductivity type ions into a first main surface (001) of the semiconductor substrate to obtain a first conductivity type source region (12) located in the second conductivity type body region (4);
h. depositing an insulating medium (7) on the first main surface (001) of the semiconductor substrate and then depositing conductive polysilicon on the insulating medium (7);
i. selectively etching the conductive polysilicon to obtain a plurality of source resistors (8) on the insulating medium (7);
j. selectively etching the insulating medium (7) to obtain a plurality of metal contact holes;
k. depositing metal in the metal contact hole, the insulating medium layer (7) and the source resistor (8), and etching the metal to obtain source metal (10) and grid metal;
and l, thinning the second main surface (002) of the semiconductor, and then depositing metal to obtain drain metal (11) positioned on the lower surface of the first conduction type substrate (1).
9. The method of claim 7, further comprising the steps of:
a. providing a semiconductor substrate, wherein the semiconductor substrate comprises a first conduction type drift region (2) and a first conduction type substrate (1) positioned below the first conduction type drift region (2), the upper surface of the first conduction type drift region (2) is a first main surface (001) of the semiconductor substrate, and the lower surface of the first conduction type substrate (1) is a second main surface (002) of the semiconductor substrate;
b. depositing a hard mask layer on a first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned first hard mask window;
c. etching the first main surface (001) under the masking of the first hard mask window to obtain an insulated deep trench (3) positioned in the first conductive type drift region (2), and removing the first hard mask window;
d. depositing an insulating medium in the first main surface (001) and the deep insulating groove (3) of the semiconductor substrate, etching the insulating medium, and removing the insulating medium on the first main surface (001) to obtain a groove insulating medium (9) in the deep insulating groove (3);
e. depositing a hard mask layer on the first main surface (001) of the semiconductor substrate, and selectively etching the hard mask layer to obtain a patterned second hard mask window;
f. etching the first main surface (001) under the masking of the second hard mask window to obtain a gate trench (13) between the insulated deep trenches (3), and removing the second hard mask window;
g. sequentially depositing an oxide layer and conductive polycrystalline silicon on the first main surface (001) of the semiconductor substrate and in the gate trench (13), and sequentially etching the conductive polycrystalline silicon and the oxide layer to obtain gate conductive polycrystalline silicon (6) and a gate oxide layer (14) which are positioned in the gate trench (13), and simultaneously obtain source conductive polycrystalline silicon (5) which is positioned above the trench insulating medium (9);
h. implanting second conductivity type ions on the first main surface (001) of the semiconductor substrate, and annealing to obtain a second conductivity type body region (4) located in the first conductivity type drift region (2);
i. implanting first conductivity type ions into a first main surface (001) of the semiconductor substrate to obtain a first conductivity type source region (12) located in the second conductivity type body region (4);
j. depositing an insulating medium (7) on the first main surface (001) of the semiconductor substrate and then depositing conductive polysilicon on the insulating medium (7);
k. selectively etching the conductive polysilicon to obtain a plurality of source resistors (8) on the insulating medium (7);
l, selectively etching the insulating medium (7) to obtain a plurality of metal contact holes;
m, depositing metal in the metal contact hole, the insulating medium layer (7) and the source resistor (8), and etching the metal to obtain source metal (10) and grid metal;
and n, thinning the second main surface (002) of the semiconductor, and then depositing metal to obtain drain metal (11) positioned on the lower surface of the first conduction type substrate (1).
10. The MOSFET device with integrated RC absorbing structure and the method of making thereof as claimed in claim 1, 8 or 9, wherein: for an N-type MOSFET device structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type MOSFET device structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111054711.3A CN113659010B (en) | 2021-09-09 | 2021-09-09 | MOSFET device integrated with RC absorption structure and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111054711.3A CN113659010B (en) | 2021-09-09 | 2021-09-09 | MOSFET device integrated with RC absorption structure and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113659010A true CN113659010A (en) | 2021-11-16 |
| CN113659010B CN113659010B (en) | 2022-07-12 |
Family
ID=78482998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111054711.3A Active CN113659010B (en) | 2021-09-09 | 2021-09-09 | MOSFET device integrated with RC absorption structure and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113659010B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114267717A (en) * | 2021-11-19 | 2022-04-01 | 深圳深爱半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116313807A (en) * | 2023-02-28 | 2023-06-23 | 上海维安半导体有限公司 | Preparation method of super-junction device with double-layer side wall structure and super-junction device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030094649A1 (en) * | 2001-11-16 | 2003-05-22 | Koninklijke Philips Electronics | Field effect transistor semiconductor device |
| CN101821852A (en) * | 2007-08-08 | 2010-09-01 | 先进模拟科技公司 | The cascode current sensor that is used for discrete power semiconductor devices |
| CN107275402A (en) * | 2017-03-31 | 2017-10-20 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| CN107768435A (en) * | 2017-10-20 | 2018-03-06 | 电子科技大学 | A kind of two-way IGBT and its manufacture method |
| CN111244179A (en) * | 2020-01-16 | 2020-06-05 | 电子科技大学 | anti-EMI super-junction VDMOS device |
| CN112002686A (en) * | 2020-09-30 | 2020-11-27 | 深圳市威兆半导体有限公司 | anti-EMI SGT device |
-
2021
- 2021-09-09 CN CN202111054711.3A patent/CN113659010B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030094649A1 (en) * | 2001-11-16 | 2003-05-22 | Koninklijke Philips Electronics | Field effect transistor semiconductor device |
| CN101821852A (en) * | 2007-08-08 | 2010-09-01 | 先进模拟科技公司 | The cascode current sensor that is used for discrete power semiconductor devices |
| CN107275402A (en) * | 2017-03-31 | 2017-10-20 | 成都芯源系统有限公司 | Semiconductor device and method for manufacturing the same |
| CN107768435A (en) * | 2017-10-20 | 2018-03-06 | 电子科技大学 | A kind of two-way IGBT and its manufacture method |
| CN111244179A (en) * | 2020-01-16 | 2020-06-05 | 电子科技大学 | anti-EMI super-junction VDMOS device |
| CN112002686A (en) * | 2020-09-30 | 2020-11-27 | 深圳市威兆半导体有限公司 | anti-EMI SGT device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114267717A (en) * | 2021-11-19 | 2022-04-01 | 深圳深爱半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN114267717B (en) * | 2021-11-19 | 2024-03-01 | 深圳深爱半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116313807A (en) * | 2023-02-28 | 2023-06-23 | 上海维安半导体有限公司 | Preparation method of super-junction device with double-layer side wall structure and super-junction device |
| CN116313807B (en) * | 2023-02-28 | 2024-05-28 | 上海维安半导体有限公司 | Preparation method of super-junction power MOSFET device with double-layer side wall structure and super-junction power MOSFET device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113659010B (en) | 2022-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9240469B2 (en) | Transverse ultra-thin insulated gate bipolar transistor having high current density | |
| CN106653836B (en) | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same | |
| CN108321196B (en) | Trench gate charge storage type IGBT and manufacturing method thereof | |
| CN113659010B (en) | MOSFET device integrated with RC absorption structure and manufacturing method | |
| CN105161539A (en) | Silicon carbide metal-oxide-semiconductor field-effect-transistor (MOSFET) device and fabrication method thereof | |
| CN113611750B (en) | SOI transverse shimming high-voltage power semiconductor device, manufacturing method and application | |
| CN113808951B (en) | Anti-electromagnetic interference super-junction MOS device and manufacturing method thereof | |
| CN115224024B (en) | Super junction device of integrated gate-drain capacitor and manufacturing method | |
| CN105679816A (en) | Trench gate charge storage type IGBT and manufacturing method thereof | |
| CN105932055A (en) | Plane gate IGBT and manufacturing method therefor | |
| CN110444586B (en) | Trench gate IGBT device with shunt area and preparation method | |
| CN109065620B (en) | IGBT device with low Miller capacitance | |
| CN113838917A (en) | Three-dimensional split gate groove charge storage type IGBT and manufacturing method thereof | |
| US20150144990A1 (en) | Power semiconductor device and method of manufacturing the same | |
| CN110459596B (en) | Transverse insulated gate bipolar transistor and preparation method thereof | |
| CN113421922B (en) | Three-dimensional IGBT with grid self-clamping function and manufacturing method thereof | |
| CN103681824A (en) | Power semiconductor device | |
| CN113270474B (en) | Short-circuit anode lateral insulated gate bipolar transistor controlled by anode depletion region and manufacturing method thereof | |
| CN115036293A (en) | Anti-electromagnetic interference super junction power device and manufacturing method thereof | |
| CN111244179B (en) | anti-EMI super-junction VDMOS device | |
| CN114975612A (en) | SiC trench gate IGBT device with low electromagnetic interference noise and preparation method thereof | |
| CN114582965A (en) | Low-switching-loss power device structure and manufacturing method thereof | |
| CN108767001B (en) | Trench IGBT device with shielding gate | |
| CN111293168B (en) | IGBT device and manufacturing method thereof | |
| CN113421923A (en) | IGBT with grid self-clamping function and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240301 Address after: No. 3000, Qiantangjiang Road, Qidong Economic Development Zone, Nantong City, Jiangsu Province, 226200 Patentee after: JIANGSU JIEJIE MICROELECTRONICS Co.,Ltd. Country or region after: China Address before: 214000 b-221, China Sensor Network International Innovation Park, 200 Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province Patentee before: Jiejie Microelectronics (Wuxi) Technology Co.,Ltd. Country or region before: China |