CN115036293A - Anti-electromagnetic interference super junction power device and manufacturing method thereof - Google Patents
Anti-electromagnetic interference super junction power device and manufacturing method thereof Download PDFInfo
- Publication number
- CN115036293A CN115036293A CN202210968077.2A CN202210968077A CN115036293A CN 115036293 A CN115036293 A CN 115036293A CN 202210968077 A CN202210968077 A CN 202210968077A CN 115036293 A CN115036293 A CN 115036293A
- Authority
- CN
- China
- Prior art keywords
- conductive type
- conductive
- type
- column
- body region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 210000000746 body region Anatomy 0.000 claims description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 25
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The invention relates to an anti-electromagnetic interference super junction power device and a manufacturing method thereof. According to the invention, the first conductive type well region is arranged in the second conductive type column, so that the parasitic resistance in the second conductive type column is increased, and an RC (resistor-capacitor) circuit formed by the parasitic resistance and the drain-source capacitor can absorb ringing and suppress electromagnetic interference under the condition of not reducing the switching speed of a device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an anti-electromagnetic interference super junction power device and a manufacturing method thereof.
Background
A power-Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is required to be used in various high-power electric devices. In the power device, the depletion layer width is increased in proportion to the drift layer concentration in order to secure the withstand voltage, and the concentration of the drift layer has to be decreased as the withstand voltage becomes higher. On the other hand, if the drift density is low, the on-resistance is high, and the withstand voltage and the on-resistance are in a trade-off relationship. In such a power device, as one of device structures for improving the tradeoff between the withstand voltage and the on-resistance, there is a Super Junction (Super Junction) device structure. According to the super junction device structure, the P-type column and the N-type column are formed on the N-type epitaxial layer, the concentration of N-type impurities in the N-type column can be increased, the on-resistance can be reduced, the area of a chip can be reduced by reducing the on-resistance, the capacitance is reduced, and a power device with high switching speed can be formed.
However, there is a trade-off relationship between switching speed and ringing upon switching. The ringing at the time of switching causes Electromagnetic Interference (EMI) noise and the like. Thus, the faster the switching speed, the more problems are caused by ringing. In recent years, as power devices having a high switching speed have been increasing, improvement of the problem of ringing has been desired.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an anti-electromagnetic interference super junction power device and a manufacturing method thereof.
According to the technical scheme provided by the invention, the super junction power device capable of resisting electromagnetic interference comprises a first conduction type substrate, a first conduction type epitaxial layer, an insulating medium layer and source electrode metal which are sequentially arranged from bottom to top, wherein the first conduction type substrate is connected with a drain electrode potential, the first conduction type epitaxial layer is arranged between the first conduction type substrate and the insulating medium layer, the insulating medium layer is arranged between the first conduction type epitaxial layer and the source electrode metal, a contact hole is arranged in the insulating medium layer, a first conduction type column and a second conduction type column are arranged at one end, close to the insulating medium layer, of the first conduction type epitaxial layer, the first conduction type column and the second conduction type column are arranged at intervals, a first conduction type well region is arranged in the second conduction type column, and the distance from one side, far away from the insulating medium layer, of the first conduction type well region to the upper surface of the first conduction type epitaxial layer is 0.5-5 micrometers, one side of the first conduction type well region, which is close to the insulating medium layer, is 0-4.5 microns away from the upper surface of the first conduction type epitaxial layer;
the super-junction power device is of a planar gate super-junction structure, a second conductive type body region is arranged at the top of a second conductive type column and is positioned above the first conductive type well region, the first conductive type column is arranged on two sides of the second conductive type body region, a first conductive type source region is arranged at one end, away from the first conductive type well region, of the second conductive type body region, a gate oxide layer is arranged between the first conductive type epitaxial layer and an insulating medium layer, the gate oxide layer covers the first conductive type column and the second conductive type body region except the first conductive type source region, gate conductive polycrystalline silicon is arranged above the gate oxide layer, the gate conductive polycrystalline silicon is arranged between the gate oxide layer and the insulating medium layer, and the insulating medium layer covers the gate conductive polycrystalline silicon and the first conductive type source region, the contact hole penetrates through the insulating medium layer and the first conduction type source region and enters the second conduction type body region, and the source metal is in ohmic contact with the first conduction type source region and the second conduction type body region through the contact hole;
or, the super-junction power device is a trench gate super-junction structure, a second conductive type body region is arranged at the top of a first conductive type column, the second conductive type body region is connected with the second conductive type column, a gate trench is arranged at the top of the first conductive type column, the gate trench penetrates through a first conductive type source region and the second conductive type body region to enter the first conductive type column, a gate oxide layer is arranged on the side wall and the bottom of the gate trench, gate conductive polysilicon is arranged in the gate oxide layer, a first conductive type source region is arranged on the surface of the second conductive type body region, the first conductive type source region is positioned at two sides of the gate trench, the insulating medium layer covers the second conductive type body region, the first conductive type source region, the gate trench and the second conductive type column, and the contact hole penetrates through the insulating medium layer and the first conductive type source region to enter the second conductive type body region, the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region through the contact hole.
The resistivity of the first conductivity type well region is greater than 0.5 ohms cm.
The width of the first conductivity type well region is 0.3 to 3 microns.
The manufacturing method when the super junction structure is a plane gate super junction structure comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, growing a first conductive type epitaxial layer on the first conductive type substrate, and then selectively etching a plurality of deep grooves with equal intervals on the first conductive type epitaxial layer, wherein the region between the adjacent deep grooves is a first conductive type column;
step two: filling the deep groove with second conductive type monocrystalline silicon, and forming a second conductive type monocrystalline silicon layer on the upper surface of the first conductive type column;
step three: etching to remove the second conductive type monocrystalline silicon on the upper surface of the first conductive type column and above the deep trench, and reserving the second conductive type monocrystalline silicon column in the lower deep trench, namely the second conductive type column;
step four: selectively implanting high-energy first conductive type impurities into the upper surface of the second conductive type column to form a first conductive type well region in the second conductive type column;
step five: selectively injecting second conductive type impurities above the second conductive type column, forming a second conductive type body region on the surface of the second conductive type column after annealing, then forming a gate oxide layer above the second conductive type body region and the first conductive type column, then depositing conductive polysilicon above the gate oxide layer, and finally selectively etching to remove the conductive polysilicon above the central position of the second conductive type body region, and forming gate conductive polysilicon by the left conductive polysilicon;
step six: implanting first conductive type impurities into the central position of the second conductive type body region and the upper surface of the grid conductive polycrystalline silicon, and forming a first conductive type source region on the upper surface of the central position of the second conductive type body region after activation;
step seven: depositing an insulating medium above the first conduction type source region and the grid conducting polycrystalline silicon to form an insulating medium layer, and then selectively etching a contact hole on the insulating medium layer, wherein the contact hole penetrates through the insulating medium layer and the first conduction type source region and enters the second conduction type body region;
step eight: and forming source metal above the insulating medium layer, wherein the contact hole is filled with the source metal.
The manufacturing method when the super junction structure is a trench gate super junction structure comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, growing a first conductive type epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities into the upper surface of the first conductive type epitaxial layer, and forming a second conductive type body region on the upper surface of the first conductive type epitaxial layer after annealing;
step two: selectively etching a plurality of deep grooves with equal intervals on the upper surface of the second conduction type body region, wherein the deep grooves penetrate through the second conduction type body region and enter the first conduction type epitaxial layer, and the region between the adjacent deep grooves is a first conduction type column;
step three: filling the deep groove with second conductive type monocrystalline silicon, and forming a second conductive type monocrystalline silicon layer on the upper surface of the second conductive type body region;
step four: etching to remove the second conductive type monocrystalline silicon on the upper surface of the second conductive type body region and above the deep groove, and reserving a second conductive type monocrystalline silicon column in the deep groove, namely a second conductive type column;
step five: selectively implanting high-energy first conductive type impurities into the upper surface of the second conductive type column to form a first conductive type well region in the second conductive type column;
step six: selectively etching a grid electrode groove on the upper surface of a second conductive type body region at the top of the first conductive type column, enabling the grid electrode groove to penetrate through the second conductive type body region and enter the first conductive type column, then forming a grid oxide layer on the side wall and the bottom of the grid electrode groove, then depositing conductive polycrystalline silicon on the surface of the grid oxide layer, filling the grid electrode groove with the conductive polycrystalline silicon, and finally etching and removing the conductive polycrystalline silicon above the grid electrode groove to form grid electrode conductive polycrystalline silicon;
step seven: selectively injecting first conductive type impurities into the upper surface of the second conductive type body region at two sides of the grid groove, and forming a first conductive type source region after activation;
step eight: depositing an insulating medium above the first conduction type source region, the second conduction type body region, the second conduction type column and the grid groove to form an insulating medium layer, and then selectively etching a contact hole on the insulating medium layer, wherein the contact hole penetrates through the insulating medium layer and the first conduction type source region and enters the second conduction type body region;
step nine: and forming source metal above the insulating medium layer, wherein the contact hole is filled with the source metal.
According to the invention, the first conductive type well region is arranged in the second conductive type column, so that the parasitic resistance in the second conductive type column is increased, and the RC circuit formed by the parasitic resistance and the drain-source capacitor can absorb ringing. The method is simple in implementation mode and compatible with the existing process.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional structure diagram of embodiment 2 of the present invention.
Fig. 3 is an internal circuit diagram of a superjunction device structure according to the present invention.
Fig. 4 is a graph comparing the gate voltage waveforms of the structure of the planar gate super junction device of embodiment 1 of the present invention with those of the conventional structure of planar gate super junction device when the device is turned on.
Fig. 5 is a graph comparing gate voltage waveforms of the trench gate superjunction device structure of embodiment 2 of the present invention with those of the conventional trench gate superjunction device structure when the device is turned on.
Fig. 6 is a diagram of the hole current path in the P-type column at the switching instant of the device in embodiment 1 of the present invention.
Fig. 7 is a diagram of the hole current path in the P-type column at the switching instant of the device in embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.
When the power device is an N-type power device, the first conduction type is an N type, and the second conduction type is a P type; or, when the power device is a P-type power device, the first conductivity type is a P-type, and the second conductivity type is an N-type. In the following embodiments, an N-type power semiconductor device is taken as an example, the first conductivity type is N-type, and the second conductivity type is P-type.
Example 1
A super-junction power device capable of resisting electromagnetic interference is of a planar gate super-junction structure and comprises an N-type substrate 1, an N-type epitaxial layer 2, an insulating medium layer 10 and a source metal 11 which are sequentially arranged from bottom to top, the N-type substrate 1 is connected with a drain potential, the N-type epitaxial layer 2 is arranged between the N-type substrate 1 and the insulating medium layer 10, the insulating medium layer 10 is arranged between the N-type epitaxial layer 2 and the source metal 11, a contact hole 12 is formed in the insulating medium layer 10, an N-type column 4 and a P-type column 3 are arranged at one end, close to the insulating medium layer 10, of the N-type epitaxial layer 2, the N-type column 4 and the P-type column 3 are arranged at intervals, and the P-type column 3 is formed by deep trench etching epitaxial filling.
The top of the P-type column 3 is provided with a P-type body region 6, two sides of the P-type body region 6 are provided with N-type columns 4, the N-type well region 5 is a high-resistance region formed after phosphorus is injected on the surface of the P-type column 3 under the injection condition of 2100keV 3e12 (energy 2100 kiloelectron volts, dosage 3e 12), the resistivity of the N-type well region 5 is greater than 0.5 ohm centimeter so as to prevent the N-type well region 5 from influencing the breakdown voltage of a device, the distance from the lower surface of the N-type well region 5 to the insulating medium layer 10 is 3 micrometers, the distance from the upper surface to the insulating medium layer 10 is 1.5 micrometers, the N-type well region 5 has a thickness of 1.5 micrometers in the longitudinal direction, the N-type well region 5 has a width of 2.5 micrometers in the transverse direction, and the P-type body region 6 is positioned above the N-type well region 5.
Be equipped with N type source region 7 in P type body district 6, N type source region 7 sets up the one end of keeping away from N type trap area 5 in P type body district 6, and is located the central point of P type body district 6 puts be equipped with gate oxide layer 8 between N type epitaxial layer 2 and the dielectric layer 10, just gate oxide layer 8 covers in the top of N type post 4 and the top of P type body district 6 except that N type source district 7 the top of gate oxide layer 8 is equipped with grid conductive polysilicon 9, grid conductive polysilicon 9 sets up between gate oxide layer 8 and dielectric layer 10, dielectric layer 10 covers grid conductive polysilicon 9 and N type source district 7, and contact hole 12 pierces through dielectric layer 10 and N type source district 7 and gets into in P type body district 6, source metal 11 passes through contact hole 12 and N type source district 7 and the ohmic contact of P type body district 6 with N type source district 7.
As shown in fig. 6, which is a path diagram of hole current in the P-type pillar at the moment of switching the device, during the switching of the device, the hole current moves from the bottom of the P-type pillar to the P-type body region along the center of the P-type pillar, and the hole current passes through the N-type well region as the high resistance region. The PN junction capacitance of a PN diode formed by the P-type column and the N-type column and the parasitic resistance of the P-type column form an RC absorption circuit, the larger the parasitic resistance of the P-type column is, the better the ringing absorption effect of the RC absorption circuit is, the N-type trap area increases the parasitic resistance of the P-type column, so the embodiment can inhibit ringing, and if the thickness of the N-type trap area is increased, the ringing inhibition capability of the embodiment can be further increased.
The conventional planar gate super junction device structure is not provided with an N-type well region, and as shown in fig. 4, a comparison graph of gate voltage waveforms of the conventional planar gate super junction device structure and the present embodiment when the device is turned on is shown, and ringing is significantly suppressed in the present embodiment.
The manufacturing method of the present embodiment includes the steps of:
the method comprises the following steps: providing an N-type substrate 1, growing an N-type epitaxial layer 2 on the N-type substrate 1, and then selectively etching a plurality of deep trenches with equal intervals on the N-type epitaxial layer 2, wherein an N-type column 4 is arranged in a region between every two adjacent deep trenches;
step two: filling the deep trench with P-type monocrystalline silicon, and forming a P-type monocrystalline silicon layer on the upper surface of the N-type column 4;
step three: etching to remove the P-type monocrystalline silicon on the upper surface of the N-type column 4 and above the deep groove, and reserving the P-type monocrystalline silicon column in the deep groove, namely the P-type column 3;
step four: selectively injecting N-type impurities into the upper surface of the P-type column 3 at high energy to form an N-type well region 5 in the P-type column 3;
step five: selectively injecting P-type impurities above the P-type column 3, forming a P-type body region 6 on the surface of the P-type column 3 after annealing, then forming a gate oxide layer 8 above the P-type body region 6 and the N-type column 4, then depositing conductive polysilicon above the gate oxide layer 8, finally selectively etching to remove the conductive polysilicon above the central position of the P-type body region 6, and forming gate conductive polysilicon 9 by the left conductive polysilicon;
step six: injecting N-type impurities into the center of the P-type body region 6 and the upper surface of the grid conductive polycrystalline silicon 9, and forming an N-type source region 7 on the upper surface of the center of the P-type body region 6 after activation;
step seven: depositing an insulating medium above the N-type source region 7 and the grid conductive polysilicon 9 to form an insulating medium layer 10, and then selectively etching a contact hole 12 on the insulating medium layer 10, wherein the contact hole 12 penetrates through the insulating medium layer 10 and the N-type source region 7 and enters the P-type body region 6;
step eight: and forming a source metal 11 above the insulating medium layer 10, wherein the contact hole 12 is filled with the source metal 11.
Example 2
A super-junction power device capable of resisting electromagnetic interference is of a trench gate super-junction structure and comprises an N-type substrate 1, an N-type epitaxial layer 2, an insulating medium layer 10 and a source metal 11 which are sequentially arranged from bottom to top, wherein the N-type substrate 1 is connected with a drain potential, the N-type epitaxial layer 2 is arranged between the N-type substrate 1 and the insulating medium layer 10, the insulating medium layer 10 is arranged between the N-type epitaxial layer 2 and the source metal 11, a contact hole 12 is formed in the insulating medium layer 10, an N-type column 4 and a P-type column 3 are arranged at one end, close to the insulating medium layer 10, of the N-type epitaxial layer 2, the N-type column 4 and the P-type column 3 are arranged at intervals, and the P-type column 3 is formed by deep trench etching epitaxial filling.
Phosphorus is implanted on the upper surface of the P-type pillars 3 under the implantation condition of 2100keV 3e12, and then N-well regions 5 are formed in the P-type pillars 3, wherein the shape of the N-well regions 5 is the same as that of embodiment 1.
The top of the N-type column 4 is provided with a P-type body region 6, the P-type body region 6 is connected with the P-type column 3, the top of the N-type column 4 is provided with a grid groove 13, the grid groove 13 penetrates through the N-type source region 7 and the P-type body region 6 to enter the N-type column 4, the side wall and the bottom of the grid groove 13 are provided with a grid oxide layer 8, grid conductive polycrystalline silicon 9 is arranged in the grid oxide layer 8, the surface of the P-type body region 6 is provided with the N-type source region 7, the N-type source region 7 is located on two sides of the grid groove 13, the insulating medium layer 10 covers the P-type body region 6, the N-type source region 7, the grid groove 13 and the P-type column 3, the contact hole 12 penetrates through the insulating medium layer 10 and the N-type source region 7 to enter the P-type body region 6, and the source metal 11 is in ohmic contact with the N-type source region 7 and the P-type body region 6 through the contact hole 12.
As shown in fig. 7, which is a path diagram of hole current in the P-type pillar at the moment of switching the device in this embodiment, the hole current moves from the bottom of the P-type pillar to the P-type body region during the switching of the device, and the hole current bypasses the N-type well region which is a high resistance region, and flows through the narrow P-type pillar between the N-type well region and the N-type pillar, and the parasitic resistance in this region is also large because this region is too narrow. The parasitic resistance of the P-type column is increased by the narrow P-type column between the N-type well region and the N-type column, the RC absorption circuit is formed by the parasitic resistance and the PN junction capacitance of the PN diode formed by the P-type column and the N-type column, the larger the parasitic resistance of the P-type column is, the better the ringing absorption effect of the RC absorption circuit is, the parasitic resistance of the P-type column is increased by the N-type well region, so the ringing can be inhibited by the embodiment, and if the width of the N-type well region is further increased, the ringing inhibition capability of the embodiment can be further increased.
The conventional trench gate super junction device structure is not provided with an N-type well region, and as shown in fig. 5, a comparison graph of gate voltage waveforms of the present embodiment and the conventional trench gate super junction device structure when the device is turned on is shown, and the present embodiment can significantly suppress ringing.
The manufacturing method of the present embodiment includes the steps of:
the method comprises the following steps: providing an N-type substrate 1, growing an N-type epitaxial layer 2 on the N-type substrate 1, then injecting P-type impurities into the upper surface of the N-type epitaxial layer 2, and forming a P-type body region 6 on the upper surface of the N-type epitaxial layer 2 after annealing;
step two: selectively etching a plurality of deep grooves with equal intervals on the upper surface of the P-type body region 6, wherein the deep grooves penetrate through the P-type body region 6 and enter the N-type epitaxial layer 2, and the region between the adjacent deep grooves is an N-type column 4;
step three: filling the deep trench with P-type monocrystalline silicon, and forming a P-type monocrystalline silicon layer on the upper surface of the P-type body region 6;
step four: etching to remove the P-type monocrystalline silicon on the upper surface of the P-type body region 6 and above the deep groove, and reserving a P-type monocrystalline silicon column in the deep groove, namely the P-type column 3;
step five: selectively injecting N-type impurities into the upper surface of the P-type column 3 at high energy to form an N-type well region 5 in the P-type column 3;
step six: selectively etching a gate trench 13 on the upper surface of the P-type body region 6 at the top of the N-type column 4, wherein the gate trench 13 penetrates through the P-type body region 6 and enters the N-type column 4, then forming a gate oxide layer 8 on the side wall and the bottom of the gate trench 13, then depositing conductive polysilicon on the surface of the gate oxide layer 8, filling the gate trench 13 with the conductive polysilicon, and finally etching to remove the conductive polysilicon above the gate trench 13 to form a gate conductive polysilicon 9;
step seven: selectively injecting N-type impurities into the upper surfaces of the P-type body regions 6 on the two sides of the grid groove 13, and forming an N-type source region 7 after activation;
step eight: depositing an insulating medium above the N-type source region 7, the P-type body region 6, the P-type column 3 and the grid groove 13 to form an insulating medium layer 10, and then selectively etching a contact hole 12 on the insulating medium layer 10, wherein the contact hole 12 penetrates through the insulating medium layer 10 and the N-type source region 7 and enters the P-type body region 6;
step nine: and forming a source metal 11 above the insulating medium layer 10, wherein the contact hole 12 is filled with the source metal 11.
The internal circuit diagram of the super junction device structure related by the invention is shown in fig. 3, a Drain-Source capacitance Cds and a distributed resistance Rs exist between a Drain Drain and a Source, the Drain-Source capacitance Cds is the junction capacitance of a PN junction formed by a P-type column and an N-type column, and the distributed resistance Rs is the parasitic resistance of the P-type column. Because the parasitic resistance of the P-type column of the traditional super junction device structure is extremely small, the RC circuit formed by the Cds and the Rs cannot remarkably inhibit ringing; according to the super junction device structure, the distributed resistance Rs is increased through the N-type well region, so that the RC circuit formed by the CdS and the Rs can remarkably suppress ringing.
Those of ordinary skill in the art will understand that: the above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit of the present invention should be included in the scope of the present invention.
Claims (5)
1. The anti-electromagnetic interference super-junction power device comprises a first conductive type substrate, a first conductive type epitaxial layer, an insulating medium layer and source metal, wherein the first conductive type substrate, the first conductive type epitaxial layer, the insulating medium layer and the source metal are sequentially arranged from bottom to top, the first conductive type substrate is connected with a drain potential, the first conductive type epitaxial layer is arranged between the first conductive type substrate and the insulating medium layer, the insulating medium layer is arranged between the first conductive type epitaxial layer and the source metal, a contact hole is formed in the insulating medium layer, a first conductive type column and a second conductive type column are arranged at one end, close to the insulating medium layer, of the first conductive type epitaxial layer, and the first conductive type column and the second conductive type column are arranged at intervals, and the super-junction power device is characterized in that: a first conduction type well region is arranged in the second conduction type column, one side of the first conduction type well region, which is far away from the insulating medium layer, is 0.5-5 micrometers away from the upper surface of the first conduction type epitaxial layer, and one side of the first conduction type well region, which is close to the insulating medium layer, is 0-4.5 micrometers away from the upper surface of the first conduction type epitaxial layer;
the super-junction power device is of a plane gate super-junction structure, a second conductive type body region is arranged at the top of a second conductive type column and is positioned above the first conductive type well region, the first conductive type column is arranged on two sides of the second conductive type body region, a first conductive type source region is arranged at one end, far away from the first conductive type well region, of the second conductive type body region, a gate oxide layer is arranged between the first conductive type epitaxial layer and an insulating medium layer, the gate oxide layer covers the first conductive type column and the second conductive type body region except the first conductive type source region, gate conductive polycrystalline silicon is arranged above the gate oxide layer, the gate conductive polycrystalline silicon is arranged between the gate oxide layer and the insulating medium layer, and the insulating medium layer covers the gate conductive polycrystalline silicon and the first conductive type source region, the contact hole penetrates through the insulating medium layer and the first conduction type source region to enter the second conduction type body region, and the source metal is in ohmic contact with the first conduction type source region and the second conduction type body region through the contact hole;
or, the super-junction power device is a trench gate super-junction structure, a second conductive type body region is arranged at the top of a first conductive type column, the second conductive type body region is connected with the second conductive type column, a gate trench is arranged at the top of the first conductive type column, the gate trench penetrates through a first conductive type source region and the second conductive type body region to enter the first conductive type column, a gate oxide layer is arranged on the side wall and the bottom of the gate trench, gate conductive polysilicon is arranged in the gate oxide layer, a first conductive type source region is arranged on the surface of the second conductive type body region, the first conductive type source region is positioned at two sides of the gate trench, the insulating medium layer covers the second conductive type body region, the first conductive type source region, the gate trench and the second conductive type column, and the contact hole penetrates through the insulating medium layer and the first conductive type source region to enter the second conductive type body region, the source metal is in ohmic contact with the first conductive type source region and the second conductive type body region through the contact hole.
2. The electromagnetic interference resistant superjunction power device of claim 1, wherein: the resistivity of the first conductivity type well region is greater than 0.5 ohms cm.
3. The electromagnetic interference resistant superjunction power device of claim 1, wherein: the width of the first conductivity type well region is 0.3 to 3 microns.
4. The method for manufacturing an electromagnetic interference resistant super-junction power device according to claim 1, wherein when the super-junction power device is a planar gate super-junction structure, the method comprises the following steps:
the method comprises the following steps: providing a first conduction type substrate, growing a first conduction type epitaxial layer on the first conduction type substrate, and then selectively etching a plurality of deep grooves with equal intervals on the first conduction type epitaxial layer, wherein the region between the adjacent deep grooves is a first conduction type column;
step two: filling the deep trench with second conductivity type monocrystalline silicon, and forming a second conductivity type monocrystalline silicon layer on the upper surface of the first conductivity type column;
step three: etching to remove the second conductive type monocrystalline silicon on the upper surface of the first conductive type column and above the deep trench, and reserving the second conductive type monocrystalline silicon column in the lower deep trench, namely the second conductive type column;
step four: selectively implanting high-energy first conductive type impurities into the upper surface of the second conductive type column to form a first conductive type well region in the second conductive type column;
step five: selectively injecting second conductive type impurities above the second conductive type column, forming a second conductive type body region on the surface of the second conductive type column after annealing, then forming a gate oxide layer above the second conductive type body region and the first conductive type column, then depositing conductive polysilicon above the gate oxide layer, and finally selectively etching to remove the conductive polysilicon above the central position of the second conductive type body region, and forming gate conductive polysilicon by the left conductive polysilicon;
step six: implanting first conductive type impurities into the central position of the second conductive type body region and the upper surface of the grid conductive polycrystalline silicon, and forming a first conductive type source region on the upper surface of the central position of the second conductive type body region after activation;
step seven: depositing an insulating medium above the first conduction type source region and the grid conductive polysilicon to form an insulating medium layer, and then selectively etching a contact hole on the insulating medium layer, wherein the contact hole penetrates through the insulating medium layer and the first conduction type source region and enters the second conduction type body region;
step eight: and forming source metal above the insulating medium layer, wherein the contact hole is filled with the source metal.
5. The method for manufacturing the electromagnetic interference resistant super junction power device of claim 1, wherein when the super junction power device is a trench gate super junction structure, the method comprises the following steps:
the method comprises the following steps: providing a first conductive type substrate, growing a first conductive type epitaxial layer on the first conductive type substrate, then injecting second conductive type impurities into the upper surface of the first conductive type epitaxial layer, and forming a second conductive type body region on the upper surface of the first conductive type epitaxial layer after annealing;
step two: selectively etching a plurality of deep grooves with equal intervals on the upper surface of the second conduction type body region, wherein the deep grooves penetrate through the second conduction type body region and enter the first conduction type epitaxial layer, and the region between the adjacent deep grooves is a first conduction type column;
step three: filling the deep groove with second conductive type monocrystalline silicon, and forming a second conductive type monocrystalline silicon layer on the upper surface of the second conductive type body region;
step four: etching to remove the second conductive type monocrystalline silicon on the upper surface of the second conductive type body region and above the deep groove, and reserving a second conductive type monocrystalline silicon column in the deep groove, namely a second conductive type column;
step five: selectively implanting high-energy first conductive type impurities into the upper surface of the second conductive type column to form a first conductive type well region in the second conductive type column;
step six: selectively etching a grid electrode groove on the upper surface of a second conductive type body region at the top of the first conductive type column, enabling the grid electrode groove to penetrate through the second conductive type body region and enter the first conductive type column, then forming a grid oxide layer on the side wall and the bottom of the grid electrode groove, then depositing conductive polycrystalline silicon on the surface of the grid oxide layer, filling the grid electrode groove with the conductive polycrystalline silicon, and finally etching and removing the conductive polycrystalline silicon above the grid electrode groove to form grid electrode conductive polycrystalline silicon;
step seven: selectively injecting first conductive type impurities into the upper surface of the second conductive type body region at two sides of the grid groove, and forming a first conductive type source region after activation;
step eight: depositing an insulating medium above the first conduction type source region, the second conduction type body region, the second conduction type column and the grid groove to form an insulating medium layer, and then selectively etching a contact hole on the insulating medium layer, wherein the contact hole penetrates through the insulating medium layer and the first conduction type source region and enters the second conduction type body region;
step nine: and forming source metal above the insulating medium layer, wherein the contact holes are filled with the source metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210968077.2A CN115036293B (en) | 2022-08-12 | 2022-08-12 | Anti-electromagnetic interference super junction power device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210968077.2A CN115036293B (en) | 2022-08-12 | 2022-08-12 | Anti-electromagnetic interference super junction power device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115036293A true CN115036293A (en) | 2022-09-09 |
| CN115036293B CN115036293B (en) | 2022-11-04 |
Family
ID=83130103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210968077.2A Active CN115036293B (en) | 2022-08-12 | 2022-08-12 | Anti-electromagnetic interference super junction power device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115036293B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115579398A (en) * | 2022-12-06 | 2023-01-06 | 无锡新洁能股份有限公司 | Shielding grid power device with deep contact hole |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060256487A1 (en) * | 2005-03-08 | 2006-11-16 | Fuji Electric Holding Co., Ltd. | Semiconductor superjunction device |
| CN112928156A (en) * | 2021-04-07 | 2021-06-08 | 四川大学 | Floating p-column reverse-conducting type grooved gate super-junction IGBT |
| CN217009199U (en) * | 2022-03-11 | 2022-07-19 | 无锡新洁能股份有限公司 | Super junction power semiconductor transistor device |
-
2022
- 2022-08-12 CN CN202210968077.2A patent/CN115036293B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060256487A1 (en) * | 2005-03-08 | 2006-11-16 | Fuji Electric Holding Co., Ltd. | Semiconductor superjunction device |
| CN112928156A (en) * | 2021-04-07 | 2021-06-08 | 四川大学 | Floating p-column reverse-conducting type grooved gate super-junction IGBT |
| CN217009199U (en) * | 2022-03-11 | 2022-07-19 | 无锡新洁能股份有限公司 | Super junction power semiconductor transistor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115579398A (en) * | 2022-12-06 | 2023-01-06 | 无锡新洁能股份有限公司 | Shielding grid power device with deep contact hole |
| CN115579398B (en) * | 2022-12-06 | 2023-03-10 | 无锡新洁能股份有限公司 | Shielding grid power device with deep contact hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115036293B (en) | 2022-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI453919B (en) | Diode structures with controlled injection efficiency for fast switching | |
| US8482062B2 (en) | Semiconductor device having a floating semiconductor zone | |
| WO2015022989A1 (en) | Semiconductor device | |
| US9685523B2 (en) | Diode structures with controlled injection efficiency for fast switching | |
| CN101385147A (en) | Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout | |
| US9293559B2 (en) | Dual trench-gate IGBT structure | |
| CN103165604A (en) | Semiconductor component with a space saving edge structure | |
| US9502547B2 (en) | Charge reservoir IGBT top structure | |
| CN114628515A (en) | SiC MOSFET device and manufacturing method | |
| CN115036293B (en) | Anti-electromagnetic interference super junction power device and manufacturing method thereof | |
| CN108598151B (en) | Semiconductor device terminal structure capable of improving voltage endurance capability and manufacturing method thereof | |
| CN116504817B (en) | RC-IGBT structure with high switching speed and low loss and preparation method thereof | |
| CN113838917A (en) | Three-dimensional split gate groove charge storage type IGBT and manufacturing method thereof | |
| CN112635548A (en) | Terminal structure of trench MOSFET device and manufacturing method | |
| CN116053300B (en) | Super junction device, manufacturing method thereof and electronic device | |
| CN116031303B (en) | Super junction device, manufacturing method thereof and electronic device | |
| KR101550798B1 (en) | Power semiconductor device having structure for preventing latch-up and method of manufacture thereof | |
| GB2585696A (en) | Semiconductor device and method for producing same | |
| US11804524B2 (en) | Semiconductor device and method for producing same | |
| JP2016046416A (en) | Semiconductor device | |
| KR20150076716A (en) | Power semiconductor device | |
| CN210607276U (en) | Groove type power device based on Schottky structure | |
| CN114388612A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN113659008A (en) | Shimming device with electric field clamping layer and manufacturing method and application thereof | |
| EP3953972A1 (en) | Reverse conducting igbt with controlled anode injection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |