CN109509792A - Optimize the super node MOSFET domain structure and manufacturing method of EMI - Google Patents
Optimize the super node MOSFET domain structure and manufacturing method of EMI Download PDFInfo
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- CN109509792A CN109509792A CN201811188014.5A CN201811188014A CN109509792A CN 109509792 A CN109509792 A CN 109509792A CN 201811188014 A CN201811188014 A CN 201811188014A CN 109509792 A CN109509792 A CN 109509792A
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- emi
- super node
- manufacturing
- node mosfet
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 238000005457 optimization Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 2
- 230000009514 concussion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The present invention relates to the super node MOSFET domain structures and manufacturing method of optimization EMI, and this method is by poly Butut, in conjunction with P-body autoregistration injection technology, reach the Cgd for increasing MOSFET, reduce dv/dt, improve the purpose of device EMI performance, while eliminating one layer body editions.The present invention is by special poly Butut, in conjunction with P-body autoregistration injection technology, can achieve the Cgd for increasing MOSFET, reduces dv/dt, improve the purpose of device EMI performance, while eliminating one layer body editions, reduces the production cost of product；By emulation, the Cgd of structure is obviously increased, so that dv/dt reduces, EMI performance boost in device use process.
Description
Technical field
The present invention relates to a kind of super node MOSFET structures, and in particular to a kind of super node MOSFET domain structure for optimizing EMI
And manufacturing method.
Background technique
Super node MOSFET possesses lower than conducting resistance (Rsp), under the conditions of identical BV and Rdson, super node MOSFET
Chip area it is smaller, cost is lower, while grid charge is also smaller, effectively reduces the switching loss of product.But it switchs
Speed accelerates meeting so that the electromagnetic interference (EMI) of super node MOSFET is greater than plane VDMOSFET, in some circuit topologies, shadow
The process of super node MOSFET substitutive patterns VDMOSFET is rung.On the other hand, with the progress of super node MOSFET design and craft,
More smaller and smaller than conducting resistance, chip area and grid charge also become smaller and smaller, and switching speed is constantly accelerated, and answers product
There is higher requirement with topological circuit design, the ease for use of product can be improved in the EMI characteristic for improving product, reduces terminal work
The design difficulty of Cheng Shi, the more conducively popularization of product.
Summary of the invention
The object of the present invention is to provide a kind of super node MOSFET domain structures and manufacturing method for optimizing EMI, pass through domain
Products C gd is optimized and revised, dv/dt during reducing switch mosfet is reached, grid concussion is reduced, improves device EMI performance
Effect.
The technical scheme adopted by the invention is as follows:
Optimize the manufacturing method of the super node MOSFET domain structure of EMI, it is characterised in that:
This method is by poly Butut, in conjunction with P-body autoregistration injection technology, reaches the Cgd for increasing MOSFET, reduces dv/
Dt, improves the purpose of device EMI performance, while eliminating one layer body editions.
With being realized by following steps:
Step 1: growing extension N- on N+ substrate；
Step 2: etching deep trench by Trench photolithography plate, then growing P-type extension, being allowed to fill full groove, go forward side by side
Row CMP process is removed p-type extension is extended to outside the N-type outside groove, constitutes the staggered super-junction structure of N column P column；
Step 3: deposit field oxide and time quarter, are returned by grid oxygen, polycrystalline silicon deposit and form gate at quarter, standard automatically is then utilized
Technique carries out the injection of Boron and annealing forms the area body, and reticle is recycled to define injection window, injects As or P and pushes away
Trap forms the area Nsource；
Step 4: deposit ILD and time quarter, hole note, finally deposit metal and return quarter, form the final structure of device.
The super node MOSFET domain structure of manufacturing method optimization EMI obtained as mentioned.
The invention has the following advantages that
The present invention is by special poly Butut, in conjunction with P-body autoregistration injection technology, can achieve and increases MOSFET's
Cgd reduces dv/dt, improves the purpose of device EMI performance, while eliminating one layer body editions, reduces being produced into for product
This.By emulation, the Cgd of structure is obviously increased, so that dv/dt reduces, EMI performance boost in device use process.
Detailed description of the invention
Fig. 1 is poly domain.
Fig. 2 is the device profile map in the direction Fig. 1 AA.
Fig. 3 is step 1 schematic diagram.
Fig. 4 is step 2 schematic diagram.
Fig. 5 is step 3 schematic diagram.
Fig. 6 is device simulation schematic diagram.
Specific embodiment
The present invention will be described in detail With reference to embodiment.
The present invention relates to a kind of super node MOSFET domain structures and manufacturing method for optimizing EMI, and wherein poly domain is as schemed
1, it is distributed in grid, increase can achieve in conjunction with P-body autoregistration injection technology by this special poly Butut
The Cgd of MOSFET reduces dv/dt, improves the purpose of device EMI performance, while eliminating one layer body editions, reduces product
Production cost.Wherein X1 and Y1 respectively represents the spacing of longitudinal poly He transverse direction poly, and X1 and Y1 can be the same or different,
Numerical value can be adjusted according to product demand.X2 and Y2 respectively represents the width of longitudinal poly He transverse direction poly, and X2 and Y2 can phases
With can also be different, numerical value can be adjusted according to product demand.Device profile map along the direction Fig. 1 AA (is only opened up as shown in Figure 2
Part in diagram 1 in box), the specific implementation process of the product are as follows:
Step 1: growing certain thickness extension N-(Fig. 3 on N+ substrate)；
Step 2: etching deep trench by Trench photolithography plate, then growing certain thickness p-type extension, it is full to be allowed to filling
Groove, and CMP process is carried out, remove p-type extension is extended to outside the N-type outside groove, constitutes the staggered superjunction knot of N column P column
Structure (Fig. 4)；
Step 3: deposit field oxide and time quarter, are returned by grid oxygen, polycrystalline silicon deposit and form gate at quarter, standard automatically is then utilized
Technique carries out the injection of Boron and annealing forms the area body, and reticle is recycled to define injection window, injects As(or P) simultaneously
It pushes away trap and forms the area Nsource (Fig. 5)；
Step 4: deposit ILD and time quarter, hole note, finally deposit metal and return quarter, form the final structure (Fig. 2) of device.
It by device simulation, compared under same case, the Cgd comparison before and after diagram optimizing, it can be seen that knot of the present invention
The Cgd of structure obviously increases (Fig. 6), so that dv/dt reduces, EMI performance boost in device use process.
Body has used automatic quasi- technique, only one of case study on implementation in present invention implementation, utilizes body editions progress body
The injection mode in region is also within the protection scope of this patent.Body injection sequence can before poly deposits etching or
Afterwards.
Poly editions are distributed in grid in the present invention, and wherein X1 and Y1 is respectively represented between longitudinal poly and transverse direction poly
Away from X1 and Y1 can be the same or different, and numerical value can be adjusted according to product demand.X2 and Y2 respectively represent longitudinal poly and
The width of lateral poly, X2 and Y2 can be the same or different, and numerical value can be adjusted according to product demand.
The contents of the present invention are not limited to cited by embodiment, and those of ordinary skill in the art are by reading description of the invention
And to any equivalent transformation that technical solution of the present invention is taken, all are covered by the claims of the invention.
Claims (3)
1. optimizing the manufacturing method of the super node MOSFET domain structure of EMI, it is characterised in that:
This method is by poly Butut, in conjunction with P-body autoregistration injection technology, reaches the Cgd for increasing MOSFET, reduces dv/
Dt, improves the purpose of device EMI performance, while eliminating one layer body editions.
2. the manufacturing method of the super node MOSFET domain structure of optimization EMI according to claim 1, it is characterised in that:
With being realized by following steps:
Step 1: growing extension N- on N+ substrate；
Step 2: etching deep trench by Trench photolithography plate, then growing P-type extension, being allowed to fill full groove, go forward side by side
Row CMP process is removed p-type extension is extended to outside the N-type outside groove, constitutes the staggered super-junction structure of N column P column；
Step 3: deposit field oxide and time quarter, are returned by grid oxygen, polycrystalline silicon deposit and form gate at quarter, standard automatically is then utilized
Technique carries out the injection of Boron and annealing forms the area body, and reticle is recycled to define injection window, injects As or P and pushes away
Trap forms the area Nsource；
Step 4: deposit ILD and time quarter, hole note, finally deposit metal and return quarter, form the final structure of device.
3. the super node MOSFET domain structure of manufacturing method as claimed in claim 1 or 2 optimization EMI obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811188014.5A CN109509792A (en) | 2018-10-12 | 2018-10-12 | Optimize the super node MOSFET domain structure and manufacturing method of EMI |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811188014.5A CN109509792A (en) | 2018-10-12 | 2018-10-12 | Optimize the super node MOSFET domain structure and manufacturing method of EMI |
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| Publication Number | Publication Date |
|---|---|
| CN109509792A true CN109509792A (en) | 2019-03-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811188014.5A Pending CN109509792A (en) | 2018-10-12 | 2018-10-12 | Optimize the super node MOSFET domain structure and manufacturing method of EMI |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130221426A1 (en) * | 2012-02-27 | 2013-08-29 | Kabushiki Kaisha Toshiba | Electric power semiconductor device and manufacturing method of the same |
| CN103325827A (en) * | 2012-03-23 | 2013-09-25 | 株式会社东芝 | Semiconductor device |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN106783590A (en) * | 2016-12-05 | 2017-05-31 | 西安龙腾新能源科技发展有限公司 | Snapback recovers the method and its device architecture of SJ MOS |
-
2018
- 2018-10-12 CN CN201811188014.5A patent/CN109509792A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130221426A1 (en) * | 2012-02-27 | 2013-08-29 | Kabushiki Kaisha Toshiba | Electric power semiconductor device and manufacturing method of the same |
| CN103325827A (en) * | 2012-03-23 | 2013-09-25 | 株式会社东芝 | Semiconductor device |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN106783590A (en) * | 2016-12-05 | 2017-05-31 | 西安龙腾新能源科技发展有限公司 | Snapback recovers the method and its device architecture of SJ MOS |
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Application publication date: 20190322 |
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