CN110176401B - Method for reducing production cost of VDMOS - Google Patents
Method for reducing production cost of VDMOS Download PDFInfo
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- CN110176401B CN110176401B CN201910511087.1A CN201910511087A CN110176401B CN 110176401 B CN110176401 B CN 110176401B CN 201910511087 A CN201910511087 A CN 201910511087A CN 110176401 B CN110176401 B CN 110176401B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 28
- 210000000746 body region Anatomy 0.000 claims abstract description 42
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000010992 reflux Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 10
- 238000001459 lithography Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for reducing the production cost of a VDMOS (vertical double-diffused metal oxide semiconductor), which comprises the following steps of: A. making a ring region graph and a deep body region graph on the initial oxide layer by adopting photoresist, wherein the ring region graph and the deep body region graph form a photoetching opening region; B. etching the photoetching opening area to form a deep body area and a terminal ring; C. performing high-temperature driving to grow a secondary oxide layer; D. performing cell manufacturing of the VDMOS in the active region, reserving a secondary oxide layer, and preparing for manufacturing a subsequent source region and reducing 1 layer of photoetching; E. growing a grid oxide layer and depositing a polysilicon grid; F. etching the polysilicon gate, etching through the gate oxide layer to form a body region window to manufacture a body region, doping the polysilicon, and manufacturing a source region; on the premise of ensuring the performance of the device, the invention reduces one-time photoetching and deep body area manufacturing process to greatly reduce the cost by about 20 percent, thereby improving the market competitiveness of the device and having good market application value.
Description
Technical Field
The invention relates to the field of semiconductor chip manufacturing processes, in particular to a method for reducing the production cost of a VDMOS.
Background
The vertical double-diffused metal-oxide-semiconductor transistor has the advantages of a bipolar transistor and a common MOS device, and the VDMOS is an ideal power device no matter in switching application or linear application. The VDMOS is mainly used for inverters, electronic switches, high-fidelity sound equipment, automobile electric appliances, electronic ballasts and the like. The VDMOS is classified into an enhancement type VDMOS and a depletion type VDMOS.
With the development of the semiconductor design field and the semiconductor process field, the current VDMOS device has been developed towards the low cost and high performance field, and how to compress the cost as much as possible on the premise of ensuring the high performance is a main subject of each design company and foundry.
In the prior art, the VDMOS device manufacturing process includes the following steps:
as shown in fig. 1, S1, providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, growing an initial oxide layer on the N-type epitaxial layer, and patterning a ring region on the initial oxide layer of the ring region by using a photoresist;
s2, photoetching and etching the ring region pattern, and injecting P-type impurities into the ring region;
as shown in fig. 2, S3, removing the photoresist, performing high temperature drive-in, and simultaneously growing a secondary oxide layer to form a ring region of the device;
as shown in fig. 3, S4, removing the initial oxide layer in the active region by using the photoresist to protect the secondary oxide layer in the ring region and the deep body region, and performing a VDMOS cell fabrication in the active region;
the following steps are carried out in the active area:
as shown in fig. 4, S5, growing a gate oxide layer, and depositing a polysilicon gate on the gate oxide layer;
as shown in fig. 5, S6, polysilicon gate doping is performed;
as shown in fig. 6, S7, performing photolithography and etching on the polysilicon gate at the position where the body region is to be formed;
s8, carrying out body region injection and drive-in;
as shown in fig. 7, S9, performing photolithography of the source region;
as shown in fig. 8, S10, performing implantation of the source region, blocking a part of the body region with photoresist, performing implantation of the source region in other regions, and removing the photoresist after implantation to complete driving of the source region;
as shown in fig. 9, S11, depositing a dielectric layer, and reflowing the dielectric layer; and completing the etching of the contact hole;
s12, implanting and driving in the buried deep body region;
as shown in fig. 10, S13, metal lead is made.
As is well known, the manufacturing cost of a semiconductor device is mainly measured by the number of times of photoetching, and the invention introduces the manufacturing method of the planar VDMOS device, which can greatly reduce the cost by reducing one photoetching and deep body region manufacturing process on the premise of ensuring the function of the device, and the cost is reduced by about 20 percent, thereby improving the market competitiveness of the device.
The prior art has defects and needs to be improved.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a method for reducing the production cost of a VDMOS.
The technical scheme provided by the invention is a method for reducing the production cost of a VDMOS (vertical double-diffused metal oxide semiconductor), which comprises the following steps of:
A. providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, growing an initial oxide layer on the N-type epitaxial layer, making a ring region graph on the initial oxide layer of the ring region by adopting photoresist, making a deep body region graph on the initial oxide layer of the active region by adopting the photoresist, and forming a photoetching opening region by the ring region graph and the deep body region graph;
B. etching the photoetching opening area to remove the initial oxide layer, and injecting P-type impurities into the etched photoetching opening area to form a deep body area and a terminal ring;
C. removing the photoresist, driving in at high temperature, and growing a secondary oxide layer;
D. removing the initial oxide layer in the active region by adopting the secondary oxide layer of the photoresist protective ring region and the deep body region, and performing cell manufacturing of the VDMOS in the active region;
the following steps are carried out in the active area:
E. growing a grid oxide layer, depositing a polysilicon grid on the grid oxide layer, and further driving in impurities in a deep body region in the process of forming the grid oxide layer and the polysilicon grid;
F. etching the polysilicon gate at the position of the pre-made body region, and etching through the gate oxide layer in the polysilicon gate etching process to form a body region window;
G. carrying out body region injection and drive-in to form a body region of the device, wherein in the body region drive-in process, the deep body region is further driven-in;
H. doping the polysilicon gate, and directly forming a device source region while doping the polysilicon gate
I. Depositing a dielectric layer and refluxing the dielectric layer;
J. performing dielectric layer photoetching and etching;
K. and (5) manufacturing a metal lead.
Preferably, in step a, the thickness of the initial oxide layer is set to 6000-.
Preferably, in step a, the thickness of the initial oxide layer is set to 10000A.
Preferably, in the step B, P-type impurities are implanted, and the implantation dosage is set to be 3E14-2E 15.
Preferably, in step B, P-type impurities are implanted, and the implantation dose is set to be 1E 15.
Preferably, in step C, a secondary oxide layer is grown, and the thickness of the secondary oxide layer is set to 3000-.
Preferably, in step C, the thickness of the secondary oxide layer is set to 4000A.
Preferably, in step E, the gate oxide layer is set to be grown by dry thermal oxidation and has a thickness of 500-.
Preferably, in step E, the polysilicon gate is set to 6000A.
Preferably, in step H, POCL3 gas source is used for doping the polysilicon gate.
Compared with the beneficial effects of the prior art, the method for reducing the production cost of the VDMOS provided by the invention has the advantages that on the premise of ensuring the performance of the device, one photoetching and deep body region manufacturing process is reduced, so that the cost is greatly reduced by about 20%, the market competitiveness of the device is improved, and the method has good market application value.
Drawings
FIG. 1 is a schematic diagram of steps S1 and S2 in the prior art;
FIG. 2 is a diagram illustrating a step S3 in the prior art;
FIG. 3 is a diagram illustrating a step S4 according to the prior art;
FIG. 4 is a diagram illustrating a step S5 according to the prior art;
FIG. 5 is a diagram illustrating a step S6 according to the prior art;
FIG. 6 is a schematic diagram of steps S7 and S8 in the prior art;
FIG. 7 is a diagram illustrating a step S9 according to the prior art;
FIG. 8 is a diagram illustrating a step S10 according to the prior art;
FIG. 9 is a schematic diagram of steps S11 and S12 in the prior art;
FIG. 10 is a diagram illustrating a step S13 according to the prior art;
FIG. 11 is a schematic view of step A of the present invention;
FIG. 12 is a schematic view of step B of the present invention;
FIG. 13 is a schematic view of step C of the present invention;
FIG. 14 is a schematic view of step D of the present invention;
FIG. 15 is a schematic view of step E of the present invention;
FIG. 16 is a schematic view of step F of the present invention;
FIG. 17 is a schematic view of step G of the present invention;
FIG. 18 is a schematic view of step H of the present invention;
FIG. 19 is a schematic view of step I of the present invention;
FIG. 20 is a schematic view of step J of the present invention;
FIG. 21 is a schematic view of step K of the present invention.
Detailed Description
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail with reference to the accompanying drawings.
A method for reducing the production cost of a VDMOS comprises the following steps:
as shown in fig. 11, a, providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, growing an initial oxide layer on the N-type epitaxial layer, patterning a ring region on the initial oxide layer of the ring region using a photoresist, patterning a deep body region on the initial oxide layer of the active region using a photoresist, and forming a lithography open region by the ring region pattern and the deep body region pattern;
as shown in fig. 12, B, etching the lithography opening region, removing the initial oxide layer, and performing P-type impurity implantation on the etched lithography opening region to form a deep body region and a terminal ring;
as shown in fig. 13, C, removing the photoresist, performing high-temperature drive-in, and growing a secondary oxide layer at the same time;
as shown in fig. 14, D, removing the initial oxide layer in the active region by using the photoresist to protect the secondary oxide layer in the ring region and the deep body region, and performing a VDMOS cell fabrication in the active region;
the following steps are carried out in the active area:
as shown in fig. 15, E, growing a gate oxide layer, depositing a polysilicon gate on the gate oxide layer, and further driving in the deep body region impurities during the process of forming the gate oxide layer and the polysilicon gate;
as shown in fig. 16, F, etching the polysilicon gate at the position where the body region is to be formed, and etching through the gate oxide layer in the polysilicon gate etching process to form a body region window;
as shown in fig. 17, G, performing body region implantation and driving to form a body region of the device, wherein during the body region driving, the deep body region is further driven in;
as shown in fig. 18, H, polysilicon gate doping is performed, and a device source region is directly formed while the polysilicon gate doping is performed
As shown in fig. 19, I, depositing a dielectric layer, and performing dielectric layer reflux;
as shown in fig. 20, J, performing dielectric layer lithography and etching;
and (5) as shown in FIG. 21, K, making a metal lead.
Preferably, in step a, the thickness of the initial oxide layer is set to be 6000-.
Preferably, in step a, the thickness of the initial oxide layer is set to 10000A.
Preferably, in the step B, P-type impurities are implanted, and the implantation dosage is set to be 3E14-2E 15.
Preferably, in step B, P-type impurities are implanted, and the implantation dose is set to 1E 15.
Preferably, in step C, a secondary oxide layer is grown, and the thickness of the secondary oxide layer is set to 3000-.
Preferably, in step C, the thickness of the secondary oxide layer is set to 4000A.
Preferably, in step E, the gate oxide layer is set to be grown by dry thermal oxidation and has a thickness of 500-.
Preferably, in step E, the polysilicon gate is set to 6000A.
Preferably, in step H, POCL3 gas source is used for doping the polysilicon gate.
Further, forming an N-type epitaxial layer on an N-type substrate is configured by molecular beam epitaxy or chemical vapor deposition technology
Furthermore, the epitaxial wafer is cleaned by cleaning liquid and then placed in an oxidation furnace to grow an initial oxidation layer, wherein in the process of growing the initial oxidation layer, the temperature is generally kept between 900 ℃ and 1200 ℃ in the thermal oxidation process, and the gas flow is 4L/min.
The temperature of the oxidation furnace is controlled to be increased from low temperature to required temperature in a linear mode, silicon wafer deformation is avoided when the temperature changes suddenly, the temperature change is kept within +/-5 ℃, the temperature is linearly reduced after oxidation is completed, and the field limiting ring is used for increasing the breakdown voltage of the VDMOS.
The technical features mentioned above are combined with each other to form various embodiments which are not listed above, and all of them are regarded as the scope of the present invention described in the specification; also, modifications and variations may be suggested to those skilled in the art in light of the above teachings, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A method for reducing the production cost of a VDMOS is characterized by comprising the following steps:
A. providing an N-type substrate, forming an N-type epitaxial layer on the N-type substrate, growing an initial oxide layer on the N-type epitaxial layer, making a ring region graph on the initial oxide layer of the ring region by adopting photoresist, making a deep body region graph on the initial oxide layer of the active region by adopting the photoresist, and forming a photoetching opening region by the ring region graph and the deep body region graph;
B. etching the photoetching opening area, removing the initial oxide layer, and injecting P-type impurities into the etched photoetching opening area to form a deep body area and a terminal ring;
C. removing the photoresist, driving in at high temperature, and growing a secondary oxide layer;
D. removing the initial oxide layer in the active region by adopting the secondary oxide layers of the photoresist protective ring region and the deep body region, and performing cell manufacturing of the VDMOS in the active region;
the following steps are carried out in the active area:
E. growing a grid oxide layer, depositing a polysilicon grid on the grid oxide layer, and further driving in impurities in a deep body region in the process of forming the grid oxide layer and the polysilicon grid;
F. etching the polysilicon gate at the position of the pre-made body region, and etching through the gate oxide layer in the polysilicon gate etching process to form a body region window;
G. carrying out body region injection and drive-in to form a body region of the device, wherein in the body region drive-in process, the deep body region is further driven-in;
H. doping the polysilicon gate, and directly forming a device source region while doping the polysilicon gate
I. Depositing a dielectric layer and refluxing the dielectric layer;
J. performing dielectric layer photoetching and etching;
K. making a metal lead;
forming an N-type epitaxial layer on an N-type substrate, and setting the N-type epitaxial layer to be a molecular beam epitaxy or chemical vapor deposition technology;
cleaning the epitaxial wafer by cleaning liquid, placing the epitaxial wafer in an oxidation furnace to grow an initial oxidation layer, wherein in the process of growing the initial oxidation layer, the temperature is kept between 900 ℃ and 1200 ℃ in the thermal oxidation process, and the gas flow is 4L/min;
controlling the temperature of the oxidation furnace to increase from low temperature to required temperature in a linear mode, avoiding the deformation of a silicon wafer when the temperature changes suddenly, keeping the temperature change within +/-5 ℃, linearly reducing the temperature after the oxidation is finished, and using a field limiting ring to increase the breakdown voltage of the VDMOS;
in step A, the thickness of the initial oxide layer is set to 6000-;
in the step B, P-type impurities are implanted, and the implantation dosage is set to be 3E14-2E 15;
in the step C, a secondary oxide layer is grown, and the thickness of the secondary oxide layer is set to 3000-6000A;
in the step E, the grid oxide layer is set to be grown by dry thermal oxidation, the thickness is set to be 500-8000A, the polysilicon grid is set to be deposited by a CVD mode, and the thickness is set to be 4000-8000A.
2. A method for reducing the production cost of a VDMOS as recited in claim 1, wherein in the step a, the thickness of the initial oxide layer is set to 10000A.
3. The method of claim 1, wherein in step B, P-type impurities are implanted at a dose of 1E 15.
4. A method for reducing the production cost of a VDMOS as recited in claim 1, wherein in the step C, the thickness of the secondary oxide layer is set to 4000A.
5. A method for reducing the production cost of a VDMOS as recited in claim 1, wherein in the step E, the polysilicon gate is set to 6000A.
6. The method as claimed in claim 1, wherein step H, the poly gate doping is performed using POCL3 gas source.
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| JPH07273319A (en) * | 1994-03-31 | 1995-10-20 | Nippondenso Co Ltd | Semiconductor device |
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| CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
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| US4443931A (en) * | 1982-06-28 | 1984-04-24 | General Electric Company | Method of fabricating a semiconductor device with a base region having a deep portion |
| CN103151268B (en) * | 2013-03-21 | 2016-02-03 | 矽力杰半导体技术(杭州)有限公司 | A kind of vertical bilateral diffusion field-effect pipe and manufacturing process thereof |
| CN104299908B (en) * | 2013-07-19 | 2017-04-19 | 北大方正集团有限公司 | VDMOS and preparation method thereof |
| CN104576361B (en) * | 2013-10-23 | 2017-09-22 | 无锡华润上华半导体有限公司 | The preparation method of power diode |
| CN103779415B (en) * | 2014-01-20 | 2016-03-02 | 张家港凯思半导体有限公司 | Planar power MOS device and manufacture method thereof |
| CN107845580A (en) * | 2017-10-17 | 2018-03-27 | 深圳市可易亚半导体科技有限公司 | A kind of VDMOS device and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07273319A (en) * | 1994-03-31 | 1995-10-20 | Nippondenso Co Ltd | Semiconductor device |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN106409675A (en) * | 2016-09-08 | 2017-02-15 | 深圳深爱半导体股份有限公司 | Production method for depletion mode power transistor |
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Denomination of invention: A method to reduce the production cost of VDMOS Effective date of registration: 20230109 Granted publication date: 20220830 Pledgee: Shenzhen small and medium sized small loan Co.,Ltd. Pledgor: SHENZHEN RUICHIPS SEMICONDUCTOR CO.,LTD. Registration number: Y2023440020003 |