CN113257917B - Planar MOSFET of integrated rectifier and manufacturing method thereof - Google Patents
Planar MOSFET of integrated rectifier and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a planar MOSFET of an integrated rectifier and a manufacturing method thereof, wherein the planar MOSFET comprises a first conductive type epitaxial layer (1), an isolation ring (2), a thick oxide layer (3), a first well region (4), a first source region (5), a gate oxide layer (6), a polycrystalline electrode layer (7), a dielectric layer (8), a second well region (9) and a metal layer (10); the method comprises the steps of forming a first conductive type epitaxial layer (1), an isolation ring (2), a thick oxide layer (3), a first well region (4), a first source region (5), a gate oxide layer (6), a polycrystalline electrode layer (7), a dielectric layer (8), a second well region (9) and a metal layer (10) respectively. Compared with the existing integrated Schottky diode, the body diode of the Schottky diode is lower in forward voltage drop and has better high-temperature working characteristics.
Description
Technical Field
The invention relates to the field of semiconductor device material manufacturing, in particular to a planar MOSFET of an integrated rectifier and a manufacturing method thereof.
Background
Because of its advantages of low power consumption, fast switching speed, strong driving capability, negative temperature coefficient, etc., the planar field effect transistor device represented by the power MOSFET is widely used in motor speed regulation, inverters, electronic switches, automobile electric appliances, electronic ballasts, etc., and is one of the core components of power integrated circuits and power integrated systems.
In practical applications, the power loss of a MOSFET is derived from conduction losses, switching losses and body diode losses. The body diode loss is derived from a parasitic body diode structure of the power MOSFET and is generally characterized by the forward conduction voltage of the body diode, and the parameter is 0.8-1.0V under the conventional condition and is not easy to regulate and control in the actual process. The conventional optimization means is to connect a low-turn-on voltage Schottky diode in parallel at the two ends of the source and the drain of the MOSFET during packaging, and the Schottky diode has a smaller turn-on voltage (0.5-0.7V), so that the forward conduction voltage of the whole device can be effectively reduced.
However, as the size of integrated circuits is reduced, the external parallel diode approach requires larger line size, and the matching of the diode and MOSFET parameters requires additional verification. Therefore, a power MOSFET integrated with a schottky diode is produced.
Compared with a Schottky diode, the super barrier rectifier diode under the same area has lower starting voltage and more stable high-temperature working characteristic. However, the super barrier rectifier diode is relatively difficult to integrate with conventional planar MOSFET processes because it is sensitive to thermal processes and cannot undergo excessive high temperature processing.
Disclosure of Invention
The invention aims to provide a planar MOSFET (metal-oxide-semiconductor field effect transistor) of an integrated rectifier, which comprises a first conductivity type epitaxial layer, an isolation ring, a thick oxide layer, a first well region, a first source region, a gate oxide layer, a polycrystalline electrode layer, a dielectric layer, a second well region and a metal layer;
the first conductivity type epitaxial layer material includes, but is not limited to, silicon carbide, or gallium nitride.
The isolation ring is positioned in the first conductive type epitaxial layer;
the thick oxidation layer covers part of the surface of the first conductive type epitaxial layer;
the thick oxide layer and the isolation ring are coaxial, so that the planar MOSFET is divided into two regions which are respectively marked as an MOS device region and a rectifier device region;
the thick oxide layer and the isolation ring are used for isolating the rectifier device and the MOS device from working.
The thick oxide layer and the isolation ring are also distributed in the peripheral area of the whole planar MOSFET as the terminal of the planar MOSFET.
The first well region is positioned in the first conduction type epitaxial layer and positioned in the MOS device region;
the first source region is positioned in the first well region and positioned in the MOS device region;
the gate oxide layer covers part of the surface of the first conduction type epitaxial layer, part of the gate oxide layer is positioned in the MOS device area, and part of the gate oxide layer is positioned in the rectifier device area;
the polycrystalline electrode layer covers the gate oxide layer, part of the polycrystalline electrode layer is positioned in the MOS device region, and part of the polycrystalline electrode layer is positioned in the rectifier device region;
the polycrystalline electrode layer covers part of the surface on the gate oxide layer.
The dielectric layer covers part of the surface of the polycrystalline electrode layer and part of the surface of the first conduction type epitaxial layer, part of the dielectric layer is located in the MOS device area, and part of the dielectric layer is located in the rectifier device area;
the second well region is positioned in the first conduction type epitaxial layer and positioned in the rectifier device region;
the metal layer covers the surface of the planar MOSFET device, part of the metal layer is located in the MOS device area, and part of the metal layer is located in the rectifier device area.
The MOS device comprises a first conductive type epitaxial layer, a first well region, a first source region, a gate oxide layer and a polycrystalline electrode layer, wherein the first conductive type epitaxial layer, the first well region and the first source region are positioned in an MOS device region;
the first conduction type epitaxial layer located in the rectifier device area, the gate oxide layer located in the rectifier device area, the polycrystalline electrode layer located in the rectifier device area, the dielectric layer located in the rectifier device area, the second well region and the metal layer located in the rectifier device area form a rectifier device.
Preferably, the MOS device region and the rectifier device region are arranged in an array within the planar MOSFET active region.
Preferably, the MOS device region and the rectifier device region are respectively and independently arranged in the device active region.
A method of fabricating a planar MOSFET with an integrated rectifier, comprising the steps of:
1) Forming an isolation ring on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
2) Performing thick oxygen growth on the surface of the first conduction type epitaxial layer, and forming a thick oxide layer after photoetching, etching and photoresist removal;
3) Forming a first well region on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
4) Forming a first source region on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are first conductive type impurities;
5) Carrying out thermal oxidation on the surface of the first conductive type epitaxial layer to form a gate oxide layer;
6) Completing a polycrystalline process on the surface of the gate oxide layer, and forming a polycrystalline electrode layer after deposition, photoetching, etching and photoresist removal;
7) Finishing a dielectric process on the partial surface of the first conductive type epitaxial layer and the partial surface of the polycrystalline electrode layer, and forming a dielectric layer after deposition, annealing, photoetching, etching and photoresist removal;
8) Performing primary ion implantation to dope impurities of a second conductive type, and performing rapid thermal annealing to form a second well region;
9) And carrying out metal deposition to form a metal layer, and finishing the preparation of the device.
It is worth to say that the invention discloses a planar MOSFET of an integrated rectifier and a manufacturing method thereof, wherein in the process of manufacturing the planar MOSFET, a rectifier is manufactured in an integrated manner, and no extra photoetching layer is required to be added, and only additional implantation and rapid thermal annealing are added in sequence. Compared with the current scheme of integrating the Schottky diode, the Schottky diode has the advantages that the forward voltage drop of the body diode is lower, and the Schottky diode has better high-temperature working characteristics. The method has the advantages of simple process implementation and controllable process cost.
The technical effect of the invention is undoubtedly that the body diode of the invention has lower forward voltage drop and better high-temperature operating characteristics than the existing integrated schottky diode.
According to the manufacturing method, the technical process for forming the rectifier is compatible with the technical process for forming the MOSFET, a photoetching layer is not added, only one-time injection and rapid thermal annealing are added in the rectifier forming process, the process is simple to realize, and the cost can be effectively controlled.
Drawings
Fig. 1 is a schematic diagram of the final device.
FIG. 2 is a schematic diagram of the device after completion of the isolation ring and thick oxide layer;
fig. 3 is a schematic diagram of the device after completion of the first well region and the first source region;
FIG. 4 is a schematic view of the device after completion of the thick gate oxide layer and the thin gate oxide layer;
FIG. 5 is a schematic view of the device after completion of the polycrystalline electrode layer and dielectric layer;
in the figure: the semiconductor device comprises a first conduction type epitaxial layer 1, an isolation ring 2, a thick oxide layer 3, a first well region 4, a first source region 5, a gate oxide layer 6, a polycrystalline electrode layer 7, a dielectric layer 8, a second well region 9, a metal layer 10, an MOS device region 11 and a rectifier device region 12.
Detailed Description
The present invention is further illustrated by the following examples, but it should not be construed that the scope of the above-described subject matter is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention and the scope of the invention is covered by the present invention according to the common technical knowledge and the conventional means in the field.
Example 1:
referring to fig. 1 to 5, a planar MOSFET of an integrated rectifier includes a first conductive type epitaxial layer 1, an isolation ring 2, a thick oxide layer 3, a first well region 4, a first source region 5, a gate oxide layer 6, a polycrystalline electrode layer 7, a dielectric layer 8, a second well region 9, and a metal layer 10;
the first conductivity type epitaxial layer 1 material includes, but is not limited to, silicon carbide, or gallium nitride.
The isolation ring 2 is positioned in the first conduction type epitaxial layer 1;
the thick oxide layer 3 covers part of the surface of the first conductive type epitaxial layer 1;
the thick oxide layer 3 and the isolation ring 2 are coaxial, so that the planar MOSFET is divided into two regions which are respectively marked as an MOS device region 11 and a rectifier device region 12;
the thick oxide layer 3 and the isolation ring 2 are used for isolating the rectifier device and the MOS device from working.
The thick oxide layer 3 and the isolation ring 2 are also distributed in the peripheral area of the whole planar MOSFET as the terminal of the planar MOSFET.
The first well region 4 is positioned in the first conduction type epitaxial layer 1 and is positioned in the MOS device region 11;
the first source region 5 is positioned in the first well region 4 and positioned in the MOS device region 11;
the gate oxide layer 6 covers part of the surface of the first conduction type epitaxial layer 1, part of the gate oxide layer 6 is positioned in the MOS device region 11, and part of the gate oxide layer 6 is positioned in the rectifier device region 12;
the polycrystalline electrode layer 7 covers the gate oxide layer 6, part of the polycrystalline electrode layer 7 is located in the MOS device region 11, and part of the polycrystalline electrode layer 7 is located in the rectifier device region 12;
the polycrystalline electrode layer 7 covers part of the surface on the gate oxide layer 6.
The dielectric layer 8 covers part of the surface of the polycrystalline electrode layer 7 and part of the surface of the first conduction type epitaxial layer 1, part of the dielectric layer 8 is located in the MOS device region 11, and part of the dielectric layer 8 is located in the rectifier device region 12;
the second well region 9 is located in the first conductivity type epitaxial layer 1 and located in the rectifier device region 12;
the metal layer 10 covers the surface of the planar MOSFET device, part of the metal layer 10 is located in the MOS device region 11, and part of the metal layer 10 is located in the rectifier device region 12.
The MOS device comprises a first conductive type epitaxial layer 1 positioned in an MOS device region 11, a first well region 4, a first source region 5, a gate oxide layer 6 positioned in the MOS device region 11 and a polycrystalline electrode layer 7 positioned in the MOS device region 11;
the first conduction type epitaxial layer 1 positioned in the rectifier device area 12, the gate oxide layer 6 positioned in the rectifier device area 12, the polycrystalline electrode layer 7 positioned in the rectifier device area 12, the dielectric layer 8 positioned in the rectifier device area 12, the second well region 9 and the metal layer 10 positioned in the rectifier device area 12 form a rectifier device.
The MOS device region 11 and the rectifier device region 12 are arranged in an array within the planar MOSFET active region.
Example 2:
a planar MOSFET of an integrated rectifier comprises a first conductive type epitaxial layer 1, an isolation ring 2, a thick oxide layer 3, a first well region 4, a first source region 5, a gate oxide layer 6, a polycrystalline electrode layer 7, a dielectric layer 8, a second well region 9 and a metal layer 10;
the first conductivity type epitaxial layer 1 material includes, but is not limited to, silicon carbide, or gallium nitride.
The isolation ring 2 is positioned in the first conduction type epitaxial layer 1;
the thick oxide layer 3 covers part of the surface of the first conductive type epitaxial layer 1;
the thick oxide layer 3 and the isolation ring 2 are coaxial, so that the planar MOSFET is divided into two regions which are respectively marked as an MOS device region 11 and a rectifier device region 12;
the thick oxide layer 3 and the isolation ring 2 are used for isolating the rectifier device and the MOS device from working.
The thick oxide layer 3 and the isolation ring 2 are also distributed in the peripheral area of the whole planar MOSFET as the terminal of the planar MOSFET.
The first well region 4 is positioned in the first conduction type epitaxial layer 1 and is positioned in the MOS device region 11;
the first source region 5 is positioned in the first well region 4 and positioned in the MOS device region 11;
the gate oxide layer 6 covers part of the surface of the first conduction type epitaxial layer 1, part of the gate oxide layer 6 is positioned in the MOS device region 11, and part of the gate oxide layer 6 is positioned in the rectifier device region 12;
the polycrystalline electrode layer 7 covers the gate oxide layer 6, part of the polycrystalline electrode layer 7 is located in the MOS device region 11, and part of the polycrystalline electrode layer 7 is located in the rectifier device region 12;
the polycrystalline electrode layer 7 covers part of the surface on the gate oxide layer 6.
The dielectric layer 8 covers part of the surface of the polycrystalline electrode layer 7 and part of the surface of the first conduction type epitaxial layer 1, part of the dielectric layer 8 is located in the MOS device region 11, and part of the dielectric layer 8 is located in the rectifier device region 12;
the second well region 9 is located in the first conductivity type epitaxial layer 1 and located in the rectifier device region 12;
the metal layer 10 covers the surface of the planar MOSFET device, and a part of the metal layer 10 is located in the MOS device region 11, and a part of the metal layer 10 is located in the rectifier device region 12.
The MOS device comprises a first conductive type epitaxial layer 1 positioned in an MOS device region 11, a first well region 4, a first source region 5, a gate oxide layer 6 positioned in the MOS device region 11 and a polycrystalline electrode layer 7 positioned in the MOS device region 11;
the first conduction type epitaxial layer 1 positioned in the rectifier device area 12, the gate oxide layer 6 positioned in the rectifier device area 12, the polycrystalline electrode layer 7 positioned in the rectifier device area 12, the dielectric layer 8 positioned in the rectifier device area 12, the second well region 9 and the metal layer 10 positioned in the rectifier device area 12 form a rectifier device.
The MOS device region 11 and the rectifier device region 12 are arranged in an array inside the planar MOSFET active region.
The MOS device region 11 and the rectifier device region 12 are respectively and independently arranged in the device active region.
Example 3:
a method of fabricating a planar MOSFET with an integrated rectifier, comprising the steps of:
1) Forming an isolation ring 2 on the first conductive type epitaxial layer 1 through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
2) Performing thick oxygen growth on the surface of the first conductive type epitaxial layer 1, and forming a thick oxide layer 3 after photoetching, etching and photoresist removal;
3) Forming a first well region 4 on the first conductive type epitaxial layer 1 through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
4) Forming a first source region 5 on the first conductive type epitaxial layer 1 through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are first conductive type impurities;
5) Performing thermal oxidation on the surface of the first conduction type epitaxial layer 1 to form a gate oxide layer 6;
6) Completing a polycrystalline process on the surface of the gate oxide layer 6, and forming a polycrystalline electrode layer 7 after deposition, photoetching, etching and photoresist removal;
7) Finishing a medium process on part of the surface of the first conductive type epitaxial layer 1 and part of the surface of the polycrystalline electrode layer 7, and forming a medium layer 8 after deposition, annealing, photoetching, etching and photoresist removal;
8) Performing primary ion implantation to dope impurities of a second conductivity type, and performing rapid thermal annealing to form a second well region 9;
9) And carrying out metal deposition to form a metal layer 10, and finishing the preparation of the device.
Example 4:
a planar MOSFET of an integrated rectifier comprises an MOS device area and a rectifier device area, and specifically comprises a first conduction type epitaxial layer, a thick oxide layer, an isolation ring, a first well region, a first source region, a second well region, a thick gate oxide layer, a thin gate oxide layer, a polycrystalline electrode layer, a dielectric layer and a metal layer;
the thick oxide layer and the isolation ring are simultaneously distributed at the junction of the MOS device and the rectifier device to play a role in isolating the two devices from working;
the first well region, the first source region and the thick gate oxide layer are distributed in the MOS device region, wherein the first well region and the first source region are positioned in the first conductive type epitaxial layer, and the thick gate oxide layer covers part of the surface of the first conductive type epitaxial layer of the MOS device region;
the second well region and the thin gate oxide layer are distributed in the rectifier device region, wherein the second well region is positioned in the first conduction type epitaxial layer, and the thin gate oxide layer covers part of the surface of the first conduction type epitaxial layer of the MOS device region;
the polycrystalline electrode layer covers partial surfaces above the thick gate oxide layer and the thin gate oxide layer;
the dielectric layer covers the polycrystalline electrode layer and part of the surface of the top epitaxial layer of the first conduction type;
the metal layer covers the surface of the whole device;
the thick oxide layer and the isolation ring are also used as terminals of the device and distributed in the peripheral area of the whole device;
the MOS device region and the rectifier device region can be arranged in the device active region in an array form, and can also be respectively and independently arranged in the device active region.
Example 5:
a manufacturing method of a planar MOSFET of an integrated rectifier comprises the following steps:
forming an isolation ring on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
performing thick oxygen growth on the first conductive type epitaxial layer, and forming a thick oxide layer after photoetching, etching and photoresist removal;
forming a first well region on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
forming a first source region on the first conductive type epitaxial layer through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are first conductive type impurities;
performing thermal oxidation on the first conductive type epitaxial layer to form a gate oxide layer;
carrying out a polycrystalline process, and forming a polycrystalline electrode layer after deposition, photoetching, etching and photoresist removal;
performing a dielectric process, and forming a dielectric layer after deposition, annealing, photoetching, etching and photoresist removal;
performing primary ion implantation to dope impurities of a second conductive type, and performing rapid thermal annealing to form a second well region;
and carrying out metal deposition to finish the preparation of the device.
Example 6:
a method for manufacturing a planar MOSFET of an integrated rectifier comprises the following steps
1) Gluing and photoetching are carried out on the first conductive type epitaxial layer, then boron ion implantation is carried out, the implantation dosage is 1e14, then photoresist removal and annealing are carried out, the annealing temperature is 1150 ℃ for 120min, and an isolation ring 2 is formed; then, field oxide oxidation is carried out to the thickness of 1um, and then photoetching is carried out to form a thick oxide layer. The device structure is now as shown in figure 1.
2) Implanting impurities into the first well region, wherein the implanted impurities are boron and have a dose of 6e13, and then performing high-temperature annealing at 1150 ℃ for 120min to form a first well region; then, impurity implantation of the first source region is performed, and the implanted impurity is phosphorus with a dose of 5e15. The device structure is now as shown in figure 2.
3) And performing gate oxide deposition, wherein the thickness of the gate oxide is 90nm, and the structure of the device is shown in figure 3.
4) Carrying out polycrystalline deposition, wherein the thickness of the polycrystalline layer is 700nm, and then carrying out photoetching to form a polycrystalline electrode layer; then, medium deposition is carried out, the deposited film is BPSG with the thickness of 1um, and a medium layer is formed after photoetching. The device structure is now as shown in fig. 4.
5) Carrying out boron injection once at the dosage of 5e12, and then carrying out a rapid thermal annealing process for 1min at the annealing time of 715 ℃ to form a second well region; then metal deposition is carried out to a thickness of 4um, and finally device preparation is finished. The device structure at this point is shown in fig. 5.
Example 7:
a method for manufacturing a planar MOSFET of an integrated rectifier comprises the following steps
1) Gluing and photoetching are carried out on the first conductive type epitaxial layer, then boron ion implantation is carried out, the implantation dosage is 8e13, then photoresist removal and annealing are carried out, the annealing temperature is 1150 ℃ for 150min, and an isolation ring 2 is formed; then, field oxide oxidation is carried out to the thickness of 1.2um, and then photoetching is carried out to form a thick oxide layer. The device structure is now as shown in figure 1.
2) Implanting impurities into the first well region, wherein the implanted impurities are boron and have a dose of 4e13, and then performing high-temperature annealing at 1150 ℃ for 120min to form a first well region; then, impurity implantation of the first source region is performed, the implanted impurity being arsenic, at a dose of 1e16. The device structure is now as shown in figure 2.
3) And carrying out gate oxide deposition, wherein the thickness of the gate oxide is 100nm, and the structure of the device is shown in figure 3.
4) Carrying out polycrystalline deposition, wherein the thickness of a polycrystalline layer is 700nm, and then carrying out photoetching to form a polycrystalline electrode layer; then, medium deposition is carried out, the deposited film is BPSG with the thickness of 1um, and a medium layer is formed after photoetching. The device structure is now as shown in figure 4.
5) Carrying out boron injection once with the dosage of 7e12, and then carrying out a rapid thermal annealing process for 1min at the annealing time of 730 ℃ to form a second well region; then metal deposition is carried out to a thickness of 4um, and finally device preparation is finished. The device structure is now as shown in fig. 5.
Claims (7)
1. A planar MOSFET with an integrated rectifier, comprising: the device comprises a first conductive type epitaxial layer (1), an isolation ring (2), a thick oxide layer (3), a first well region (4), a first source region (5), a gate oxide layer (6), a polycrystalline electrode layer (7), a dielectric layer (8), a second well region (9) and a metal layer (10);
the isolation ring (2) is positioned in the first conduction type epitaxial layer (1);
the thick oxide layer (3) covers part of the surface of the first conduction type epitaxial layer (1);
the thick oxide layer (3) and the isolation ring (2) are coaxial, so that the planar MOSFET is divided into two regions which are respectively marked as an MOS device region (11) and a rectifier device region (12);
the thick oxide layer (3) and the isolation ring (2) are used for isolating the rectifier device and the MOS device from working;
the first well region (4) is positioned in the first conduction type epitaxial layer (1) and positioned in the MOS device region (11);
the first source region (5) is positioned in the first well region (4) and positioned in the MOS device region (11);
the gate oxide layer (6) covers part of the surface of the first conduction type epitaxial layer (1), part of the gate oxide layer (6) is located in the MOS device region (11), and part of the gate oxide layer (6) is located in the rectifier device region (12);
the polycrystalline electrode layer (7) covers the gate oxide layer (6), part of the polycrystalline electrode layer (7) is located in the MOS device region (11), and part of the polycrystalline electrode layer (7) is located in the rectifier device region (12);
the dielectric layer (8) covers part of the surface of the polycrystalline electrode layer (7) and part of the surface of the first conduction type epitaxial layer (1), part of the dielectric layer (8) is located in the MOS device region (11), and part of the dielectric layer (8) is located in the rectifier device region (12);
the second well region (9) is positioned in the first conduction type epitaxial layer (1) and is positioned in the rectifier device region (12);
the metal layer (10) covers the surface of the planar MOSFET device, part of the metal layer (10) is located in the MOS device area (11), and part of the metal layer (10) is located in the rectifier device area (12);
the MOS device region (11) and the rectifier device region (12) are respectively and independently arranged in the device active region.
2. The planar MOSFET of claim 1 wherein: the polycrystalline electrode layer (7) covers part of the surface of the gate oxide layer (6).
3. A planar MOSFET of an integrated rectifier as claimed in claim 1 or 2, wherein: the MOS device comprises a first conductive type epitaxial layer (1) positioned in an MOS device region (11), a first well region (4), a first source region (5), a gate oxide layer (6) positioned in the MOS device region (11) and a polycrystalline electrode layer (7) positioned in the MOS device region (11);
the rectifier device comprises a first conduction type epitaxial layer (1) located in a rectifier device area (12), a gate oxide layer (6) located in the rectifier device area (12), a polycrystalline electrode layer (7) located in the rectifier device area (12), a dielectric layer (8) located in the rectifier device area (12), a second well area (9) and a metal layer (10) located in the rectifier device area (12).
4. The planar MOSFET of claim 1, wherein: the first conductivity type epitaxial layer (1) material includes, but is not limited to, silicon carbide, or gallium nitride.
5. The planar MOSFET of claim 1, wherein: the thick oxide layer (3) and the isolation ring (2) are also used as terminals of the planar MOSFET and distributed in the peripheral area of the whole planar MOSFET.
6. The planar MOSFET of claim 1, wherein: the MOS device regions (11) and the rectifier device regions (12) are arranged in an array within the planar MOSFET active region.
7. A method of manufacturing a planar MOSFET integrated with a rectifier as claimed in any one of claims 1 to 6, including the steps of:
1) Forming an isolation ring (2) on the first conductive type epitaxial layer (1) through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conductive type impurities;
2) Performing thick oxygen growth on the surface of the first conductive type epitaxial layer (1), and forming a thick oxide layer (3) after photoetching, etching and photoresist removal;
3) Forming a first well region (4) on the first conduction type epitaxial layer (1) through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are second conduction type impurities;
4) Forming a first source region (5) on the first conductive type epitaxial layer (1) through photoetching, injection, photoresist removal and annealing, wherein the injected impurities are first conductive type impurities;
5) Carrying out thermal oxidation on the surface of the first conduction type epitaxial layer (1) to form a gate oxide layer (6);
6) Completing a polycrystalline process on the surface of the gate oxide layer (6), and forming a polycrystalline electrode layer (7) after deposition, photoetching, etching and photoresist removal;
7) Finishing a medium process on the partial surface of the first conductive type epitaxial layer (1) and the partial surface of the polycrystalline electrode layer (7), and forming a medium layer (8) after deposition, annealing, photoetching, etching and photoresist removal;
8) Carrying out primary ion implantation, doping impurities into second conductive type impurities, and then carrying out rapid thermal annealing to form a second well region (9);
9) And carrying out metal deposition to form a metal layer (10) so as to finish the preparation of the device.
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