CN108198759A - A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen - Google Patents
A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen Download PDFInfo
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- CN108198759A CN108198759A CN201711261016.8A CN201711261016A CN108198759A CN 108198759 A CN108198759 A CN 108198759A CN 201711261016 A CN201711261016 A CN 201711261016A CN 108198759 A CN108198759 A CN 108198759A
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- polycrystalline
- well region
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- dielectric layer
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 29
- 229910052760 oxygen Inorganic materials 0.000 title claims abstract description 29
- 239000001301 oxygen Substances 0.000 title claims abstract description 29
- 230000015556 catabolic process Effects 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000007796 conventional method Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 10
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 5
- 239000000956 alloy Substances 0.000 claims abstract description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 5
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a kind of manufacturing methods for improving the breakdown of plane VDMOS Gate oxygen, it is characterised in that：Including epitaxial layer, well region, source region, grid oxide layer, polycrystal layer, polycrystalline conforma dielectric layer, dielectric layer and metal layer.It follows the steps below：1) epitaxial layer is formed using conventional method.2) well region and source region are prepared.3) deposit of grid oxide layer is carried out.4) deposit and doping of polycrystal layer are carried out.5) polycrystalline chemical wet etching is carried out.6) SiO is deposited using low temperature LPCVD2Mode, formed polycrystalline conforma dielectric layer.The thickness of the polycrystalline conforma dielectric layer is 10nm~60nm.7) deposit of dielectric layer is carried out using conventional method.8) hole chemical wet etching, sputtering interconnection metal are carried out.9) interconnection metal lithographic etching, alloy.
Description
Technical field
The present invention relates to field of semiconductor, specifically a kind of manufacturer for improving the breakdown of plane VDMOS Gate oxygen
Method.
Background technology
Vertical double diffusion power MOSFET (VDMOS：Vertical Double-diffusion Metal Oxide
Semiconductor) device is because it has many advantages, such as that low in energy consumption, switching speed is fast, driving force is strong, negative temperature coefficient, and wide
It is general to be used to be applied to electric machine speed regulation, inverter, electronic switch, car electrics and electric ballast etc., be power integrated circuit and
One of core component of power integrated system.
As the grid oxygen technique of MOS device core, key parameter and long-term reliability to device have vital
Effect.Grid oxygen deterioration can lead to threshold voltage shift, grid leak electricity increase, with the reduction of process, grid oxygen
Quality more as one of research hotspot of MOS device
Grid oxygen breakdown can be reflected by the test structure of similar capacity plate antenna.Such as national inventing patent：A kind of " grid oxygen
Dielectric tests structure ", number of patent application：201410106620.3 describe what a kind of short processes flow can be realized, based on lining
The test structure of similar capacity plate antenna that bottom, grid, grid oxide layer and polysilicon pole plate form can accurately reflect grid oxygen quality
Quality.In ideal capacity plate antenna structure, the size of grid oxygen breakdown is only related with the quality and thickness of grid oxygen.
But for practical plane VDMOS device, true Gate breakdown is practical to be determined by two paths (such as Fig. 1)：The
One, the polysilicon similar with conventional structure capacity plate antenna --- grid oxygen --- substrate well regions and source region access；Second, by polycrystalline
Etching, sidewall oxidation, dielectric deposition and metal interconnection and polysilicon --- side wall medium layer --- the top-level metallic circuit formed.
In ideal conditions, circuit two due to thickness of dielectric layers it is larger, be not influence grid breakdown principal element.But
In practical plane VDMOS processing flows, we can use polycrystalline to aoxidize or with oxygen in technique usually after polycrystal etching
The annealing that atmosphere is enclosed forms polycrystalline oxide layer in the polysilicon surface for having adulterated and having etched, prevents the polysilicon being doped
It is exposed in subsequent high temperature process outer and impurity is caused to be precipitated.And this can cause the polysilicon bottom etched to form one
Similar to structure such as Fig. 2 of beak so that should concentrate and divide in sharp corner in the electric field line of polysilicon bottom vertical distribution originally
Cloth reduces grid oxygen breakdown.The characteristics of based on plane VDMOS process, conventional polycrystalline oxidation technology or with oxygen atmosphere
Annealing although evaded the problem of impurity is precipitated in heavily doped polysilicon in high temperature process, but result in grid oxygen breakdown
It reduces.
Invention content
Present invention aim to address problems of the prior art, provide a kind of raising plane VDMOS Gate oxygen breakdown
Manufacturing method.
To realize the present invention purpose and the technical solution adopted is that such, it is a kind of to improve plane VDMOS Gate oxygen breakdown
Manufacturing method, it is characterised in that：Including epitaxial layer, well region, source region, grid oxide layer, polycrystal layer, polycrystalline conforma dielectric layer, dielectric layer
And metal layer.
It follows the steps below：
1) epitaxial layer is formed using conventional method.
2) well region and source region are prepared.
The well region is located in epitaxial layer, and the upper surface of the well region and the upper surface of epitaxial layer are coplanar.The source region position
In in well region, the upper surface of the well region and the upper surface of epitaxial layer are coplanar.
3) deposit of grid oxide layer is carried out.
The grid oxide layer is covered in the upper surface of epitaxial layer.The grid oxide layer is also covered in the part surface on well region.
4) deposit and doping of polycrystal layer are carried out.
The polycrystal layer is covered in the upper surface of grid oxide layer.
5) polycrystalline chemical wet etching is carried out.
6) SiO is deposited using low temperature LPCVD2Mode, formed polycrystalline conforma dielectric layer.
The polycrystalline conforma dielectric layer is covered in the surface of polycrystal layer.
The thickness of the polycrystalline conforma dielectric layer is 10nm~60nm.
7) deposit of dielectric layer is carried out using conventional method.
8) hole chemical wet etching, sputtering interconnection metal are carried out.
9) interconnection metal lithographic etching, alloy.
Further, in process, high temperature promotes technique not use the technique with oxygen atmosphere.
The solution have the advantages that unquestionable, the present invention has the following advantages：
1) method in the present invention can evade polycrystalline sidewall profile and continue behind changes in thermal oxidation technology, and most
The problem of grid oxygen breakdown is caused to reduce eventually.
By taking 650A grid oxygen techniques as an example, routinely GOI test structures method is tested, its breakdown value is read under 10uA as 80V,
And after a polycrystalline oxidation is completed, breakdown is reduced to 60~65V, after using manufacturing method of the present invention, breakdown
It is worth for 77~80V.
2) method in the present invention is realized simple, can not change processing main flow, need to only be replaced polycrystalline in process and be carved
Oxidation technology after erosion can be realized.
Description of the drawings
Fig. 1 is the Gate breakdown circuit diagrams of existing VDMOS device；
Fig. 2 is the diagrammatic cross-section that Gate oxidations are front and rear after polycrystal etching；
Fig. 3 is using the diagrammatic cross-section after the deposit of polycrystalline conforma dielectric layer after polycrystal etching；
Fig. 4 is the plane VDMOS device sectional view completed after polycrystal etching；
Fig. 5 is the plane VDMOS device sectional view completed after the deposit of polycrystalline conforma dielectric layer；
Fig. 6 is the plane VDMOS device sectional view completed after entire processing flow.
In figure：Epitaxial layer 1, well region 2, source region 3, grid oxide layer 4, polycrystal layer 5, polycrystalline conforma dielectric layer 6, dielectric layer 7 and gold
Belong to layer 8
Specific embodiment
With reference to embodiment, the invention will be further described, but should not be construed the above-mentioned subject area of the present invention only
It is limited to following embodiments.Without departing from the idea case in the present invention described above, according to ordinary skill knowledge and used
With means, various replacements and change are made, should all be included within the scope of the present invention.
Embodiment 1：
A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen, it is characterised in that：Including epitaxial layer 1, well region 2, source region
3rd, grid oxide layer 4, polycrystal layer 5, polycrystalline conforma dielectric layer 6, dielectric layer 7 and metal layer 8.
It follows the steps below：
1) epitaxial layer 1 is formed using conventional method.
2) well region 2 and source region 3 are prepared.
The well region 2 is located in epitaxial layer 1, and the upper surface and the upper surface of epitaxial layer 1 of the well region 2 are coplanar.The source
Area 3 is located in well region 2, and the upper surface and the upper surface of epitaxial layer 1 of the well region 2 are coplanar.
3) deposit of grid oxide layer 4 is carried out.
The grid oxide layer 4 is covered in the upper surface of epitaxial layer 1.The grid oxide layer 4 is also covered in the part table on well region 2
Face.
4) deposit and doping of polycrystal layer 5 are carried out.
The polycrystal layer 5 is covered in the upper surface of grid oxide layer 4.
5) as shown in figure 4, carrying out polycrystalline chemical wet etching.
6) it uses and is cleaned by the solution that SPM, SC-1, SC-2 are formed；
As shown in figure 5, deposit SiO using low temperature LPCVD2Mode, form polycrystalline conforma dielectric layer 6.After ensuring etching
Polycrystalline sidewall profile do not lead to localized variation due to thermal oxide.
The polycrystalline conforma dielectric layer 6 is covered in the surface of polycrystal layer 5.
The thickness of the polycrystalline conforma dielectric layer 6 is 20nm~40nm.
7) deposit of dielectric layer 7 is carried out using conventional method.
8) hole chemical wet etching, sputtering interconnection metal are carried out.
9) as shown in Figure 6.Interconnect metal lithographic etching, alloy.
In process, high temperature promotes technique not use the technique with oxygen atmosphere.
Embodiment 2：
A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen, it is characterised in that：Including epitaxial layer 1, well region 2, source region
3rd, grid oxide layer 4, polycrystal layer 5, polycrystalline conforma dielectric layer 6, dielectric layer 7 and metal layer 8.
It follows the steps below：
1) epitaxial layer 1 is formed using conventional method.
2) well region 2 and source region 3 are prepared.
The well region 2 is located in epitaxial layer 1, and the upper surface and the upper surface of epitaxial layer 1 of the well region 2 are coplanar.The source
Area 3 is located in well region 2, and the upper surface and the upper surface of epitaxial layer 1 of the well region 2 are coplanar.
3) deposit of grid oxide layer 4 is carried out.
The grid oxide layer 4 is covered in the upper surface of epitaxial layer 1.The grid oxide layer 4 is also covered in the part table on well region 2
Face.
4) deposit and doping of polycrystal layer 5 are carried out.
The polycrystal layer 5 is covered in the upper surface of grid oxide layer 4.
5) as shown in figure 4, carrying out polycrystalline chemical wet etching.
6) it uses and is cleaned by the solution that SPM, SC-1, SC-2 are formed；
As shown in figure 5, deposit SiO using low temperature LPCVD2Mode, form polycrystalline conforma dielectric layer 6.After ensuring etching
Polycrystalline sidewall profile do not lead to localized variation due to thermal oxide.
The polycrystalline conforma dielectric layer 6 is covered in the surface of polycrystal layer 5.
The thickness of the polycrystalline conforma dielectric layer 6 is 20nm~60nm.
7) deposit of dielectric layer 7 is carried out using conventional method.
8) hole chemical wet etching, sputtering interconnection metal are carried out.
9) as shown in Figure 6.Interconnect metal lithographic etching, alloy.
In process, high temperature promotes technique not use the technique with oxygen atmosphere.
Claims (2)
1. a kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen, it is characterised in that：Including epitaxial layer (1), well region (2), source
Area (3), grid oxide layer (4), polycrystal layer (5), polycrystalline conforma dielectric layer (6), dielectric layer (7) and metal layer (8)；
It follows the steps below：
1) epitaxial layer (1) is formed using conventional method；
2) well region (2) and source region (3) are prepared；
For the well region (2) in epitaxial layer (1), the upper surface and the upper surface of epitaxial layer (1) of the well region (2) are coplanar；Institute
Source region (3) is stated in well region (2), the upper surface and the upper surface of epitaxial layer (1) of the well region (2) are coplanar；
3) deposit of grid oxide layer (4) is carried out；
The grid oxide layer (4) is covered in the upper surface of epitaxial layer (1)；The grid oxide layer (4) is also covered in the portion on well region (2)
Divide surface；
4) deposit and doping of polycrystal layer (5) are carried out；
The polycrystal layer (5) is covered in the upper surface of grid oxide layer (4)；
5) polycrystalline chemical wet etching is carried out；
6) SiO is deposited using low temperature LPCVD2Mode, formed polycrystalline conforma dielectric layer (6)；
The polycrystalline conforma dielectric layer (6) is covered in the surface of polycrystal layer (5)；
The thickness of the polycrystalline conforma dielectric layer (6) is 10nm~60nm；
7) deposit of dielectric layer (7) is carried out using conventional method；
8) hole chemical wet etching, sputtering interconnection metal are carried out；
9) interconnection metal lithographic etching, alloy.
2. the manufacturing method punctured according to a kind of raising plane VDMOS Gate oxygen described in claim 1, it is characterised in that：
In process, high temperature promotes technique not use the technique with oxygen atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201711261016.8A CN108198759A (en) | 2017-12-04 | 2017-12-04 | A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711261016.8A CN108198759A (en) | 2017-12-04 | 2017-12-04 | A kind of manufacturing method for improving the breakdown of plane VDMOS Gate oxygen |
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| CN108198759A true CN108198759A (en) | 2018-06-22 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103110A (en) * | 2018-09-19 | 2018-12-28 | 盛世瑶兰（深圳）科技有限公司 | A kind of VDMOS device and preparation method thereof |
| CN113257917A (en) * | 2021-03-29 | 2021-08-13 | 重庆中科渝芯电子有限公司 | Planar MOSFET of integrated rectifier and manufacturing method thereof |
| CN113257916A (en) * | 2021-03-29 | 2021-08-13 | 重庆中科渝芯电子有限公司 | Planar field effect transistor of integrated rectifier and manufacturing method thereof |
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| CN107068569A (en) * | 2017-03-16 | 2017-08-18 | 重庆中科渝芯电子有限公司 | A kind of power MOSFET manufacture methods with back side corrosion oxidation layer process |
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| US20090090919A1 (en) * | 2007-10-03 | 2009-04-09 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of producing the same |
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| CN109103110A (en) * | 2018-09-19 | 2018-12-28 | 盛世瑶兰（深圳）科技有限公司 | A kind of VDMOS device and preparation method thereof |
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| CN113257917A (en) * | 2021-03-29 | 2021-08-13 | 重庆中科渝芯电子有限公司 | Planar MOSFET of integrated rectifier and manufacturing method thereof |
| CN113257916A (en) * | 2021-03-29 | 2021-08-13 | 重庆中科渝芯电子有限公司 | Planar field effect transistor of integrated rectifier and manufacturing method thereof |
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Application publication date: 20180622 |