CN112071913A - Silicon carbide planar gate MOSFET cell structure and manufacturing method - Google Patents
Silicon carbide planar gate MOSFET cell structure and manufacturing method Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims abstract description 115
- 210000004027 cell Anatomy 0.000 claims abstract description 38
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- 210000003850 cellular structure Anatomy 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 28
- 238000005468 ion implantation Methods 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- -1 boron ions Chemical class 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000012047 saturated solution Substances 0.000 claims description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention discloses a silicon carbide planar gate MOSFET cellular structure, which is covered with a silicon carbide epitaxial layer, a gate electrode and an interlayer dielectric layer from bottom to top. The silicon carbide epitaxial layer is characterized in that a plurality of first conduction type contact regions and a plurality of second conduction type contact regions are arranged in the middle of the upper end of the silicon carbide epitaxial layer, and the first conduction type contact regions are located in the middle of the second conduction type contact regions and are distributed at intervals along the length direction of the MOSFET channel. The gate electrodes cover two sides of the upper end of the second conductive type contact area, and a first distance between the gate electrodes on the two sides is smaller than the width of the second conductive type contact area and larger than the width of the first conductive type contact areas. The interlayer dielectric layers cover the gate electrodes, and the second distance between the interlayer dielectric layers on the two sides is smaller than the width of the first conductive type contact regions. Therefore, the cell density can be improved, the channel resistance is reduced, and the purpose of reducing the on resistance is achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a silicon carbide planar gate MOSFET cellular structure and a manufacturing method thereof.
Background
Silicon Carbide (SiC) material is an excellent material for preparing core power devices in the power electronic field due to its forbidden bandwidth three times that of Silicon, high critical breakdown electric field, high thermal conductivity and carrier saturation drift velocity. On the other hand, in the power device family, the MOSFET is used as a fully-controlled power Metal-Oxide-Semiconductor Field Effect transistor (MOSFET), and has the characteristics of high switching speed, high input impedance, relatively simple driving and the like. Thus, SiC-based power mosfets (SiC mosfets) possess the innate advantages of SiC materials on the one hand and the advantages of unipolar transport conduction mechanisms on the other hand.
However, compared with the silicon-based MOSFET, the silicon carbide MOSFET has a lower channel mobility and a higher channel resistance Rch due to the poor channel interface state. Because the critical breakdown electric field of the silicon carbide is high, the doping concentration of the drift region can be improved, the thickness of the drift region can be reduced, and the resistance of the drift region can be reduced. Ultimately resulting in a significant increase in the inversion layer channel resistance Rch of silicon carbide MOSFETs over the overall device on-resistance Ron as compared to silicon-based MOSFETs.
Disclosure of Invention
In view of the above, it is desirable to provide a cell structure of a silicon carbide planar gate MOSFET and a method for fabricating the same, which can increase the cell density to reduce the channel resistance, thereby achieving the purpose of reducing the on-resistance of the silicon carbide MOSFET.
The technical scheme provided by the invention for achieving the purpose is as follows:
a silicon carbide planar gate MOSFET cell structure is characterized in that a silicon carbide epitaxial layer 001, a gate electrode 014 and an interlayer dielectric layer 015 are covered on the silicon carbide planar gate MOSFET cell structure from bottom to top, the doping type of the silicon carbide epitaxial layer 001 is a first conduction type, a plurality of first conduction type contact regions 013 and second conduction type contact regions 008 are arranged in the middle of the upper end of the silicon carbide epitaxial layer 001, the size of the first conduction type contact regions 013 is smaller than that of the second conduction type contact regions 008, and the first conduction type contact regions 013 are located in the middle of the second conduction type contact regions 008 and are distributed at intervals along the length direction of an MOSFET channel; the gate electrodes 014 cover both sides of the upper end of the second conductive type contact region 008, and a first distance between the gate electrodes at both sides is smaller than the width of the second conductive type contact region 008 and larger than the width of the first conductive type contact regions 013; the interlayer dielectric layers 015 cover the gate electrode 014, and a second distance between the interlayer dielectric layers 015 at two sides is smaller than the width of the first conductive type contact regions 013.
Further, the width of each first conductive type contact region 013 is 2um, the first pitch is 3um, the second pitch is 1.8 um.
Further, each first conductive type contact region 013 has a square shape in cross section.
Further, the first conductive type is a P type, and the second conductive type is an N type.
Further, the first conductive type may be an N-type, and the second conductive type may be a P-type.
A manufacturing method of a silicon carbide planar gate MOSFET cellular structure comprises the following steps:
s1, depositing a first mask layer 002 on the surface of a silicon carbide epitaxial layer 001 by adopting a chemical vapor deposition method, and photoetching the first mask layer 002 to etch a first ion implantation area 003 with a U-shaped section;
s2, implanting AL ions into the first ion implantation region 003 to form a P-well;
s3, removing the first mask layer 002, depositing a second mask layer 004 on the surface of the silicon carbide epitaxial layer 001 by using a chemical vapor deposition method, and performing photolithography on the second mask layer 004 to etch a second ion implantation region 005, where the second ion implantation region includes a plurality of first regions 006 and a plurality of second regions 007, each first region 006 has a U-shaped cross section, each second region 007 has a W-shaped cross section, and the first regions 006 and the second regions 007 are alternately connected along the length direction of the MOSFET channel and the inner walls of the masks on both sides are aligned;
s4, implanting second conductive ions into the second ion implantation regions 005 to form second conductive type contact regions 008 at the middle of the upper end of the silicon carbide epitaxial layer 001, wherein the second conductive type contact regions 008 include first contact regions 009 formed to communicate with each of the first regions 006, and second contact regions 010 formed to have a space region with each of the second regions 007;
s5, removing the second mask layer 004, depositing a third mask layer 011 on the surface of the silicon carbide epitaxial layer 001 by adopting a chemical vapor deposition method, and photoetching the third mask layer 011 to completely etch the third mask layer 011 corresponding to the interval region of each second contact region 010 to form a third ion implantation region 012;
s6, implanting first conductive ions into the third ion implantation region 012 to form a first conductive type contact region 013 at a spacing region of each of the second contact regions 010;
s7, removing the third mask layer 011, depositing gate electrodes 014 on two sides of the upper end of the silicon carbide epitaxial layer 010, wherein a first distance between the gate electrodes 014 on the two sides is smaller than the width of the second conductive type contact region 008 and larger than the width of the first conductive type contact region 013;
s8, interlayer dielectric layers 015 are deposited on the surfaces of the two-sided gate electrodes 014 such that the second spacing between the two-sided interlayer dielectric layers 015 is less than the width of the first conductivity type contact region 013.
Further, the first mask layer, the second mask layer and the third mask layer in steps S2, S4 and S6 respectively include a silicon nitride layer and a silicon dioxide layer, and the silicon dioxide layer is deposited on the upper surface of the silicon nitride layer.
Further, the first conductive ions are boron ions, and the second conductive ions are phosphorus or nitrogen ions.
Further, in steps S4, S6, and S8, the mask layer is removed by washing with a saturated solution of ammonium fluoride and hot phosphoric acid at 70 ℃, and removing impurities remaining on the surface by washing with an acid.
According to the silicon carbide planar gate MOSFET cellular structure and the manufacturing method thereof, a plurality of first conductive type contact regions and second conductive type contact regions are arranged in the middle of the upper end of the silicon carbide epitaxial layer; the plurality of first conduction type contact areas are positioned in the middle of the second conduction type contact area and are distributed at intervals along the length direction of the MOSFET channel, so that when the gate electrodes are deposited on the second conduction type contact area, the first distance between the gate electrodes on two sides is smaller than the width of the second conduction type contact area and larger than the width of the plurality of first conduction type contact areas. Therefore, the cell density can be improved, and the channel resistance is reduced, so that the purpose of reducing the on resistance of the silicon carbide MOSFET is realized.
Drawings
Fig. 1 is a schematic top view of a sic planar gate MOSFET cell structure according to a preferred embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a sic planar gate MOSFET cell structure provided by the present invention along line ab in fig. 1.
Fig. 3 is a schematic cross-sectional view of a sic planar gate MOSFET cell structure provided by the present invention along the line cd in fig. 1.
Fig. 4 is a schematic cross-sectional view of a first mask layer etched in the method for manufacturing the silicon carbide planar gate MOSFET cell structure according to the present invention.
FIG. 5 is a schematic cross-sectional view of a well region formed in the method for fabricating a SiC planar gate MOSFET cell structure according to the present invention.
Fig. 6 is a schematic cross-sectional view along line ab in fig. 1 after a second mask layer is etched in the method for manufacturing the silicon carbide planar gate MOSFET cell structure according to the present invention.
Fig. 7 is a schematic cross-sectional view along the cd line in fig. 1 after a second mask layer is etched in the method for manufacturing the silicon carbide planar gate MOSFET cell structure according to the present invention.
Fig. 8 is a schematic cross-sectional view taken along line ab in fig. 1 after a second conductive type contact region is formed in the method for fabricating the sic planar gate MOSFET cell structure according to the present invention.
Fig. 9 is a schematic cross-sectional view along the line cd in fig. 1 after forming a second conductive type contact region in the method for manufacturing a sic planar gate MOSFET cell structure according to the present invention.
Fig. 10 is a schematic cross-sectional view along line ab in fig. 1 after a third mask layer is etched in the method for manufacturing the silicon carbide planar gate MOSFET cell structure according to the present invention.
Fig. 11 is a schematic cross-sectional view along the cd line in fig. 1 after a third mask layer is etched in the method for manufacturing the silicon carbide planar gate MOSFET cell structure according to the present invention.
Fig. 12 is a schematic cross-sectional view taken along line ab in fig. 1 after a first conductive type contact region is formed in the method for fabricating a sic planar gate MOSFET cell structure according to the present invention.
Fig. 13 is a schematic cross-sectional view along the line cd in fig. 1 after a first conductive type contact region is formed in the method for manufacturing a sic planar gate MOSFET cell structure according to the present invention.
Fig. 14 is a schematic cross-sectional view along line ab in fig. 1 after deposition of a gate electrode and an interlayer dielectric layer in the method for fabricating a silicon carbide planar gate MOSFET cell structure according to the present invention.
Fig. 15 is a schematic cross-sectional view along the cd line in fig. 1 after a gate electrode and an interlayer dielectric layer are deposited in the method for manufacturing the sic planar gate MOSFET cell structure according to the present invention.
Description of the main elements
Silicon carbide planar gate MOSFET cell structure 1
Silicon carbide epitaxial layer 001
First ion implantation region 003003
Second ion implantation region 005
Second conductivity type contact region 008
Third ion implantation region 012
First conductivity type contact region 013
Interlayer dielectric layer 015
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a silicon carbide planar gate MOSFET cell structure 1. Referring to fig. 1-3, fig. 1 is a schematic top view of a preferred embodiment of a sic planar gate MOSFET cell structure provided in the present invention, fig. 2 is a schematic cross-sectional view of the sic planar gate MOSFET cell structure provided in the present invention along line ab in fig. 1, and fig. 3 is a schematic cross-sectional view of the sic planar gate MOSFET cell structure provided in the present invention along line cd in fig. 1. The silicon carbide planar gate MOSFET cellular structure 1 is covered with a silicon carbide epitaxial layer 001, a gate electrode 014 and an interlayer dielectric layer 015 from bottom to top.
The doping type of the silicon carbide epitaxial layer 001 is a first conductivity type. A plurality of first conductive contact regions 013 and second conductive contact regions 008 are disposed in the middle of the upper end of the silicon carbide epitaxial layer 001. The size of the number of first conductive type contact regions 013 is smaller than the size of the second conductive type contact regions 008. The plurality of first conductivity type contact regions 013 are located in the middle of the second conductivity type contact regions 008 and are spaced apart along the length of the MOSFET channel. In the present embodiment, each first conductivity type contact region 013 has a square shape in cross section.
The gate electrodes 014 cover both sides of the upper end of the second conductive type contact region 008, and a first distance C between the gate electrodes at both sides is smaller than the width a of the second conductive type contact region 008 and larger than the width X of the first conductive type contact regions 013.
The interlayer dielectric layers 015 cover the gate electrode 014, and a second distance B between the interlayer dielectric layers 015 at two sides is smaller than the width X of the first conductive type contact regions 013.
The source contact regions in the conventional structure are changed into a plurality of source contact regions distributed at intervals, and the width of the source contact regions distributed at intervals is larger than the second spacing B (i.e., cont openings) between the interlayer dielectric layers 015 in the conventional structure and smaller than the first spacing C between the gate electrodes 014 in the conventional structure. In this way, the first pitch C between the gate electrodes 014 can be reduced, thereby increasing the cell density, reducing the channel resistance, and further achieving the purpose of reducing the on-resistance of the silicon carbide MOSFET.
For example, in the conventional structure, the pitch of the gate electrode poly is 5um, wherein the width of the P region at the middle position is 2um, the total width of the poly is 5um, and then the total width of the cell is 10 um. In the structure provided by the present invention, the first pitch of the gate electrode 014 is 3um, the widths of the P + regions distributed at intervals are still 2um, and the width of the gate electrode 014 is 5um, but the total width of the cell can be reduced to 8 um. Therefore, under the condition of the same area, the cell density can be improved by 20%, and the equivalent channel resistance Rch can be reduced by 20%.
In the present embodiment, each first conductivity type contact region 013 has a width of 2 um; the first distance C is 3 um; the second distance B is 1.8 um.
In this embodiment, the first conductive type is a P-type, and the second conductive type is an N-type. In other embodiments, the first conductivity type may be N-type and the second conductivity type may be P-type.
The invention also provides a manufacturing method of the silicon carbide planar gate MOSFET cellular structure. The method for manufacturing the silicon carbide planar gate MOSFET unit cell structure comprises the following steps:
s1, referring to fig. 4, depositing a first mask layer 002 on the surface of a silicon carbide epitaxial layer 001 by using a chemical vapor deposition method, and performing photolithography on the first mask layer 002 to etch a first ion implantation region 003 with a U-shaped cross section.
S2, please refer to fig. 5, AL ions are implanted into the first ion implantation region 003 to form a P-well. Specifically, Al ions are implanted at 400 ℃ by adopting 500-1500 Kev energy and 1E 12-1E 15 dosage.
S3, please refer to fig. 6 and 7, removing the first mask layer 002, depositing a second mask layer 004 on the surface of the silicon carbide epitaxial layer 001 by using a chemical vapor deposition method, and performing photolithography on the second mask layer 004 to etch a second ion implantation region 005, where the second ion implantation region includes a plurality of first regions 006 and a plurality of second regions 007, each of the first regions 006 has a U-shaped cross section, each of the second regions 007 has a W-shaped cross section, and the first regions 006 and the second regions 007 are alternately connected along the length direction of the MOSFET channel and the inner walls of the masks on both sides are aligned.
S4, referring to fig. 8 and 9, second conductive ions are implanted into the second ion implantation regions 005 to form second conductive type contact regions 008 at a middle portion of an upper end of the silicon carbide epitaxial layer 001, where the second conductive type contact regions 008 include first contact regions 009 formed to communicate with each of the first regions 006, and second contact regions 010 formed to have a space region corresponding to each of the second regions 007. In this embodiment, the second conductive ions are phosphorus or nitrogen ions, and the implantation process is performed by implanting phosphorus or nitrogen ions with an energy of 50 to 200Kev and a dose of 1E14 to 1E 16.
S5, please refer to fig. 10 to 11, removing the second mask layer 004, depositing a third mask layer 011 on the surface of the silicon carbide epitaxial layer 001 by using a chemical vapor deposition method, and performing photolithography on the third mask layer 011 to etch the third mask layer 011 corresponding to the spacing region of each second contact region 010, so as to form a third ion implantation region 012;
s6, referring to fig. 12 to 13, first conductive ions are implanted into the third ion implantation region 012 to form a first conductive type contact region 013 at a spacing region of each of the second contact regions 010. In this embodiment, the first conductive ions are boron ions, and the implantation process is performed at an energy of 50 to 200Kev and a dose of 1E14 to 1E 16.
S7, please refer to fig. 14 and 15, removing the third mask layer 011, depositing gate electrodes 014 on two sides of the upper end of the silicon carbide epitaxial layer 010, wherein a first distance between the gate electrodes 014 on the two sides is smaller than the width of the second conductive type contact region 008 and larger than the width of the first conductive type contact region 013;
s8, interlayer dielectric layers 015 are deposited on the surfaces of the two-sided gate electrodes 014 such that the second spacing between the two-sided interlayer dielectric layers 015 is less than the width of the first conductivity type contact region 013.
In this embodiment, the first mask layer, the second mask layer and the third mask layer in steps S2, S4 and S6 respectively include a silicon nitride layer and a silicon dioxide layer, and the silicon dioxide layer is deposited on the upper surface of the silicon nitride layer.
In this embodiment, in steps S4, S6, and S8, the mask layer is removed by washing with a saturated solution of ammonium fluoride and hot phosphoric acid at 70 ℃, and removing impurities remaining on the surface by washing with an acid.
In summary, the silicon carbide planar gate MOSFET cell structure and the manufacturing method provided by the present invention have a plurality of first conductive contact regions 013 and second conductive contact regions 008 disposed at the middle portion of the upper end of the silicon carbide epitaxial layer 10; the plurality of first conductive type contact regions 013 are located in the middle of the second conductive type contact regions 008 and are spaced apart along the length direction of the MOSFET channel, such that when the gate electrodes 014 are deposited on the second conductive type contact regions 008, the first distance C between the gate electrodes at both sides is smaller than the width a of the second conductive type contact regions 008 and larger than the width X of the plurality of first conductive type contact regions 013. Therefore, the cell density can be improved, and the channel resistance is reduced, so that the purpose of reducing the on resistance of the silicon carbide MOSFET is realized.
The foregoing is a more detailed description of the invention in connection with specific/preferred embodiments and is not intended to limit the practice of the invention to those descriptions. It will be apparent to those skilled in the art that various substitutions and modifications can be made to the described embodiments without departing from the spirit of the invention, and these substitutions and modifications should be considered to fall within the scope of the invention. In the description herein, references to the description of the term "one embodiment," "some embodiments," "preferred embodiments," "an example," "a specific example," or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Claims (9)
1. A silicon carbide planar gate MOSFET cellular structure is characterized in that a silicon carbide epitaxial layer 001, a gate electrode 014 and an interlayer dielectric layer 015 are covered on the silicon carbide planar gate MOSFET cellular structure from bottom to top, the doping type of the silicon carbide epitaxial layer 001 is a first conduction type, a plurality of first conduction type contact regions 013 and second conduction type contact regions 008 are arranged in the middle of the upper end of the silicon carbide epitaxial layer 001, the size of the first conduction type contact regions 013 is smaller than that of the second conduction type contact regions 008, and the first conduction type contact regions 013 are located in the middle of the second conduction type contact regions 008 and are distributed at intervals along the length direction of an MOSFET channel; the gate electrodes 014 cover both sides of the upper end of the second conductive type contact region 008, and a first distance between the gate electrodes at both sides is smaller than the width of the second conductive type contact region 008 and larger than the width of the first conductive type contact regions 013; the interlayer dielectric layers 015 cover the gate electrode 014, and a second distance between the interlayer dielectric layers 015 at two sides is smaller than the width of the first conductive type contact regions 013.
2. The silicon carbide planar gate MOSFET cell structure of claim 1, wherein each first conductivity type contact region 013 has a width of 2um, the first pitch is 3um, and the second pitch is 1.8 um.
3. The silicon carbide planar gate MOSFET cell structure of claim 1, wherein each first conductivity type contact region 013 has a square shape in cross section.
4. The silicon carbide planar gate MOSFET cell structure of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.
5. The silicon carbide planar gate MOSFET cell structure of claim 1, wherein the first conductivity type can be N-type and the second conductivity type is P-type.
6. A manufacturing method of a silicon carbide planar gate MOSFET cellular structure is characterized by comprising the following steps:
s1, depositing a first mask layer 002 on the surface of a silicon carbide epitaxial layer 001 by adopting a chemical vapor deposition method, and photoetching the first mask layer 002 to etch a first ion implantation area 003 with a U-shaped section;
s2, implanting AL ions into the first ion implantation region 003 to form a P-well;
s3, removing the first mask layer 002, depositing a second mask layer 004 on the surface of the silicon carbide epitaxial layer 001 by using a chemical vapor deposition method, and performing photolithography on the second mask layer 004 to etch a second ion implantation region 005, where the second ion implantation region includes a plurality of first regions 006 and a plurality of second regions 007, each first region 006 has a U-shaped cross section, each second region 007 has a W-shaped cross section, and the first regions 006 and the second regions 007 are alternately connected along the length direction of the MOSFET channel and the inner walls of the masks on both sides are aligned;
s4, implanting second conductive ions into the second ion implantation regions 005 to form second conductive type contact regions 008 at the middle of the upper end of the silicon carbide epitaxial layer 001, wherein the second conductive type contact regions 008 include first contact regions 009 formed to communicate with each of the first regions 006, and second contact regions 010 formed to have a space region with each of the second regions 007;
s5, removing the second mask layer 004, depositing a third mask layer 011 on the surface of the silicon carbide epitaxial layer 001 by adopting a chemical vapor deposition method, and photoetching the third mask layer 011 to completely etch the third mask layer 011 corresponding to the interval region of each second contact region 010 to form a third ion implantation region 012;
s6, implanting first conductive ions into the third ion implantation region 012 to form a first conductive type contact region 013 at a spacing region of each of the second contact regions 010;
s7, removing the third mask layer 011, depositing gate electrodes 014 on two sides of the upper end of the silicon carbide epitaxial layer 010, wherein a first distance between the gate electrodes 014 on the two sides is smaller than the width of the second conductive type contact region 008 and larger than the width of the first conductive type contact region 013;
s8, interlayer dielectric layers 015 are deposited on the surfaces of the two-sided gate electrodes 014 such that the second spacing between the two-sided interlayer dielectric layers 015 is less than the width of the first conductivity type contact region 013.
7. The method of claim 6, wherein the first mask layer, the second mask layer and the third mask layer in steps S2, S4 and S6 respectively comprise a silicon nitride layer and a silicon dioxide layer, and the silicon dioxide layer is deposited on the upper surface of the silicon nitride layer.
8. The method of claim 6, wherein the first conductive ions are boron ions and the second conductive ions are phosphorous or nitrogen ions.
9. The method of claim 6, wherein the mask layer is removed in steps S4, S6, and S8 by rinsing with a saturated solution of ammonium fluoride and 70 deg.C hot phosphoric acid, and removing the impurities remaining on the surface by acid rinsing.
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