CN219435880U - Trench MOSFET transistor - Google Patents

Trench MOSFET transistor Download PDF

Info

Publication number
CN219435880U
CN219435880U CN202320007254.0U CN202320007254U CN219435880U CN 219435880 U CN219435880 U CN 219435880U CN 202320007254 U CN202320007254 U CN 202320007254U CN 219435880 U CN219435880 U CN 219435880U
Authority
CN
China
Prior art keywords
gate
field plate
field
mosfet transistor
field plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202320007254.0U
Other languages
Chinese (zh)
Inventor
付红霞
章剑锋
崔京京
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Ruineng Weilan Semiconductor Technology Co ltd
Original Assignee
Ruineng Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ruineng Semiconductor Technology Co ltd filed Critical Ruineng Semiconductor Technology Co ltd
Application granted granted Critical
Publication of CN219435880U publication Critical patent/CN219435880U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a trench MOSFET transistor, and relates to the technical field of semiconductor devices. The trench MOSFET transistor includes: a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is provided; a well region of a second doping type disposed within the epitaxial layer; a gate trench structure disposed within the well region; a gate trench structure comprising: a gate electrode disposed on a side away from the first surface; a plurality of first field plates disposed between the gate and the bottom of the gate trench structure, each of the first field plates having the same length in a direction parallel to the first surface; the grid electrode is insulated from the first field plate; the distance between two adjacent first field plates in a direction perpendicular to the first surface is determined by the thickness of the respective first field plate. According to the method and the device, the electric field distribution in the groove type MOSFET transistor can be ensured to be uniform, and the manufacturing process is simplified.

Description

Trench MOSFET transistor
Cross Reference to Related Applications
This application claims priority from chinese patent application 202211114593.5 entitled "trench MOSFET transistor and method of making same," filed on the year 2022, month 09, and 14, the entire contents of which are incorporated herein by reference.
Technical Field
The application belongs to the technical field of semiconductor devices, and particularly relates to a trench MOSFET transistor.
Background
The metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor) is a voltage-type control device, has a simple driving circuit, small driving power, high switching speed and high working frequency.
In a trench MOSFET structure of a single Field Plate (FP), a peak electric field occurs at the bottom of a drift region at the side of a gate trench structure, and thus, the electric field distribution appears as a triangle, and the electric field distribution is uneven.
In order to realize uniform electric field distribution in the trench MOSFET, the multi-step MOSFET structure designs a dielectric layer in contact with the deep trench and the drift region into a plurality of steps. That is, in the direction perpendicular to the substrate, the closer the field plate is to the substrate in the trench, the shorter the length of the field plate in the direction parallel to the substrate, and the thicker the dielectric layer between the field plate and the drift region; the further away the field plate is from the substrate in the trench in a direction perpendicular to the substrate, the longer the field plate is in a direction parallel to the substrate, the thinner the dielectric layer between the field plate and the drift region. However, in the case of multi-step MOSFET structure fabrication, multiple field plate alignments are required to maintain the symmetry of the stepped dielectric layer.
Disclosure of Invention
The embodiment of the application provides a trench MOSFET transistor, which can ensure that the electric field distribution in the trench MOSFET transistor is uniform and simplify the manufacturing process.
In a first aspect, embodiments of the present application provide a trench MOSFET transistor, including:
a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;
a well region of a second doping type disposed within the epitaxial layer;
a gate trench structure disposed within the well region;
the gate trench structure includes:
a gate electrode disposed on a side remote from the first surface;
a plurality of first field plates disposed between the gate and the bottom of the gate trench structure, each of the first field plates having the same length in a direction parallel to the first surface; the grid is insulated from the first field plate; the distance between two adjacent first field plates in the direction perpendicular to the first surface is determined by the thickness of each first field plate;
the second doping type is opposite to the first doping type.
In some alternative embodiments, the thickness of each first field plate is the same in a direction perpendicular to the first surface and from the gate to the bottom of the gate trench structure, and the distance between two adjacent first field plates sequentially increases.
In some alternative embodiments, in a direction perpendicular to the first surface and from the gate to the bottom of the gate trench structure, the thickness between two adjacent first field plates decreases in sequence, and the distance between two adjacent first field plates is equal.
In some alternative embodiments, the trench MOSFET transistor further comprises:
and at least one second field plate arranged in the grid groove structure, wherein the second field plate is connected with each first field plate.
In some alternative embodiments, the second field plate is connected to a center point of each of the first field plates, the center point being a center point of a cross-sectional pattern of each of the first field plates in a plane perpendicular to the first surface.
In some alternative embodiments, the first field plate has a rectangular cross-sectional shape in a plane perpendicular to the first surface.
In some alternative embodiments, the material of the first field plate is polysilicon.
In some alternative embodiments, the trench MOSFET transistor further comprises:
and the doped region is arranged in the well region and is in contact with the grid groove structure and of the first doping type.
In some alternative embodiments, the substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.
In some alternative embodiments, the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type.
The embodiment of the application provides a trench MOSFET transistor, which comprises: the epitaxial layer is arranged in the well region of the epitaxial layer, the gate groove structure is arranged in the well region and comprises a plurality of first field plates arranged between the gate and the bottom of the gate groove structure, and the distance between two adjacent first field plates is determined by the thickness of each first field plate in the direction perpendicular to the first surface. That is, the distance between two adjacent field plates is determined according to the thickness of each first field plate, the thickness of each first field plate is the same, the charge compensation effect (charge balance principle) sequentially decreases along with the sequential increasing of the distance between two adjacent first field plates, the distance between two adjacent first field plates is the same, the charge compensation effect sequentially decreases along with the sequential decreasing of the thickness between two adjacent first field plates, and then the drift regions on two sides of the gate trench structure are respectively subjected to charge compensation to different degrees through the thickness of each first field plate and the distance between two adjacent field plates, so that the longitudinal electric fields (i.e., the electric fields in the direction perpendicular to the first surface) of the drift regions on two sides of the gate trench structure form rectangular distribution, and the stretching of the depletion region can greatly improve the withstand voltage efficiency of the trench MOSFET device. In the direction parallel to the first surface, the first field plates have the same length, so that multiple field plate alignments are not needed to keep the stepped dielectric layer symmetrical during the manufacture of the trench MOSFET, and the manufacturing process is simplified.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of an embodiment of a trench MOSFET transistor provided herein;
fig. 2 is another schematic structural diagram of an embodiment of a trench MOSFET transistor provided herein;
fig. 3 is a schematic structural diagram of another embodiment of a trench MOSFET transistor provided herein;
fig. 4 is a schematic diagram of still another structure of an embodiment of a trench MOSFET transistor provided herein;
fig. 5 is a flow chart of an embodiment of a method for manufacturing a trench MOSFET transistor provided herein;
FIG. 6 is a schematic cross-sectional structure of a substrate provided herein;
FIG. 7 is a schematic cross-sectional view of a well region formed according to the present application;
FIG. 8 is a schematic cross-sectional view of a doped region formed as provided herein;
FIG. 9 is a schematic cross-sectional view of a trench structure formed as provided herein;
fig. 10 is a schematic cross-sectional structure of forming a first gate oxide layer provided herein;
FIG. 11 is a schematic cross-sectional view of a first field plate formed in accordance with the teachings of the present application;
FIG. 12 is a schematic cross-sectional view of a second gate oxide layer formed according to the present disclosure;
FIG. 13 is a schematic cross-sectional structure of forming all of the field plates and all of the second gate oxide provided herein;
fig. 14 is a schematic cross-sectional structure of forming a gate trench structure provided herein.
Reference numerals illustrate:
1. a substrate; 11. a first surface; 12. a second surface.
2. And (5) an epitaxial layer.
3. And a well region.
4. A gate trench structure; 41. a gate; 42. a first field plate; 43. a second field plate; 44. a trench structure; 45. a first gate oxide layer; 46. a second gate oxide layer; 47. and isolating the dielectric layer.
5. And a doped region.
6. And a drain structure.
7. A source electrode structure.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
Fig. 1 shows a schematic structural diagram of an embodiment of a trench MOSFET transistor according to an embodiment of the present application.
As shown in fig. 1, the trench MOSFET transistor provided in the embodiment of the present application may include:
a substrate 1 of a first doping type, the substrate 1 comprising a first surface 11, the first surface 11 being provided with an epitaxial layer 2 of the first doping type;
a well region 3 of a second doping type provided within the epitaxial layer 2;
a gate trench structure 4 disposed within the well region 3;
gate trench structure 4, comprising:
a gate electrode 41 disposed on a side remote from the first surface 11;
a plurality of mutually insulated first field plates 42 disposed between the gate 41 and the bottom of the gate trench structure 4, each first field plate 42 having the same length in a direction parallel to the first surface 11; the gate 41 is insulated from the first field plate 42; the distance between two adjacent first field plates 42 in a direction perpendicular to the first surface 11 is determined by the thickness of each first field plate 42;
the second doping type is opposite to the first doping type.
The embodiment of the application provides a trench MOSFET transistor, which comprises: the epitaxial layer is arranged in the well region of the epitaxial layer, the gate groove structure is arranged in the well region and comprises a plurality of first field plates arranged between the gate and the bottom of the gate groove structure, and the distance between two adjacent first field plates is determined by the thickness of each first field plate in the direction perpendicular to the first surface. That is, the distance between two adjacent field plates is determined according to the thickness of each first field plate, the thickness of each first field plate is the same, the charge compensation effect (charge balance principle) sequentially decreases along with the sequential increasing of the distance between two adjacent first field plates, the distance between two adjacent first field plates is the same, the charge compensation effect sequentially decreases along with the sequential decreasing of the thickness between two adjacent first field plates, and then the drift regions on two sides of the gate trench structure are respectively subjected to charge compensation to different degrees through the thickness of each first field plate and the distance between two adjacent field plates, so that the longitudinal electric fields (i.e., the electric fields in the direction perpendicular to the first surface) of the drift regions on two sides of the gate trench structure form rectangular distribution, and the stretching of the depletion region can greatly improve the withstand voltage efficiency of the trench MOSFET device. In the direction parallel to the first surface, the first field plates have the same length, so that multiple field plate alignments are not needed to keep the stepped dielectric layer symmetrical during the manufacture of the trench MOSFET, and the manufacturing process is simplified.
In this embodiment, the first doping type may be N-type, and the second doping type may be P-type. The substrate 1 may be a silicon carbide substrate 1. The substrate 1 of the first doping type may be an N-type substrate 1; the epitaxial layer 2 of the first doping type may be an N-type epitaxial layer 2; the well region 3 of the second doping type may be a P-type well region 3.
Alternatively, the plurality of first field plates 42 between the gate 41 and the bottom of the gate trench structure 4 may be insulated from each other by providing a second gate oxide layer 46 between adjacent two first field plates 42. Accordingly, the gate 41 may be insulated from the first field plate 42 by disposing a second gate oxide layer 46 between the gate 41 and the first field plate 42.
The material of the second gate oxide layer 46 may be silicon dioxide (SiO 2 ) Commonly known as silicon oxide.
The second doping type is opposite to the first doping type, it being understood that the first doping type may be one of N-type or P-type and the second doping type may be the other of N-type or P-type.
By arranging the first field plate 42 in the gate trench structure 4, since the potential of the first field plate 42 is set to be low, in the drain reverse bias state, the first field plate 42 has enough charge to be coupled with the drift region, according to the charge balance principle, the corresponding drift region of the first field plate 42 can be coupled to induce a depletion region and even be completely depleted, the net charge of the drift region is zero, the longitudinal electric field distribution of the trench type MSOFET transistor can show rectangular distribution similar to that of a super junction device, so that the voltage withstand capability of the trench type MOSFET transistor device is improved, or the doping concentration of the epitaxial layer 2 can be increased while the voltage withstand capability of a retainer piece is unchanged, and the on resistance of the trench type MOSFET transistor device is reduced.
In some alternative embodiments, the substrate 1 may further comprise a second surface 12 opposite the first surface 11, the second surface 12 being provided with the drain structure 6.
In some alternative embodiments, as shown in fig. 1 and 2, the cross-sectional shape of the first field plate 42 is rectangular or inverted "V" shaped in a plane perpendicular to the first surface 11. Fig. 1 shows a schematic structural view of the first field plate 42 having a rectangular cross-sectional shape in a plane perpendicular to the first surface 11, and fig. 2 shows a schematic structural view of the first field plate 42 having an inverted "V" shape in a plane perpendicular to the first surface 11.
The charge compensation effect on the drift region is more linear and the electric field distribution is more uniform in the direction perpendicular to the first surface 11 of the first field plate 42 having the shape of an inverted "V" with respect to the first field plate 42 having the shape of a rectangle.
In this embodiment, the cross-sectional shape of the first field plate 42 on the plane perpendicular to the first surface 11 is rectangular or inverted "V" as an example, and in practical implementation, the cross-sectional shape of the first field plate 42 on the plane perpendicular to the first surface 11 may be set according to practical situations, and is not limited herein.
As shown in fig. 1 and 3, in some alternative embodiments, the thickness of each first field plate 42 is the same in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, and the distance between two adjacent first field plates 42 sequentially increases.
The direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4 can be understood as the X-direction shown in fig. 1 and 3.
Along the X-direction, and closer to the first surface 11, the distance between two adjacent first field plates 42 is larger, the distribution density of the first field plates 42 is sparse, and the charge compensation effect is weaker; along the X direction, the farther from the first surface 11, the smaller the distance between two adjacent first field plates 42, the denser the distribution density of the first field plates 42, and the stronger the charge compensation effect, so that the depletion of the side drift region of the gate trench structure 4 gradually increases from the bottom of the gate trench structure 4 to the top of the gate trench structure 4, and further the longitudinal electric fields of the drift regions on two sides of the gate trench structure 4 form rectangular distribution, thereby ensuring the uniform distribution of the electric fields in the trench MOSFET transistor.
Optionally, in the direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, the thickness of each first field plate 42 is the same, and the distances between two adjacent first field plates 42 are sequentially increased in an equal-difference sequence, so that the longitudinal electric fields of the drift regions on two sides of the gate trench structure 4 form rectangular distribution, and the electric fields in the trench MOSFET transistors are ensured to be uniformly distributed.
As shown in fig. 2 and 4, in some alternative embodiments, in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, the thickness between two adjacent first field plates 42 decreases in sequence, and the distance between two adjacent first field plates 42 is equal.
The distance between two adjacent first field plates 42 is the same, and the depletion effects of the drift regions corresponding to the first field plates 42 of different thicknesses are also different. Specifically, along the X direction, and closer to the first surface 11, the thickness of the first field plate 42 is thinner, which is equivalent to the sparse distribution density of the first field plate 42, and the weaker the charge compensation effect; along the X direction, and further away from the first surface 11, the thickness of the first field plate 42 is thicker, which is equivalent to that the distribution density of the first field plate 42 is denser, and the charge compensation effect is stronger, so that the depletion of the side drift region of the gate trench structure 4 is gradually enhanced from the bottom of the gate trench structure 4 to the top of the gate trench structure 4, and further, the longitudinal electric fields of the drift regions at two sides of the gate trench structure 4 form rectangular distribution, and the electric field in the trench MOSFET transistor is ensured to be uniformly distributed.
Optionally, in the direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, the thicknesses between two adjacent first field plates 42 decrease in an equal-differential sequence, and the distances between two adjacent first field plates 42 are equal, so that the longitudinal electric fields of the drift regions on two sides of the gate trench structure 4 form rectangular distribution, and the electric fields in the trench MOSFET transistor are ensured to be uniformly distributed.
As shown in fig. 3 and 4, in some alternative embodiments, the trench MOSFET transistor may further include:
at least one second field plate 43 arranged in the gate trench structure 4, the second field plate 43 being connected to the respective first field plate 42.
In this embodiment, the material of the first field plate 42 and the material of the second field plate 43 may be polysilicon.
In the present embodiment, the electric potential between the respective first field plates 42 can be kept equal by providing at least one second field plate 43 connected to the respective first field plates 42 in the gate trench structure 4.
In this embodiment, taking the gate trench structure 4 with one second field plate 43 as an example, in practical implementation, the number of second field plates 43 in the gate trench structure 4 may be set according to practical situations. For example, the number of second field plates 43 is the same as the number of first field plates 42, each first field plate 42 is connected to a different second field plate 43, and each second field plate 43 is connected to each other.
In some alternative embodiments, the second field plates 43 may be connected to a center point of each first field plate 42, which is a center point of a cross-sectional pattern of each first field plate 42 in a plane perpendicular to the first surface 11.
In the present embodiment, the manufacturing process can be simplified by connecting the second field plates 43 with the center points of the respective first field plates 42 such that the first field plates 42 are axisymmetric with respect to the second field plates 43 on a plane perpendicular to the first surface 11.
In other alternative embodiments, the electrical connection between the first field plates 42 may be implemented by providing a through hole at the periphery of the chip, and forming a short-circuit connection with the source structure 7 or with the gate 41 metal, so as to implement an equipotential between the first field plates 42, and all low when the device blocks high voltage.
In some alternative embodiments, the trench MOSFET transistor further comprises:
a doped region 5 of the first doping type is arranged in the well region 3 and in contact with the gate trench structure 4.
The doped region 5 of the first doping type may be an N-type doped region 5.
Based on the trench MOSFET transistor provided in the above embodiment, the present application also provides a trench MOSFET transistor manufacturing method. A method of manufacturing the trench MOSFET transistor will be described below.
It should be noted that the first doping type is N-type and the second doping type is P-type in this embodiment. However, in actual implementation, the substrate 1 is not limited to the N-type, and may be P-type. When the substrate 1 is P-type, the conductivity type of the structures of the epitaxial layer 2, the well region 3, and the doped region 5 is also changed accordingly.
Fig. 5 is a schematic flow chart of an embodiment of a method for manufacturing a trench MOSFET transistor according to the present application.
As shown in fig. 5, the trench MOSFET transistor manufacturing method may include S501 to S506. Referring to fig. 6 to 14 together, fig. 6 to 14 are schematic cross-sectional views corresponding to a series of processes in the method for manufacturing a trench MOSFET transistor provided in the present application.
S501, providing a substrate 1 of a first doping type, wherein the substrate 1 comprises a first surface 11, and an epitaxial layer 2 of the first doping type is arranged on the first surface 11.
In the present embodiment, the substrate 1 of the first doping type is an N-type substrate 1.
In some alternative embodiments, as shown in fig. 6, an N-type substrate 1 is provided first, and then an epitaxy is performed on the substrate 1 to form an N-type epitaxial layer 22.
S502, forming a well region 3 of the second doping type on a surface of the epitaxial layer 2 remote from the first surface 11.
In this embodiment, the well region 3 of the second doping type is a P-type well region 3.
As shown in fig. 7, forming the well region 3 of the second doping type on the surface of the epitaxial layer 2 remote from the first surface 11 may include:
ion doping of the second doping type is performed on the surface of the epitaxial layer 2 remote from the first surface 11 to form a well region 3 of the second doping type.
As shown in fig. 8, in some alternative embodiments, after forming the well region 3 of the second doping type on the surface of the epitaxial layer 2 remote from the first surface 11, it may further include:
within the well region 3, a doped region 5 of a first doping type is formed in contact with the gate trench structure 4.
S503, forming a trench structure 44 in the epitaxial layer 2.
As shown in fig. 9, forming a trench structure 44 within the epitaxial layer 2 may include:
a trench etch is performed down the surface of the epitaxial layer 2 remote from the first surface 11 to form a trench structure 44 in the epitaxial layer 2.
Specifically, a mask may be used to etch a trench down on a surface of the epitaxial layer 2 away from the first surface 11, so as to form a trench structure 44 in the epitaxial layer 2.
S504, a first gate oxide layer 45 is formed in the trench structure 44.
As shown in fig. 10, forming the first gate oxide layer 45 within the trench structure 44 may include:
the upper surface of trench structure 44 is oxidized to form a first gate oxide layer 45 within trench structure 44.
S505, forming a first field plate 42 on the first gate oxide layer 45, forming a second gate oxide layer 46 on the first field plate 42 until all of the first field plate 42 is formed in the trench structure 44, and forming a second gate oxide layer 46 on the last first field plate 42; each first field plate 42 has the same length in a direction parallel to the first surface 11; the first field plates 42 are insulated from each other, and the grid 41 is insulated from the first field plates 42; the distance between two adjacent first field plates 42 in a direction perpendicular to the first surface 11 is determined by the thickness of the respective first field plate 42.
In this embodiment, the manufacturing process in which the cross-sectional shape of the first field plate 42 is rectangular in a plane perpendicular to the first surface 11 is taken as an example. As shown in fig. 11, a layer of polysilicon is deposited on the first gate oxide layer 45 and is subjected to photolithography to form a first field plate 42; as shown in fig. 12, a second gate oxide layer 46 is deposited on the upper surface of the first field plate 42; the foregoing steps are repeated until all of the first field plates 42 are formed within the trench structure 44 and a second gate oxide layer 46 is formed over the last first field plate 42. All of the first field plates 42 formed within the trench structure 44, and a layer of second gate oxide 46 formed on the last first field plate 42 are shown in fig. 13.
The material of the first gate oxide layer 45 and the material of the second gate oxide layer 46 may be polysilicon.
The process of fabricating the first field plate 42 with the cross-sectional shape of an inverted "V" shape in a plane perpendicular to the first surface 11 is similar to the process of fabricating the first field plate 42 with the cross-sectional shape of a rectangle in a plane perpendicular to the first surface 11, except that after depositing a layer of polysilicon on the first gate oxide layer 45, an inverted "V" shaped field plate is formed using different etching rates of different crystalline phases of polysilicon. The manufacturing process of the first field plate 42 having the inverted V-shape in cross section is not described herein.
S506, forming a gate 41 and an isolation dielectric layer 47 on the second gate oxide layer 46 to form a gate trench structure 4.
As shown in fig. 14, a gate 41 is formed on the second gate oxide layer 46, and the upper surface of the gate 41 is oxidized to form an isolation dielectric layer 47, so as to form the gate trench structure 4.
In some alternative embodiments, the thickness of each first field plate 42 is the same in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, and the distance between two adjacent first field plates 42 increases sequentially.
In some alternative embodiments, the thickness between two adjacent first field plates 42 decreases in sequence in a direction perpendicular to the first surface 11 and from the gate 41 to the bottom of the gate trench structure 4, and the distance between two adjacent first field plates 42 is equal.
In some alternative embodiments, forming the first field plate 42 on the first gate oxide layer 45, forming the second gate oxide layer 46 on the first field plate 42 until all of the first field plate 42 is formed within the trench structure 44, and forming the second gate oxide layer 46 on the last first field plate 42 may further include:
a portion of the first field plate 42 and the second field plate 43 is formed on the first gate oxide layer 45, a second gate oxide layer 46 is formed on the first field plate 42 and on a portion of the second field plate 43 until all of the first field plate 42 and all of the second field plate 43 are formed within the trench structure 44, and a second gate oxide layer 46 is formed on the last one of the first field plates 42.
In some alternative embodiments, the second field plates 43 are connected to a center point of each first field plate 42, which is a center point of a cross-sectional pattern of each first field plate 42 in a plane perpendicular to the first surface 11.
In some alternative embodiments, the cross-sectional shape of the first field plate 42 is rectangular in a plane perpendicular to the first surface 11.
In some alternative embodiments, the material of first field plate 42 is polysilicon.
In some alternative embodiments, the substrate 1 further includes a second surface 12 opposite to the first surface 11, and after forming the gate 41 and the isolation medium layer 47 on the second gate oxide layer 46 to form the gate trench structure 4, the method may further include:
a drain structure 6 is formed at the second surface 12.
In some alternative embodiments, after forming the gate 41 and the isolation medium layer 47 on the second gate oxide layer 46 to form the gate trench structure 4, the method may further include:
a source structure 7 is formed on a side of the well region 3 remote from the first surface 11, the source structure 7 being in contact with the isolation dielectric layer 47, the doped region 5 and the well region 3.
In some alternative embodiments, the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type.
The trench MOSFET transistor manufacturing method in the above embodiment, in which the respective structures and advantageous effects have been described in detail in the embodiment concerning the trench MOSFET transistor, will not be described in detail here.
In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, which are intended to be included in the scope of the present application.

Claims (9)

1. A trench MOSFET transistor, comprising:
a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;
a well region of a second doping type disposed within the epitaxial layer;
a gate trench structure disposed within the well region;
the gate trench structure includes:
a gate electrode disposed on a side remote from the first surface;
a plurality of first field plates disposed between the gate and the bottom of the gate trench structure, each of the first field plates having the same length in a direction parallel to the first surface; the grid is insulated from the first field plate; the distance between two adjacent first field plates in the direction perpendicular to the first surface is determined by the thickness of each first field plate;
the trench MOSFET transistor further includes:
at least one second field plate disposed within the gate trench structure, the second field plate being connected to each of the first field plates; the second doping type is opposite to the first doping type.
2. The trench MOSFET transistor of claim 1 wherein the thickness of each of said first field plates is the same in a direction perpendicular to said first surface and from said gate to the bottom of said gate trench structure, and the distance between adjacent ones of said first field plates increases in sequence.
3. The trench MOSFET transistor of claim 1, wherein a thickness between adjacent two of said first field plates decreases in sequence and a distance between adjacent two of said first field plates is equal in a direction perpendicular to said first surface and from said gate to a bottom of said gate trench structure.
4. The trench MOSFET transistor of claim 1 wherein said second field plate is connected to a center point of each of said first field plates, said center point being a center point of a cross-sectional pattern of each of said first field plates in a plane perpendicular to said first surface.
5. The trench MOSFET transistor according to any one of claims 1 to 4, wherein the cross-sectional shape of the first field plate is rectangular in a plane perpendicular to the first surface.
6. The trench MOSFET transistor according to any one of claims 1 to 4, wherein the material of the first field plate is polysilicon.
7. The trench MOSFET transistor according to any one of claims 1 to 4, characterized in that it further comprises:
and the doped region is arranged in the well region and is in contact with the grid groove structure and of the first doping type.
8. The trench MOSFET transistor according to any one of claims 1-4, wherein the substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.
9. The trench MOSFET transistor according to any one of claims 1-4, wherein the first doping type is one of N-type or P-type and the second doping type is the other of N-type or P-type.
CN202320007254.0U 2022-09-14 2023-01-03 Trench MOSFET transistor Active CN219435880U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2022111145935 2022-09-14
CN202211114593.5A CN115207100A (en) 2022-09-14 2022-09-14 Trench MOSFET and method of manufacturing the same

Publications (1)

Publication Number Publication Date
CN219435880U true CN219435880U (en) 2023-07-28

Family

ID=83572885

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202211114593.5A Pending CN115207100A (en) 2022-09-14 2022-09-14 Trench MOSFET and method of manufacturing the same
CN202320007254.0U Active CN219435880U (en) 2022-09-14 2023-01-03 Trench MOSFET transistor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202211114593.5A Pending CN115207100A (en) 2022-09-14 2022-09-14 Trench MOSFET and method of manufacturing the same

Country Status (1)

Country Link
CN (2) CN115207100A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005041321B4 (en) * 2005-08-31 2012-03-01 Infineon Technologies Ag Grave structure semiconductor devices
US8354711B2 (en) * 2010-01-11 2013-01-15 Maxpower Semiconductor, Inc. Power MOSFET and its edge termination
US9761676B2 (en) * 2014-03-26 2017-09-12 Infineon Technologies Americas Corp. Power semiconductor device with embedded field electrodes
CN113707713B (en) * 2021-08-31 2023-06-30 西安电子科技大学 Multi-stage petal-shaped body region metal oxide semiconductor power device and manufacturing method thereof

Also Published As

Publication number Publication date
CN115207100A (en) 2022-10-18

Similar Documents

Publication Publication Date Title
JP2585331B2 (en) High breakdown voltage planar element
US6404032B1 (en) Semiconductor device
US8362551B2 (en) Semiconductor device
CN107464837B (en) Super junction power device
CN113611750B (en) SOI transverse shimming high-voltage power semiconductor device, manufacturing method and application
CN111989778B (en) Small-pitch superjunction MOSFET structure and method
CN111799322B (en) Double-groove type SiC MOSFET structure for high-frequency application and manufacturing method
CN112382658B (en) Low gate charge device with stepped discrete shield trenches and method of making the same
US8330233B2 (en) Semiconductor device
CN114823872B (en) Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof
KR20170122335A (en) SiC Super junction MOSFET using pillar oxide and manufacturing method thereof
CN117352548A (en) LDMOS device and preparation method thereof
CN219435880U (en) Trench MOSFET transistor
CN116364778A (en) HJD integrated SiC VDMOSFET device and preparation method thereof
US20240038837A1 (en) Super junction mosfet device
CN115911097A (en) Composite terminal structure for SiC power device and manufacturing method thereof
CN107046062B (en) Longitudinal double-diffusion metal oxide semiconductor field effect transistor with semi-insulating polycrystalline silicon layer
CN114530504A (en) High-threshold SiC MOSFET device and manufacturing method thereof
KR20000048749A (en) Power mos component
CN210156383U (en) Super junction power semiconductor device
CN112071913A (en) Silicon carbide planar gate MOSFET cell structure and manufacturing method
CN218730960U (en) Trench type MOSFET transistor
CN213093207U (en) Silicon carbide planar gate MOSFET cellular structure
EP4297100A1 (en) Method for producing a semiconductor device and semiconductor device
CN116314325A (en) Trench MOSFET transistor and manufacturing method thereof

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20240909

Address after: 200032 area a, 2nd floor, 420 Fenglin Road, Xuhui District, Shanghai

Patentee after: Shanghai Ruineng Weilan Semiconductor Technology Co.,Ltd.

Country or region after: China

Address before: 330052 North first floor, building 16, No. 346, xiaolanzhong Avenue, Xiaolan Economic Development Zone, Nanchang County, Nanchang City, Jiangxi Province

Patentee before: Ruineng Semiconductor Technology Co.,Ltd.

Country or region before: China