JPH01259555A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01259555A JPH01259555A JP63087013A JP8701388A JPH01259555A JP H01259555 A JPH01259555 A JP H01259555A JP 63087013 A JP63087013 A JP 63087013A JP 8701388 A JP8701388 A JP 8701388A JP H01259555 A JPH01259555 A JP H01259555A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- type
- pressure cvd
- cvd method
- low pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010409 thin film Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 10
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000002019 doping agent Substances 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000010575 Pueraria lobata Nutrition 0.000 description 1
- 241000219781 Pueraria montana var. lobata Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はフラット・デイスプレィ、ＳＯＩ素子（Ｓｅｎ
ｉｃｏｎｄｕｃｔａｒ ｏｎ １ｎｓｕｌａｔｏｒ）等
に用いる半導体装置の構造及びその製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to flat displays, SOI devices (Sen
The present invention relates to the structure of a semiconductor device used for a semiconductor device (iconductor on one insulator) and a method for manufacturing the same.
従来、例えばＣｏｎｆｅｒｅｎｃｅ Ｒｅｃｏｒｄ ｏ
ｆ ｔｈｅ １９８５Ｉｎｔｅｒｎａｔｉｏｎａｌ
Ｄｉｓｐｌａｙ Ｒｅ５ｅａｒｃｈ Ｃｏｎｆｅｒｅ
ｎｃｅ、ｐ。Conventionally, for example, Conference Record o
f the 1985 International
DisplayRe5earchConfere
nce, p.
９−１３（１９８５）のように、非晶質基板上に多結晶
半導体でＣＭＯ３ｌｉｉ造（相補型ＭＯ３構造）を形成
する場合、ｎ型領域とｐ型頭域を異なる部分に形成する
方法として、イオン注入法が用いられるのが一般であっ
た。9-13 (1985), when forming a CMO3lii structure (complementary MO3 structure) with a polycrystalline semiconductor on an amorphous substrate, the method of forming the n-type region and the p-type head region in different parts is as follows. Ion implantation was generally used.
しかし前述の従来技術は、イオン注入法を用いてドーパ
ントの導入を行うため、高価なイオン注入装置の使用が
不可欠であり、またその処理能力も小さなものであった
。また、イオン注入後にドーパントを活性化するために
高温に保持する必要があるため、非晶質基板として高価
な石英ガラスの使用が不可欠であるという欠点を有して
いた。However, in the above-mentioned conventional technology, the dopant is introduced using an ion implantation method, so it is essential to use an expensive ion implantation device, and its processing capacity is also small. Furthermore, since it is necessary to maintain the temperature at a high temperature in order to activate the dopant after ion implantation, it has the disadvantage that expensive quartz glass must be used as the amorphous substrate.
そこで本発明は従来技術の欠点を解決するもので、その
目的とするところは、安価なガラス基板を非晶質基板に
用いて、量産性に富む製造方法で形成可能なＣＭＯ３構
造を提供するところにある。Therefore, the present invention solves the drawbacks of the prior art, and its purpose is to provide a CMO3 structure that can be formed by a manufacturing method that is highly suitable for mass production, using an inexpensive glass substrate as an amorphous substrate. It is in.
本発明は、量産性に富む減圧ＣＶＤ法を用いてドーパン
トの導入を行い、高価で生産性の低いイオン注入装置を
使用せずにＣ−ＭＯ３ｍ造の形成を行う、また、イオン
注入後にドーパントを活性化するために高温に保持する
必要がないため、非晶質基板として安価なカラス基板の
使用が可能になる。The present invention introduces dopants using the low-pressure CVD method, which is highly suitable for mass production, and forms a C-MO3m structure without using expensive and low-productivity ion implantation equipment. Since there is no need to hold the material at a high temperature for activation, an inexpensive glass substrate can be used as the amorphous substrate.
第１図は本発明による構造を用いて作製したインバータ
（反転増幅器）を上方より眺めた図である。FIG. 1 is a top view of an inverter (inverting amplifier) manufactured using a structure according to the present invention.
ガラス基板１上にｎ型Ｓｉ薄膜２及びｎ型Ｓｉ薄膜３が
島状に形成されており、そのあいだを橋渡しするように
形状でノンドープＳｉ薄膜４が形成されている。それら
の上にはゲート酸化膜として機能しうるＳｉＯ２薄膜５
が形成されており、電気的にコンタクトをとるため、該
薄膜には一部窓領域６が設けられている。それらを金属
配線材料で結線して入力電極７、出力電極８、電源供給
電ｆ！９．１０が設けられテイテ、Ｃ−ＭＯ３構造を構
成している。このインバータは、高周波帯域にわたり安
定な動作が可能な、非常に良好な特性を得ることができ
た。An n-type Si thin film 2 and an n-type Si thin film 3 are formed in the form of islands on a glass substrate 1, and a non-doped Si thin film 4 is formed in the shape of bridging between them. On top of them is a SiO2 thin film 5 that can function as a gate oxide film.
A window region 6 is provided in a portion of the thin film in order to make electrical contact. These are connected using metal wiring materials to form an input electrode 7, an output electrode 8, and a power supply f! 9.10 is provided and constitutes the C-MO3 structure. This inverter has very good characteristics that enable stable operation over a high frequency band.
第２図は、第１図の本発明による構造を用いて作製した
インバータ（反転増幅器）のＡ−８の線に沿った断面構
造を示す図である。FIG. 2 is a diagram showing a cross-sectional structure taken along line A-8 of an inverter (inverting amplifier) manufactured using the structure according to the present invention shown in FIG.
第３図は、第１図に示した半導体装置の製造工程の一例
を示す断面図である。FIG. 3 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device shown in FIG. 1.
第３図（ａ）の工程
カラス基板１上に減圧ＣＶＤ法を用いてｎ型Ｓｉ薄膜を
付着させ、フォトリソグラフィー法を用いて該ｎ型Ｓｉ
薄膜を島状に加工し、ｎ型Ｓｉ薄膜２を形成する。In the step of FIG. 3(a), an n-type Si thin film is deposited on the glass substrate 1 using the low pressure CVD method, and the n-type Si thin film is deposited on the glass substrate 1 using the photolithography method.
The thin film is processed into an island shape to form an n-type Si thin film 2.
第３図（ｂ）の工程
減圧ＣＶＤ法を用いてｐ型Ｓｔ薄膜を付着させ、フォト
リソグラフィー法を用いて該ρ型Ｓｔ薄膜を島状に加工
し、ｐ型Ｓｔ薄ＷＡ３を形成する。Step of FIG. 3(b) A p-type St thin film is deposited using a low pressure CVD method, and the ρ-type St thin film is processed into an island shape using a photolithography method to form a p-type St thin WA3.
第３図（ｃ）の工程
減圧ＣＶＤ法を用いてノンドープＳｉ薄膜を付着させ、
フォトリソグラフィー法を用いて該ノンドープＳｉ薄膜
を島状に加工し、ノンドープＳｉ薄膜４を形成する。A non-doped Si thin film is deposited using a low pressure CVD method in the process shown in FIG. 3(c),
The non-doped Si thin film is processed into an island shape using a photolithography method to form a non-doped Si thin film 4.
第３図（ｄ）の工程
常圧ＣＶＤ法を用いてＳｉＯ２薄膜を付着させ、フォト
リソグラフィー法を用いて該５ｉｎ２薄膜に一部窓領域
６を設け、ゲート酸化膜として機能しうる５ＬＯ２薄膜
５を形成する。Step of FIG. 3(d) A SiO2 thin film is deposited using the atmospheric pressure CVD method, and a partial window region 6 is formed in the 5in2 thin film using the photolithography method to form a 5LO2 thin film 5 that can function as a gate oxide film. Form.
第３図（ｅ）の工程
スパッタリング法を用いて金属薄膜を付着させ、フォト
リソグラフィー法を用いて該金属薄膜を島状に加工し、
入力電極７、゛出力電極８、電源供給電極り、１０を形
成する。A metal thin film is deposited using the process sputtering method in FIG. 3(e), and the metal thin film is processed into an island shape using a photolithography method,
An input electrode 7, an output electrode 8, and a power supply electrode 10 are formed.
以上の工程により、第１図に示した構造の半導体装置を
得ることができた。Through the above steps, a semiconductor device having the structure shown in FIG. 1 could be obtained.
尚、第３図の製造法ではｎ型Ｓｉ薄膜２を形成してから
ｎ型Ｓｉ薄膜３を形成したが、この逆の順でももちろん
横わない。Incidentally, in the manufacturing method shown in FIG. 3, the n-type Si thin film 2 is formed and then the n-type Si thin film 3 is formed, but of course the reverse order does not apply.
また、金属配線層の代わりに、ｎ型もしくはｐ型Ｓｔ薄
膜を用いてら同様な効果を示すことはあきらかである。Furthermore, it is clear that similar effects can be obtained by using an n-type or p-type St thin film instead of the metal wiring layer.
本発明は以上述べたように、量産性に富む減圧ＣＶＤ法
を用いてドーパントの導入を行っているため、高価で生
産性の低いイオン注入装置を使用せずにＣ−ＭＯ３ｍ造
の形成が可能であると言う特徴を有する。また、イオン
注入後にドーパントを活性化するために高温に保持する
必要がないため、非晶質基板として安価なガラス基板の
使用か可能になった。As described above, the present invention introduces dopants using the low-pressure CVD method, which is highly suitable for mass production, so it is possible to form C-MO3m structures without using expensive and low-productivity ion implantation equipment. It has the characteristics of Furthermore, since there is no need to hold the dopant at a high temperature to activate the dopant after ion implantation, it has become possible to use an inexpensive glass substrate as the amorphous substrate.
本発明が半導体技術の発展に寄与するところ大であると
確信する。We are confident that the present invention will greatly contribute to the development of semiconductor technology.
第１図は本発明による構造を用いて作製したインバータ
（反転増幅器）を上方より眺めた図である。
第２図は、第１図の本発明による構造を用いて作製した
インバータ（反転増幅器）のＡ−Ｂの線に沿った断面構
造を示す図である。
第３図（ａ）〜（ｅ）は、第１図に示した半導体装置の
製造工程の一例を示す断面図である。
第３図（ａ）の工程
ガラス基板１上に減圧ＣＶＤ法を用いてｎ型Ｓｉ薄膜を
付着させ、フォトリソグラフィー法を用いて該ｎ型Ｓｉ
薄膜を島状に加工し、ｎ型Ｓｉ薄膜２を形成する工程。
第３図（ｂ）の工程
減圧ＣＶＤ法を用いてｎ型Ｓｉ薄膜を付着させ、フォト
リソグラフィー法を用いて該ｐ型ＳｉＲ膜を島状に加工
し、ｎ型Ｓｉ薄膜３を形成する工程。
第３図（ｃ）の工程
減圧ＣＶＤ法を用いてノンドープＳｉ薄膜を付着させ、
フォトリソグラフィー法を用いて該ノンドープＳｉ薄膜
を島状に加工し、ノンドープＳｉ薄膜４を形成する工程
。
第３図（ｄ）の工程
常圧Ｃ’Ｖ Ｄ法を用いて５ｉ０２薄膜を付着させ、フ
ォトリソグラフィー法を用いて該Ｓｉｎ、薄膜に一部窓
領域６を設け、ゲート酸化膜として橘能しうる５ｉ０２
薄膜５を形成する工程。
第３図（ｅ）の工程
スパッタリング法を用いて金属薄膜を付着させ、フォト
リソグラフィー法を用いて該金属薄ｊ模を島状に加工し
、入力電極７、出力電極８、電源供給電極９．１０を形
成する工程工程。
１・・・・・・ガラス基板
２・・・・・・ｎ型Ｓｉ薄膜
３・・・・・・ｎ型Ｓｉ薄膜
４・・・・・・ノンドープＳｉ薄膜
５・・・・・・５ｉ０２薄膜
６・・・・・・窓領域
７・・・・・・入力電極
８・・・・・・出力電極
９．１０・・・電源供給電極
以 上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉（他１名）葛 １１ｇ
冨 ２ 還FIG. 1 is a top view of an inverter (inverting amplifier) manufactured using a structure according to the present invention. FIG. 2 is a diagram showing a cross-sectional structure along the line AB of an inverter (inverting amplifier) manufactured using the structure according to the present invention shown in FIG. 3(a) to 3(e) are cross-sectional views showing an example of the manufacturing process of the semiconductor device shown in FIG. 1. Step of FIG. 3(a) An n-type Si thin film is deposited on the glass substrate 1 using the low pressure CVD method, and the n-type Si thin film is deposited on the glass substrate 1 using the photolithography method.
A process of forming an n-type Si thin film 2 by processing the thin film into an island shape. Step of FIG. 3(b) A step of depositing an n-type Si thin film using a low pressure CVD method and processing the p-type SiR film into an island shape using a photolithography method to form an n-type Si thin film 3. A non-doped Si thin film is deposited using a low pressure CVD method in the process shown in FIG. 3(c),
A step of processing the non-doped Si thin film into an island shape using a photolithography method to form a non-doped Si thin film 4. In the step of FIG. 3(d), a 5i02 thin film is deposited using the normal pressure C'VD method, and a window region 6 is formed in the thin film using photolithography, and a window region 6 is formed as a gate oxide film. Uru5i02
Step of forming thin film 5. Process of FIG. 3(e) A metal thin film is deposited using a sputtering method, and the metal thin film is processed into an island shape using a photolithography method to form an input electrode 7, an output electrode 8, a power supply electrode 9. Process steps for forming 10. 1...Glass substrate 2...N-type Si thin film 3...N-type Si thin film 4...Non-doped Si thin film 5...5i02 thin film 6...Window area 7...Input electrode 8...Output electrode 9.10...Power supply electrode and above Applicant Seiko Epson Corporation Agent Patent attorney Kamiyanagi Masa Homare (1 other person) Kudzu 11g Tomi 2 return
Claims (2)
ｐ型半導体の多結晶薄膜が重なって設置された構造を含
むことを特徴とする半導体装置。(1) A semiconductor device characterized by including a structure in which a polycrystalline thin film of an n-type semiconductor and a polycrystalline thin film of a p-type semiconductor are placed overlappingly on an insulating substrate.
Ｄ法を用いることを特徴とする半導体装置の製造方法。(2) Low pressure CV as a method for manufacturing polycrystalline thin films of semiconductors
A method for manufacturing a semiconductor device, characterized by using the D method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63087013A JPH01259555A (en) | 1988-04-08 | 1988-04-08 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63087013A JPH01259555A (en) | 1988-04-08 | 1988-04-08 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01259555A true JPH01259555A (en) | 1989-10-17 |
Family
ID=13903082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63087013A Pending JPH01259555A (en) | 1988-04-08 | 1988-04-08 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01259555A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232580A (en) * | 1996-02-21 | 1997-09-05 | Samsung Electron Co Ltd | Transistor and manufacture thereof |
-
1988
- 1988-04-08 JP JP63087013A patent/JPH01259555A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232580A (en) * | 1996-02-21 | 1997-09-05 | Samsung Electron Co Ltd | Transistor and manufacture thereof |
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