JPH01270354A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a MOS structure, which can be formed by a manufacturing method having a high degree of mass productivity using a low-cost glass substrate as an amorphous substrate and has a multiple structure, by a method wherein a semiconductor device is provided with at least one group of structures covering a structure wherein an insulating layer is pinched by semiconductor films of the same conductivity type as that of the insulating layer between them with a conductive thin film. CONSTITUTION:An N-type Si thin film first layer 2, an SiO2 thin film layer 3 for insulation and an N-type Si thin film second layer 4 are formed on a glass substrate 1 superposing on one another. Moreover, a non-doped Si thin film 5, an SiO2 thin film 6 capable of functioning as a gate oxide film and a gate electrode 7 are formed in a configuration covering the layers 2, 3 and 4. The layers 2 and 4 are formed by a method wherein an N-type Si thin film is adhered using a reduced CVD method and the formed thin film is processed insularly using a photolithography method. The electrode 7 is formed by a method wherein a metal thin film is adhered using a sputtering method and the metal thin film is processed insularly using a photolithography method.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to flat displays, SOI devices (SEM
The present invention relates to the structure of a semiconductor device used in a semiconductor device (1 conductor on 1 insulator), etc., and a method for manufacturing the same.

[Prior art] Conventionally, for example, a conference record
f the 1985 International D
isplay Research Conference
e.

When forming an MO5 structure using a polycrystalline semiconductor on an amorphous substrate, as in p. 9-13 (1985), ion implantation is used as a method of forming a conductive thin film, and the element is formed in a planar manner. It was common.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology uses an ion implantation method to introduce dopants, so it is essential to use an expensive ion implantation device, and its processing capacity is also small. Ta. Furthermore, since it is necessary to hold the dopant at high temperature after ion implantation to activate it, it is essential to use expensive quartz glass as the amorphous substrate, and the activation process can damage the already formed structure. For this reason, forming the elements in a stacked manner has the disadvantage of being redundant. Therefore, it has not been possible to realize effects such as speeding up the operation and reducing the mounting area by arranging the elements and elements one on top of the other.

SUMMARY OF THE INVENTION The present invention aims to solve the drawbacks of the prior art, and its purpose is to create a multi-layer structure that can be formed using an inexpensive glass substrate as an amorphous substrate and a manufacturing method that is mass-produced and highly flexible. It provides an O'S structure.

[Means for Solving the Problems] The present invention introduces a dopant using a low-pressure CVD method with high M productivity, and forms an MO3 structure without using an expensive and low-productivity ion implantation device. . Furthermore, since there is no need to maintain the temperature at a high temperature to activate the dopant after ion implantation, an inexpensive glass substrate can be used as the amorphous substrate.

Further, since the semiconductor devices are arranged one on top of the other, the area occupied by the semiconductor devices is significantly reduced, and high-density packaging of the semiconductor devices becomes possible.

[Example] Figure 1 shows n-MO3 produced using the structure according to the present invention.
FIG. 3 is a view of the mold element viewed from above.

On a glass substrate 1, an n-type Si thin film first layer 2 and an insulating SiO
Two thin film layers 3 and an n-type Si thin film second layer 4 are formed in an overlapping manner. Furthermore, in a shape that covers them, a non-doped Si thin film 5, a SiO2 thin film 6 that can function as a gate oxide film,
A gate electrode 7 is formed. Further, the SiO2 thin film 6, which can function as a gate oxide film, is provided with a window region 8 for making electrical contact. Further, power supply electrodes 9 and 10 are provided on the n-type Si thin film first layer 2 and the n-type Si thin film second layer 4, forming an n-MOS structure. This device has very good characteristics that enable stable operation over a high frequency band.

FIG. 2 is a diagram showing a cross-sectional structure along the line AB of an n-MO3 structure manufactured using the structure according to the present invention shown in FIG.

FIG. 3 is a cross-sectional view showing an example of the manufacturing process of the semiconductor device shown in FIG. 1.

Step of FIG. 3(a) An n-type Si thin film is deposited on the glass substrate 1 using the low pressure CV and D method, and the formed thin film is processed into an island shape using the photolithography method. 1 layer 2 is formed.

The process in Figure 3(b) A thin SiO2 film is deposited using atmospheric pressure CVD.

This Si0g thin film functions as an insulating SiO2 thin film layer 3.

Step of FIG. 3(C) An n-type Si thin film is deposited using a low pressure CVD method, and the n-type Si thin film is processed into an island shape using a photolithography method to form a second layer 4 of an n-type Si thin film. do.

A non-doped Si thin film is deposited using a low pressure CVD method in the process shown in FIG. 3(d),
The non-doped Si thin film is processed into an island shape using a photolithography method to form a non-doped Si thin film layer 5.

The process in Figure 3(e) A thin SiO2 film is deposited using atmospheric pressure CVD.

This SiO2 thin film is the SiO2 thin film 6, which functions as a gate oxide film. Then, a window region 8 is provided in this SiO2 thin film 6 using a photolithography method.

Step of FIG. 3(f) A metal thin film is deposited using a sputtering method, and the metal thin film is processed into an island shape using a photolithography method.
A gate electrode 7 and power supply electrodes 9 and 10 are formed.

Through the above steps, a semiconductor device having the structure shown in FIG. 1 could be obtained.

In the manufacturing method shown in FIG. 3, an n-type Si thin film is used as the conductive semiconductor thin film, but a p-type Si thin film may of course be used.

Furthermore, it is clear that similar effects can be obtained by using an n-type or p-type Si thin film instead of the metal wiring layer.

[Effects of the Invention] As described above, the present invention has the effect that since the semiconductor devices are arranged one on top of the other, the area occupied by the semiconductor devices is significantly reduced, and it is possible to package the semiconductor devices at a higher density than before. In addition, because the dopant is introduced using the low-pressure CVD method, which is highly suitable for mass production, the C-MO3 structure can be formed without using expensive and low-productivity ion implantation equipment. . Furthermore, since there is no need to hold the dopant at a high temperature to activate the dopant after ion implantation, it has become possible to use an inexpensive glass substrate as the amorphous substrate.

We are confident that the present invention will greatly contribute to the development of semiconductor technology.

[Brief explanation of the drawing]

Figure 1 shows n-MO3 produced using the structure according to the present invention.
FIG. 3 is a view of the mold element viewed from above. 1...Glass substrate 2...N-type Si thin film first layer 3...Insulating SiO2 thin film layer 4...N-type Si thin film second layer 5 ......Non-doped Sil film 6...Si○2 that functions as a gate oxide film
Thin film 7...Gate electrode 8...Window area for making electrical contact 9.10...Power supply electrode Figure 2 shows the present invention in Figure 1. Using the structure by. It is a figure which shows the cross-sectional structure along the line AB of the produced n-MO3 structure. FIGS. 3(a) to 3(f) are cross-sectional views showing an example of the manufacturing process of the semiconductor device shown in FIGS. Step of FIG. 3(a) A step of forming the n-type Si thin film first layer 2. Step of FIG. 3(b) Deposition of first layer 3 of 5iOa thin film for insulation. The step of FIG. 3(c) is a step of forming the n-type Si thin film second layer 4. Step of FIG. 3(d) A step of forming a non-doped Si thin film layer 5. Step of FIG. 3(e): Step of forming a 5iOz thin film 6 for gate oxide film, and
Step of providing window area 8. Step of FIG. 3(f) Step of forming gate electrode 7 and power supply electrode 9.10. Applicant: Seiko Epson Corporation

Claims (2)

[Claims] (1) A semiconductor device characterized by having at least one structure in which an insulating layer is sandwiched between semiconductor thin films of the same conductivity type and the structure is covered with a conductive thin film. (2) The method for manufacturing a semiconductor device according to item 1, wherein a low pressure CVD method is used as the method for manufacturing the semiconductor thin film.