JPH07115203A - Thin film, manufacture of the thin film and thin-film transistor using the thin film - Google Patents

Abstract

PURPOSE:To provide a thin film transistor without the wire disconnection or the separation of a gate electrode by using a conductive thin film, whose internal stress is decreased, as the gate electrode. CONSTITUTION:An active semiconductor layer 2 is formed on a light transmitting glass substrate 1. A gate insulating layer 5 is formed thereon. A gate electrode 6 is further formed so that the absolute value of the internal stress per unit width is 2X10<5>dyn/cm or less and the thickness is 100nm or more and 400nm or less. With the gate electrode 6 as a mask, impurities are introduced into the region of a part of the semiconductor thin film, and a source region 3 and a drain region 4 are formed. After a layer insulating layer 8 is formed thereon, a contact hole, a source electrode 9 and a drain electrode are formed, and the thin film transistor is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor applied to a liquid crystal display device, an image sensor or the like.

[0002]

BACKGROUND OF THE INVENTION thin film transistor (T hin F ilm
A transistor (hereinafter abbreviated as a TFT) is used, for example, as a switching element of a pixel of a liquid crystal display device.
No. 127,166 publication is mentioned.

The TF shown in FIG. 2 as an example is shown below.
A method of manufacturing T will be described. FIG. 2A is a plan view of a conventional thin film transistor, and FIG.
The X sectional view and the same figure (c) are YY sectional views of the same figure (a).
First, the island-shaped active semiconductor layer 2 having a film thickness of about 100 nm is formed on the transparent glass substrate 1. A gate insulating layer 5 is formed thereon. Next, the gate electrode 6 is formed to a film thickness of 200 nm.
After being formed of chromium to a certain extent, impurities are introduced by ion implantation or the like using the gate electrode 6 as a mask to form the source region 3 and the drain region 4. Then, the interlayer insulating layer 7, the contact hole, the source electrode 8 and the drain electrode 9 are formed to complete the TFT.

[0004]

In the TFT as described above, especially in a portion where the gate electrode crosses the step,
Problems such as disconnection of the gate electrode (for example, the disconnection portion shown in FIG. 2) may occur. This is caused by the internal stress of the gate electrode, and is easily affected by the internal stress in a portion where the film thickness of the gate electrode is thin, such as the above-mentioned step portion, and a film due to disconnection due to tensile stress or compressive stress. Lifting and peeling occurred.

It is an object of the present invention to provide a TFT which is free from breakage or peeling of the gate electrode by reducing the internal stress of the gate electrode.

[0006]

[Means for Solving the Problems] Internal stress per unit width as a gate electrode (internal stress per unit cross-sectional area x film thickness)
A conductive thin film having an absolute value of 2 × 10 5 dyn / cm or less is used.

[0007]

As described above, by reducing the absolute value of the internal stress per unit width of the gate electrode,
The force acting between the gate electrode and its base can be weakened to prevent disconnection or peeling of the gate electrode.

[0008]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 shows a coplanar TFT according to the present invention.
FIG. This embodiment will be described below with reference to this drawing. First, a 100-nm-thick polycrystalline silicon film is formed as the active semiconductor layer 2 on the transparent glass substrate 1 by, for example, the LP-CVD method, and is processed into an island shape by using photolithography and etching. Silicon dioxide is formed thereon as the gate insulating layer 5 by atmospheric pressure CVD, for example. Further, a tantalum film is formed as the gate electrode 6 and processed by using photolithography and etching. This tantalum is formed into a film with a film thickness of 200 nm by, for example, a high frequency sputtering method under a pressure of argon of 20 mTorr.

As can be seen from the relationship between the tantalum film forming conditions and the internal stress shown in FIG. 3, the internal stress per unit width of the gate electrode (internal stress per unit cross-sectional area × film thickness) The absolute value can be set to 2 × 10 5 power dyn / cm or less. By the way, it has been confirmed that disconnection and peeling due to internal stress of the gate electrode can be prevented by setting the absolute value of the internal stress per unit width of the gate electrode to about 2 × 10 5 dyn / cm or less, ( Figure 4) also shows the relationship between chromium film formation conditions and internal stress.

Next, using the gate electrode 6 as a mask, phosphorus is introduced as an impurity by, for example, an ion implantation method to form the source region 3 and the drain region 4. After that, silicon dioxide is formed as the interlayer insulating layer 7 by, for example, an atmospheric pressure CVD method, and then a contact hole is formed by photolithography and etching. Further, the source electrode 9 and the drain electrode 10 are deposited and processed in the order of, for example, titanium and aluminum to complete the TFT.

Coplanar TF produced by this example
T has the following effects. By forming the gate electrode under the above conditions, the internal stress per unit width is 2 ×.
By making it 10 5 dyn / cm or less, peeling of the gate electrode can be prevented.

In this embodiment, tantalum was used as the gate electrode 6 under the above film forming conditions. However, the absolute value of the internal stress per unit width is 2 × 10 5 dyn / cm.
Any conductive thin film may be used, for example, a film thickness of 2
One in which chromium having a thickness of 00 nm was formed by a direct-current sputtering method at an argon pressure of 0.5 mTorr during film formation, or Mo-Ta or N whose internal stress was adjusted by multielement formation.
For example, i-Cr or a gate electrode having a multi-layer structure of two or more layers to adjust the internal stress of the entire gate electrode may be used.

In this embodiment, silicon dioxide produced by the atmospheric pressure CVD method is used as the gate insulating layer 5 and the interlayer insulating layer 8. However, this is not limited to silicon nitride produced by the plasma CVD method as an insulating layer. Anything is fine.

In this embodiment, polycrystalline silicon is used as the active semiconductor layer 2, but amorphous silicon,
Any material that works as an active semiconductor such as single crystal silicon or a compound semiconductor may be used.

Although phosphorus is used as an impurity in this embodiment, any element that acts as a donor such as arsenic may be used in the case of manufacturing an n-channel TFT, and phosphorus may be used in the case of manufacturing a p-channel TFT. Anything can be used as long as it works as an acceptor.

In this embodiment, the ion implantation method is used as a method for adding impurities. However, the high-frequency discharge plasma containing at least the impurity ions to be added is generated and the impurity ions are accelerated and added without mass separation. Any method can be used as long as impurities can be added.

[0018]

As described above, according to the present invention, the absolute value of the internal stress per unit width of the gate electrode is 2 × 10.
By setting the value to the fifth power dyn / cm or less, it is possible to provide a TFT that does not cause disconnection or peeling of the gate electrode.

[Brief description of drawings]

FIG. 1 is a sectional view of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is an explanatory view of a conventional thin film transistor.

FIG. 3 is a graph showing the relationship between the internal stress of a tantalum thin film prepared by a high frequency sputtering method and the pressure of argon gas during film formation.

FIG. 4 is a graph showing the relationship between the internal stress of a chromium thin film prepared by the DC sputtering method and the pressure of argon gas during film formation.

[Explanation of symbols]

 1 Translucent glass substrate 2 Active semiconductor layer 3 Source region 4 Drain region 5 Gate insulating layer 6 Gate electrode 7 Interlayer insulating layer 8 Source electrode 9 Drain electrode

Front page continued (72) Inventor Tetsuya Kawamura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Yutaka Miyata 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (10)

[Claims] 1. An absolute value of internal stress per unit width is 2 ×, which is composed of one or more kinds of elements and is composed of one or more layers.
10 5 dyn / cm or less and a thickness of 100
A thin film having a thickness of not less than 400 nm and not more than 400 nm. 2. The thin film on the substrate is composed of one or more kinds of elements and is composed of one or more layers, and the absolute value of the internal stress per unit width is 2 × 10 5 dyn / cm or less,
A method for manufacturing a thin film, wherein the thickness is 100 nm or more and 400 nm or less, and the substrate surface on which the thin film is formed has a step difference of 30 nm or more and 150 nm or less. 3. The thin film according to claim 2, wherein the thin film is a conductive thin film containing tantalum as a main component, and is formed by a sputtering method at a pressure of argon of 8 mTorr or more during film formation. Production method. 4. The thin film according to claim 2, wherein the thin film is a conductive thin film whose main component is chromium, and is formed by a sputtering method at a pressure of argon of 2 mTorr or less during film formation. Production method. 5. The electrode is composed of one or more kinds of elements and is composed of one or more layers, and the absolute value of the internal stress per unit width is 2 × 10 5 dyn / cm or less and the thickness is Is formed by a conductive thin film having a thickness of 100 nm or more and 400 nm or less. 6. The thin film transistor according to claim 5, wherein the electrode is a gate electrode and the structure of the thin film transistor is a top gate type. 7. A surface on which an electrode is formed is 30 nm or more and 150 or more.
7. The thin film transistor according to claim 5, which has a step difference of not more than nm. 8. The thin film transistor according to claim 5, 6 or 7, wherein the step of manufacturing the thin film transistor after forming the electrodes includes a heat step of 300 ° C. or higher. 9. The electrode according to claim 5, wherein the electrode is a conductive thin film whose main component is tantalum, and is formed by a sputtering method so that the pressure of argon during film formation is 8 mTorr or more. 2. The thin film transistor according to Item 1. 10. The thin film is a conductive thin film whose main component is chromium, and is formed by a sputtering method at a pressure of argon of 2 mTorr or less at the time of film formation. 2. The thin film transistor according to Item 1.