JP2842892B2 - Thin film transistor, method of manufacturing the same, matrix circuit substrate using the same, and image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a thin film transistor used in an active matrix drive type image display device, and more particularly to a thin film transistor in which a gate insulating film has a film quality changed in a depth direction of the film, a manufacturing method thereof, and an active matrix circuit using the same The present invention relates to a substrate and an image display device.

[Prior art]

Many thin film transistors formed in a matrix on an insulating substrate such as glass have been put to practical use as switching elements of an active matrix circuit substrate used for an image display device. FIG. 5 (a) shows a cross-sectional structural view of a main part of an amorphous silicon thin film transistor most frequently used at present.
In the figure, 1 is an insulating film plate such as a glass plate, 2 is a gate electrode made of a metal film such as a chromium film, 3 is a gate insulating film made of a silicon nitride film or the like, and 4 is an amorphous silicon film. Reference numerals 51 and 61 denote an n-type semiconductor film made of an amorphous silicon film doped with phosphorus or the like, and 52 and 62 denote a drain electrode or a source electrode made of a metal film such as an aluminum film. By arranging a plurality of thin film transistors in a two-dimensional matrix, connecting the gate electrodes to form a first bus line, and connecting the drain electrodes to form a second bus line, an active matrix circuit substrate Is completed. Japanese Patent Application Laid-Open No. 63-181472 can be mentioned as one related to this type of thin film transistor.

[Problems to be solved by the invention]

In the above prior art, no consideration was given to the workability of the gate insulating film, for example, when providing an opening for taking out an electrode in the gate insulating film, performing inclined etching on the inner wall of the opening. . Therefore, as shown in FIG. 5 (b), when connecting, for example, the source electrode 6 and the display pixel electrode 7 of the thin film transistor via the etching step (indicated by 3 ') of the gate insulating film, the step 3 ′
5C, or when a drain line (signal wiring) 9 is present on the etching step 3 'of the gate insulating film 3 as shown in FIG. ′, The wiring resistance is increased, and the wire is easily derailed. Therefore, an object of the present invention is to solve the above-mentioned conventional problems. The first object is to provide a thin film transistor having an electrode connection hole which is obliquely etched in a gate insulating film, and the second object is to provide a thin film transistor. A third object is to provide an active matrix circuit board using the same, and a fourth object is to provide an image display device using the improved active matrix circuit board. It is in.

[Means for Solving the Problems]

The first object of the present invention is to form an electrode group having a gate electrode and other wirings and electrodes provided separately on an insulating substrate, and to form the electrode group so as to cover the electrode group. A gate insulating film, a semiconductor film pattern disposed so as to be located at least on the gate insulating film on the gate electrode, and disposed at least on both ends of the semiconductor film pattern with an overlapping portion with the gate electrode. A drain electrode and a source electrode, and a wiring conductor or the drain electrode and the source electrically connected to at least one of the drain electrode and the source electrode and the other wiring electrode through an opening provided in the gate insulating film. A wiring conductor electrically connected to at least one of the electrodes and present on an etching step provided in the gate insulating film. In becomes thin film transistor,
The gate insulating film is formed of a gate insulating film having an etching rate substantially gradually reduced as the distance from the surface toward the substrate in the depth direction is increased, and a step is formed on a wall surface of an opening provided in the gate insulating film. Alternatively, this is achieved by a thin film transistor in which an inclined portion is provided to make the inclination of the wall surface of the opening portion substantially gentle. Preferably, the gate insulating film is formed of a silicon-based insulating thin film, and hydrogen or oxygen is contained in the gate insulating film. In the case of hydrogen, the content on the surface side of the insulating film is large in the depth direction. This is achieved by a thin film transistor having a concentration gradient that gradually decreases, and in the case of oxygen, the content on the surface side of the insulating film decreases and gradually increases in the depth direction. As described above, a single insulating film may be provided with a property that the etching rate gradually decreases in the depth direction from the surface thereof, or may be configured as a multilayer film as described below. In other words, the gate insulating film has a multilayer structure having different etching rates, and the outermost insulating thin film in contact with the semiconductor pattern is a thin film having a high etching rate, and gradually decreases as the distance from the substrate in the internal depth direction increases. A thin film transistor formed by laminating thin films having a small etching rate may be used, and this is preferable in practical use. In the case of using this multilayer film, the number of film layers constituting the gate insulating film may be any number in principle as long as it can sufficiently act as the gate of the transistor. Considering the degree of freedom in selecting the film forming conditions, it is practical to use 2 to 4 layers. The second object is to form an electrode group pattern having a gate electrode and other wiring electrodes on an insulating substrate when manufacturing the thin film transistor, and then form a gate insulating film so as to cover the electrode group. The forming step includes a step of forming a film while sequentially moving without breaking a vacuum in a plurality of insulating thin film forming chambers arranged in series from a thin film having a small etching rate to a thin film in order from a thin film, and then forming a thin film semiconductor pattern. After forming, a step of providing an electrode extraction hole by dry etching with a fluorine compound gas using a predetermined register mask pattern in the gate insulating film, exposing a part of the electrode group provided on the insulating substrate; At both ends of the semiconductor pattern, a drain electrode and a source electrode are provided separately from each other, and the drain electrode is connected to the electrode extraction hole. And forming a wiring conductor electrically connected to at least one of the drain electrode and the source electrode on an etching step provided in the gate insulating film. This is achieved by a method for manufacturing a thin film transistor. As the gate insulating film, for example, a silicon-based insulator such as a silicon nitride film is preferable. The third object is to arrange a plurality of the thin film transistors on the same insulating substrate in a matrix, connect the gate electrodes of the thin film transistors to form a first bus line, and connect the drain electrodes to form a second bus line. This is achieved by the matrix circuit board serving as the bus line. The fourth object is to dispose a display pixel electrode group on a gate insulating film between thin film transistors provided on the matrix circuit substrate, and to connect each electrode terminal of the display pixel electrode group to a corresponding one of the thin film transistors. An image display comprising a display cell connected to a source electrode and further provided with a counter electrode facing the display pixel electrode group, and further filled with a liquid crystal in a gap between the display pixel electrode group and the counter electrode and hermetically sealed. This is achieved by the device. Note that the display pixel display can be provided in advance on the same surface as the gate electrode, instead of being formed on the gate insulating film. In this case, the gate insulating film on the display pixel electrode is removed by etching. From the source electrode of the thin film transistor.

[Action]

In the present invention, since the etching rate of the gate insulating film in contact with the semiconductor pattern is set higher than that in the lower part depth direction, the side etching amount in the upper part of the gate insulating film is larger than that in the lower part, Thus, the gate insulating film can be inclinedly etched.

【Example】

Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 (a) is a cross-sectional view of a thin film transistor to which the present invention is applied, and FIG. 1 (b) is a graph showing dry etching rate and gate insulation of a silicon nitride film used for a gate insulation film by using a fluorine compound gas. 3 schematically shows a profile of a hydrogen content in a film in a depth direction. In the figure, 1 is an insulating substrate such as a glass substrate, 2 is a gate electrode made of a metal film such as chromium, 3 is a gate insulating film made of a silicon-based insulating thin film, and 4 is a semiconductor made of an amorphous silicon film. Film patterns 51 and 61 are semiconductor films made of an n-type amorphous silicon film to which phosphorus (P) is added.
62 is a metal film such as aluminum, 5 is a drain electrode,
Reference numeral 6 denotes a source electrode. When the present invention is applied, the film quality of the gate insulating film 3 is changed in the depth direction of the film as shown in FIG. The point is that it gets larger as you get closer and smaller as you get away. In the present example, the conditions for forming the silicon nitride film were changed within a range where the N / Si ratio in the gate insulating film was 1.3 or more. The film density is changed by changing the hydrogen content in the film, and the etching rate has a distribution in the depth direction. Hereinafter, a manufacturing process of the thin film transistor will be described with reference to FIG. FIG. 2 (a) shows a manufacturing process flow of the thin film transistor shown in FIG. 1, and FIG. 2 (b) shows a plasma CVD method.
The (C hemical V apor D eposition) device, a block diagram of a case where the gate insulating film 3 and the amorphous silicon film 51 and 61 of the amorphous silicon film 4, n-type. Second
In FIG. 2B, reference numeral 101 denotes a load chamber, 102 denotes a gate insulating film forming chamber, 1020 denotes a control unit for controlling gate insulating film forming conditions, 103 denotes a semiconductor film forming chamber, and 104 denotes an n-type. Reference numeral 105 denotes a semiconductor film formation chamber, and reference numeral 105 denotes an unload chamber. The outline of the manufacturing process of the thin film transistor shown in FIG. 1 will be described below with reference to FIG. Step (A): A metal film such as a chromium film (Cr) film is formed on an insulating substrate 1 such as a glass plate by a sputtering method or the like, and a pattern of the gate electrode 2 is formed by well-known photoetching. Step (B): the substrate on which the gate electrode pattern is formed is
It is set in the load chamber 101 of the plasma CVD apparatus shown in FIG. 2B, preheated, and the load chamber 101 is evacuated. After that, the substrate is transferred to the gate insulating film forming chamber 102,
While introducing a reaction gas such as silane, nitrogen, and ammonia, and changing the film formation conditions such as a reaction gas composition, a film formation power, a film formation gas pressure, and a film formation temperature by a control unit, the control unit shown in FIG. )
A silicon nitride film as the gate insulating film 3 is formed. That is, the control of the hydrogen content in the gate insulating film 3 may be performed, for example, by changing the composition of the source gas component of the CVD as the film thickness increases, and the hydrogen content increases as the flow rate of ammonia with respect to silane increases. . Also, CVD
If the temperature at the time is controlled high, the hydrogen content can be reduced, and if the temperature is controlled low, the hydrogen content can be increased. Step (C): The substrate on which the gate insulating film 3 is formed is transferred to the semiconductor film forming chamber 103, and an amorphous silicon film is formed from silane and hydrogen. Step (D): The substrate on which the amorphous silicon film is formed is transferred to the n-type semiconductor film forming chamber 104, and an n-type amorphous silicon film is formed from silane, phosphine, and hydrogen. Thereafter, the substrate is taken out after cooling in the unloading chamber 105. (E) Step: A silicon-based semiconductor film island pattern 4 made of an amorphous silicon film or the like is formed by a known photoresist step and dry etching. Step (F): a gate insulating film 3 made of a silicon-based insulating thin film by a well-known photoresist process and dry etching.
Is selectively etched, and the terminal of the gate electrode is obtained. This etched portion is not shown in FIG. (G) Step: A metal film such as aluminum is formed by a sputtering method, and electrode patterns 52 and 62 made of a metal film are formed by a known photoetching step. Next, the n-type amorphous silicon film on the channel is separated into 51 and 61 by well-known dry etching to form a drain electrode 5 and a source electrode 6. Thus, the thin film transistor shown in FIG. 1 is completed.
The point where the present invention is applied is that in the step (B), the dry etching rate by the fluorine compound gas is changed by giving the distribution of the hydrogen content of the silicon nitride film in the thickness direction. Hereinafter, the effect of the present invention will be described with reference to FIG. 3 showing the connection between the drain bus line and the drain terminal at the step of etching the gate insulating film. FIG. 3 is a diagram showing the flow of the process, in which 1 is an insulating substrate, 3 is a gate insulating film, 9 is a drain bus line, 9 'is a drain terminal, and 10 is a register pattern. The step (A) shows a state in which a resist pattern 10 for etching the gate insulating film 3 is formed, and the step (B) shows an etching process when the gate insulating film 3 is processed by dry etching using a fluorine compound gas. (C) Step is a state in which the etching is completed. (D) Step is to remove the resist pattern 10 and then connect the drain bus line 9 and the drain terminal 9 ′ through the etching step of the gate insulating film 3. This shows the situation. When the gate insulating film is etched, in the step (B),
As indicated by the arrow, the etched surface enters below the resist pattern 10. With the application of the present invention, the amount of the etched surface entering below the resist pattern 10 increases in the upper layer portion of the gate insulating film 3 (the side closer to the resist pattern 10). As a result, in the step (C) where the etching is completed, the etching step of the gate insulating film 3 becomes forward tapered and gentle. Therefore, the connection between the drain bus line 9 and the drain terminal 9 ′ at the etching step of the gate insulating film 3 can be completed. For example, when the wiring width of the drain bus line 9 is 10 μm, the thickness of the thin film forming the wiring is substantially the same as the thickness of the silicon nitride film, and the etching step of the silicon nitride film is steep and almost perpendicular. Often has a wiring resistance of 10 kΩ or more, and sometimes breaks. Such a problem is solved by applying the present invention. The same effect is obtained as shown in FIG. 5 (b).
This is also seen when the source electrode 6 of the thin film transistor and the display pixel electrode 7 made of tin oxide or indium oxide are connected through the etching step 3 ′ of the gate electrode 3. In other words, the silicon nitride film 3 on the display pixel electrode 7 shown in FIG. 5B is removed by dry etching using a fluorine compound gas. Since the etching rate is made higher than that of the lower layer, the etching step of the silicon nitride film can be made to have a forward taper and a gentle slope as in FIG. 3 (c). As a result, the reliability of the connection between the source electrode 6 and the display pixel electrode 7 can be significantly improved. For example, when the etching step of the silicon nitride film is steep and almost perpendicular as shown in FIG. 5B, connection failure often occurs. However, the application of the present invention has eliminated these problems. In the present embodiment, a silicon nitride film is used as the gate insulating film 3. In this case, however, the characteristics of the thin film transistor itself shown in FIG. 1 can be improved, and favorable results can be obtained. This will be described in detail below. The silicon nitride film has a stoichiometric composition Si ₃ N ₄ (N / S
At an i ratio of 4/3), the film has a low etching rate and a high withstand voltage (dielectric breakdown electric field). But plasma CV
When a stoichiometric silicon nitride film is formed by the D method or the like, many Si dangling bonds (unbonded hands) are present, and the thin film transistor applied to the gate insulating film has good stability against gate voltage stress. It cannot be said that. Therefore, it is necessary to reduce the Si dangling bonds (often accompanied by an increase in the hydrogen content) by setting the composition of the gate insulating film 3 in the region in contact with the semiconductor film pattern 4 to be N / Si ≧ 4/3. That is, as the composition of the silicon nitride film used for the gate insulating film 3 approaches the semiconductor film pattern 4, increasing the composition N / Si ratio is effective for stabilizing the thin film transistor. The change in the film quality in the thickness direction of the silicon nitride film is the same as that in the present invention. In other words, by applying the present invention, it is possible to improve the characteristics of the thin film transistor itself as well as the reliability of the electrode connection and the wiring. The effects described above are caused by changing the film quality of the gate insulating film 3 in the film thickness direction and increasing the dry etching rate by the fluorine compound gas closer to the semiconductor film pattern 4 (upper layer). In this embodiment,
A silicon nitride film is used as the gate insulating film to change the film quality such as its composition.However, oxygen is added to the silicon-based insulating thin film used for the gate insulating film, and the amount of addition is changed in the thickness direction from the surface of the insulating film. The larger the distance, the larger it may be. To change the film quality of the silicon-based insulating thin film, the film-forming conditions may be changed manually. However, as in this embodiment, a control unit such as a minicomputer or a microcomputer is used to form the silicon-based insulating thin film. It is effective to equip the device. Further, the gate insulating film 3 needs to have a certain thickness or more in order to guarantee the electric breakdown voltage. However, in order to increase mass productivity, the film forming chambers are separated into 2 to 4 pieces and are arranged in series. It is possible to form films sequentially without breaking the vacuum. Embodiment 2 This embodiment relates to an image display device comprising a liquid crystal display device using the thin film transistor and the active matrix circuit substrate shown in Embodiment 1, and FIG. 4 (a) is a plan view of a main part thereof, and FIG. (B) shows a sectional view. In the figure, reference numeral 80 denotes the thin film transistor 89 shown in FIG.
An active matrix circuit board having a drain bus line 9 connected to the drain electrode 5, a gate bus line 8 connected to the gate electrode 2, and a display pixel electrode 7 connected to the source electrode 6, 20 is a polarizing plate, 21 is A color filter, 23 is an opposite electrode of the display pixel electrode 7 made of a transparent conductive film and also made of a transparent conductive film, 22 and 26 are protective films, 24 is an alignment film, and 25 is a space filled therein. Shows liquid crystal. This example of the image display device is for color display with the above configuration. Further, this display device can be easily manufactured by a manufacturing process similar to that of a known color liquid crystal display device. In an actual display device, in addition to the configuration shown in FIG. 4, various electric circuit control systems and illumination means from the back are provided as well-known image display driving means. Description is omitted. Embodiment 3 In this embodiment, an example of a thin film transistor having a multilayer gate insulating film in which a gate insulating film is composed of a plurality of films having different etching rates will be described. Therefore, the thin film transistor of this embodiment is basically the same as the first embodiment except for the structure of the gate insulating film. An embodiment of the present invention will be described below with reference to FIGS. FIG. 6 is a sectional view of a thin film transistor to which the present invention is applied. In the figure, 1 is an insulating substrate such as a glass substrate, 2 is a gate electrode made of a metal film such as chromium, 31 is a first layer of a gate insulating film 3 made of a silicon-based insulating thin film, and 32 is a silicon-based film. The second layer of the gate insulating film 3 made of an insulating thin film, 4 is a semiconductor film pattern made of an amorphous silicon film, and 51 and 61 are semiconductor films made of an n-type amorphous silicon film to which phosphorus is added. , 52 and 62 indicate metal films such as aluminum, 5 indicates a drain electrode, and 6 indicates a source electrode. The application of the present invention is that the gate insulating film 3 has a two-layer structure, and the dry etching rate using a fluorine compound gas is higher in the second layer than in the first layer. Hereinafter, a manufacturing process of the thin film transistor will be described with reference to FIG. Figure 7 (a) is a plasma CVD for forming a gate insulating film 3 and the amorphous silicon film 4, n-type amorphous silicon film 51 and 61 of the thin film transistor shown in FIG. 6 (C hemical V a
The por D eposition) device, the diagram (b) (A) ~
(H) shows a manufacturing process flow of the thin film transistor. Step (A): A metal film such as a chromium (Cr) film is formed on an insulating substrate 1 such as a glass plate by a sputtering method or the like, and a pattern of the gate electrode 2 is formed by well-known photoetching. Step (B): set in the load chamber 101 of the plasma CVD apparatus shown in FIG.
Evacuate 101. Thereafter, the sample is transferred to the first film forming chamber 1021, and a reaction gas of silane, nitrogen, and hydrogen is introduced to form a first-layer silicon-based insulating thin film 31 made of a silicon nitride film as the first layer of the gate insulating film 3. Film. The insulating thin film 31 contained 1.5 × 10 ²² / cm ³ of hydrogen atoms, and the atomic ratio of N / Si was about 1.3. (C) Step: The sample 100 on which the first-layer silicon-based insulating thin film 31 is formed is transferred to the second film-forming chamber 1022, and a reaction gas of silane nitrogen and hydrogen is introduced thereinto to form the second layer of the gate insulating film 3. A second-layer silicon-based insulating thin film 32 made of a silicon nitride film or the like is formed. In this case, the film forming conditions such as the reaction gas composition and the film forming power are changed to those of the first-layer silicon-based insulating thin film 31, and the second-layer silicon-based insulating thin film 32 is used as the first-layer silicon-based insulating thin film. Select so that the etching rate is higher than 31. In this example, hydrogen atoms are used as the insulating thin film 32 for 2.
It contained 5 × 10 ²² / cm ³ and had an N / Si atomic ratio of about 1.4. The etching rate is about 5 times faster than that of the first insulating thin film 31.
It was twice as fast. The difference between the practical etching rates of the first layer and the second layer insulating film is sufficient if it is 5 to 10%, and does not need to be extremely large. (D) Step: The sample on which the gate insulating film 3 is formed is transferred to the third film forming chamber 103, and an amorphous silicon film is formed from silane and hydrogen. Step (E): The sample on which the amorphous silicon film is formed is transferred to the fourth film formation chamber 104, and an n-type amorphous silicon film is formed from silane, phosphine, and hydrogen. Then unload room
Remove the sample after cooling at 105. (F) Step: A silicon-based semiconductor film island pattern 4 made of an amorphous silicon film or the like is formed by a known photoresist step and dry etching. Step (G): a gate insulating film 3 made of a silicon-based insulating thin film by a well-known photoresist process and dry etching.
Is etched, and the terminal of the gate electrode is obtained. In addition,
This etched part is not shown in FIG. Step (H): A metal film such as aluminum is formed by a sputtering method, and the electrode patterns 52 and 62 made of the metal film are formed by a known photoetching process. Next, the n-type amorphous silicon film on the channel is separated into 51 and 61 by well-known dry etching to form a drain electrode 5 and a source electrode 6. Thus, the thin film transistor shown in FIG. 6 is completed.
The steps to which the present invention is applied are (B) and (C). The effects of the present invention will be described with reference to FIGS. FIG.
In this example, the thin film transistor shown in FIG. 6 is applied to an active matrix substrate, and a source electrode 6 and a display pixel electrode 7 made of tin oxide or indium oxide are connected through an etching step of a gate electrode 3. The display pixel electrode 7
The upper silicon nitride film is removed by dry etching using a fluorine compound gas, but by applying the present invention,
Since the etching rate of the second layer 32 of the gate insulating film 3 is higher than that of the first layer 31, the etching step of the silicon nitride film can be made gentle as shown in the figure. As a result, the connection reliability between the source electrode 6 and the display pixel electrode 7 can be significantly increased as in the case of the first embodiment. For example, if the etching step of the silicon nitride film is steep and close to a right angle, connection failure often occurs. However, application of the present invention has eliminated these problems. This becomes clearer in the case of the example shown in FIG. Ninth
In the figure, the thin film transistor according to the present invention is applied to an active matrix substrate, and an external connection terminal 9 ′ of a drain bus line 9 depending on a gate insulating film 3 is connected to a gate electrode 2 or a gate bus on an insulating substrate 1 such as a glass substrate. This is an example in which they are arranged on the same plane as the line 8. The electrodes and the electrode group such as wiring on the insulating substrate 1 are all formed in the same process. The drain bus line 9 is obviously connected to the connection terminal 9 ′ through a gentle etching step of the gate insulating film 3. The wiring width of the drain bus line 9 is 10 μm, the thickness of the thin film constituting the wiring is almost the same as the thickness of the silicon nitride film, and the etching step of the silicon nitride film is steep and nearly perpendicular as in the conventional case. In such a case, the wiring resistance is often 100 kΩ or more, sometimes leading to disconnection. However, in the case of FIG. 9, since the present invention is applied, the problems of increasing the resistance of the wiring and disconnection described above are eliminated. Such an effect of the present invention is caused by forming the gate insulating film 3 in a two-layer structure and increasing the etching rate in etching the gate insulating film 3 on the upper (second layer) side. A similar effect can be obtained by forming the gate insulating film 3 into a multilayer structure of three or more layers and increasing the etching rate in the upper layer. However, in consideration of capital investment for mass production, two to four layers are set. Is appropriate. Further, in order to keep the interface state between the layers constituting the gate insulating film 3 clean, it is desirable to form the films continuously without breaking the vacuum. When the film forming chambers of the respective layers constituting the gate insulating film 3 are arranged separately in series as in this embodiment, there is an effect of improving the productivity. Further, according to the present invention, there is an effect that the characteristics of the amorphous silicon thin film transistor itself can be improved and defects such as cloudiness of the amorphous silicon film as the semiconductor film can be prevented. This will be described with reference to FIG. FIG. 10 (a) is a characteristic curve showing the effect of the present invention, in which the relative mobility of the first-layer insulating film 31 with respect to the total thickness of the gate insulating film 3 and the effective mobility and threshold voltage variation of the thin-film transistor. It shows the relationship with the value. FIG. 10 (b) is a curve diagram showing the principle. FIG. 10 (b) shows the reaction gas composition (ammonia / silane gas introduction ratio) when forming a silicon nitride film and the etching rate of the fluorine compound gas (for example, methane tetrafluoride or sulfur hexafluoride). This graph shows the relationship between the effective mobility of an amorphous silicon thin film transistor using it as a gate insulating film and the amount of change in threshold voltage due to gate voltage stress. In the plasma CVD apparatus used by the inventors, even if the ammonia / silane gas introduction ratio is 0, the nitrogen / silane gas introduction ratio in the reaction gas is adjusted so that the N / Si ratio of the silicon nitride film becomes 1.3 or more.
15. The deposition power (frequency: 13.56 MHz) was 500 W, the reaction gas pressure was 79.8 Pa, and the deposition temperature was 300 ° C. When the ammonia / silane gas introduction ratio is increased, the hydrogen content and the nitrogen content of the formed silicon nitride film are increased, the density of the film is reduced, and the dry etching rate for increasing the silicon nitride is increased. In addition, as the ammonia / silane gas introduction ratio is increased, the number of dangling bonds of silicon in the silicon nitride film is reduced. Therefore, the threshold due to the gate voltage stress of the amorphous silicon thin film transistor using the silicon nitride film as the gate insulating film. Although the value voltage shift can be reduced, stress is applied to the amorphous silicon film / silicon nitride film (the amorphous silicon film is laminated on the silicon nitride film), and the effective mobility is reduced. FIG. 10 (a) shows the thin film transistor shown in FIG. 6, in which the first layer 31 of the gate insulating film 3 is made of a silicon nitride film which has a low dry etching rate but increases the effective mobility. The dry etching rate is high in the layer 32, the effective mobility of the thin film transistor using the silicon nitride film for suppressing the threshold voltage shift due to the gate voltage stress, the threshold voltage variation due to the gate voltage stress, and the first layer This shows the relationship between the relative thickness of the silicon nitride film 31 (the thickness of the gate insulating film is 1). Obviously, the first layer 31
And the features of the second layer 32 are utilized. In particular, it can be seen that this is effective when the relative thickness of the first silicon nitride film 31 is set to 0.2 to 0.8. Further, it is easily understood that the inclined etching of the gate insulating film is possible. An amorphous silicon film used as a semiconductor film of an amorphous silicon thin film transistor has a large compressive stress (5 × 10 5
⁸ Pa or more). Therefore, depending on the stress of the gate insulating film, when the total stress of the semiconductor film / gate insulating film increases toward the compression side, the film tends to become cloudy. In the example shown in FIG. 10, the silicon nitride film forming the first layer 31 of the gate insulating film 3 has a compressive stress, and the silicon nitride film forming the second layer 32 has a tensile stress. First
By adjusting the thicknesses of the layer 31 and the second layer 32, the total stress of the gate insulating film can be adjusted. Therefore, by adjusting the total stress of the semiconductor film / gate insulating film,
This has the effect of preventing defects such as cloudiness of the amorphous silicon film constituting the semiconductor film 4. The effects described above are produced when the gate insulating film 3 has a two-layer structure, and each layer satisfies a certain film quality condition. In the example described above, the gate insulating film 3 has two layers, but may have more layers. However, considering the efficiency and capital investment in mass production, as described above, it is appropriate to use two to four layers. Further, in the above example, each layer constituting the gate insulating film 3 is a silicon nitride film, and the film quality of the first layer 31 and the second layer 32 is determined by the film forming conditions (in the above example, the reaction gas composition is taken up. However, the reaction gas introduction amount, the reaction gas pressure, the film formation power, the power supply frequency, the film formation temperature, and the like may be changed). However, in order to obtain the same effect of the present invention, the lower insulating film (for example, 31) constituting the gate insulating film 3 may be made of a silicon oxide film or may be compared with a layer on the side in contact with the semiconductor film. A silicon nitride film with a large amount of added oxygen may be used. The thin-film transistor of Example 3 having the gate insulating film 3 made of the multilayer insulating film was used to assemble an active matrix circuit board in the same manner as in Example 2 and an image display apparatus using the same as in FIG. Thus, a device having the same characteristics as in Example 2 could be obtained.

【The invention's effect】

According to the present invention, the etching rate of the layer in contact with the semiconductor film of the gate insulating film is higher than that of the lower layer, and the amount of side etching in the upper layer can be increased, so that the gate insulating film can be inclinedly etched. become. Accordingly, in an active matrix circuit substrate or an image display device using such a thin film transistor, the reliability of connection through the etching step between the gate insulating film of the source electrode and the display pixel electrode of the thin film transistor is increased, and the etching step of the gate insulating film is not increased. This has the effect of preventing an increase in wiring resistance and a disconnection accident due to this.

[Brief description of the drawings]

FIG. 1A is a cross-sectional structural view of a thin film transistor according to one embodiment of the present invention, FIG. 1B is a curve diagram illustrating the properties of a gate insulating film of the thin film transistor shown in FIG. 1A,
FIG. 2 (a) is a manufacturing process diagram of the thin film transistor shown in FIG. 1 (a), FIG. 2 (b) is a block diagram of a manufacturing apparatus showing one embodiment of a manufacturing method according to the present invention, and FIG.
4A and 4B are a plan view and a sectional view, respectively, showing an embodiment of an image display device according to the present invention.
FIGS. 7A, 7B and 7C are sectional views of a conventional thin film transistor and an active matrix circuit substrate, FIG. 6 is a sectional view of a thin film transistor according to another embodiment of the present invention, and FIG. FIG. 7 is a schematic view of a manufacturing apparatus as an embodiment for manufacturing the thin film transistor of the present invention, FIG. 7 (b) is a manufacturing process diagram of the thin film transistor of the present invention using the apparatus of FIG. 7 (a), and FIGS. FIG. 9 is a sectional view of a matrix circuit board showing the effect of the embodiment of the present invention.
FIG. 10A is a characteristic curve showing the effect of the thin film transistor of the present invention, and FIG. 10B is a characteristic curve for explaining the principle.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode 3 ... Gate insulating film 3 '... Etching step part of gate insulating film 4 ... Semiconductor film, 5 ... Drain electrode 6 ... Source electrode, 7 ... Display Pixel electrode 8 Gate bus line 9, Drain bus line 9 'Drain terminal 51, 61 N-type semiconductor film 52, 62 Metal film, 20 Polarizing plate 21 Color filter 22, 26: Protective film 23: Counter electrode, 24: Alignment film 25: Liquid crystal 31: First-layer gate insulating film 32: Second-layer gate insulating film 80: Active matrix circuit Substrate 89 Thin film transistor 101 Load chamber 102, 1021, 1022 Gate insulating film forming chamber 1020 Control unit of gate insulating film forming chamber 103 Semiconductor film forming chamber 104 n Type semiconductor film deposition chamber 105: unloading chamber, 107: cathode electrode 108: high-frequency power source

Continued on the front page (72) Inventor Mifumi Yoritomi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd.Production Technology Research Laboratory (72) Inventor Akihiro Kusunoki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. (72) Inventor Mitsuo Nakatani 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratory (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1/136 500

Claims (6)

(57) [Claims] An electrode group having a gate electrode and other wirings and electrodes provided separately on an insulating substrate, and a gate insulating film formed to cover the electrode group. A semiconductor film pattern disposed at least on the gate insulating film on the gate electrode;
A drain electrode and a source electrode disposed at both ends of the semiconductor film pattern so as to overlap with at least the gate electrode; and at least one of the drain electrode and the source electrode and the other wiring electrode are provided on the gate insulating film. And a wiring conductor electrically connected to at least one of the drain electrode and the source electrode through the opening, and being present on an etching step provided in the gate insulating film. In the thin film transistor, the gate insulating film is formed of a gate insulating film whose etching rate is gradually reduced as the distance from the surface to the substrate side in the depth direction is increased, and the opening provided in the gate insulating film is formed. Steps or slopes are provided on the wall surface of the opening to substantially reduce the inclination of the opening wall surface. Thin-film transistor was formed by. 2. The gate insulating film is composed of a silicon-based insulating thin film, and hydrogen or oxygen is contained in the gate insulating film. In the case of hydrogen, the content on the surface side of the insulating film is large and the depth is large. 2. The thin film transistor according to claim 1, wherein the concentration gradient gradually decreases, and in the case of oxygen, the concentration on the surface side of the insulating film decreases and gradually increases in the depth direction. 3. The semiconductor device according to claim 2, wherein the gate insulating film has a multilayer structure having different etching rates, and an outermost insulating thin film in contact with the semiconductor pattern is a thin film having a high etching rate and is provided on the substrate side in the internal depth direction. 2. The thin film transistor according to claim 1, wherein the thin film transistor is laminated with a thin film having a gradually lower etching rate as the distance from the thin film transistor increases. 4. The method of manufacturing a thin film transistor according to claim 1, further comprising: forming an electrode group pattern having a gate electrode and other wiring electrodes on an insulating substrate; and covering the electrode group. As a step of forming a gate insulating film, a step of forming a film while sequentially moving without breaking vacuum in a plurality of insulating thin film forming chambers arranged in series from a thin film having a small etching rate to a thin film having a large etching rate is included. Then, after forming a thin-film semiconductor pattern, an electrode extraction hole is provided on the gate insulating film by dry etching with a fluorine compound gas using a predetermined resist mask pattern, and a part of the electrode group provided on the insulating substrate is exposed. And providing a drain electrode and a source electrode at both ends of the thin-film semiconductor pattern at a distance from each other. Manufacturing method of a thin film transistor comprising and a step connected form the wiring electrodes on the substrate through the electrode extraction hole. 5. A thin film transistor according to claim 1, 2 or 3, which is arranged in a matrix on the same insulating substrate, wherein said gate electrode of each thin film transistor is connected to form a first bus line, and said drain electrode Connect the second
Matrix circuit board to be used as a bus line. 6. A display pixel electrode group is provided between thin film transistors provided on a matrix circuit substrate according to claim 5, and each electrode terminal of said display pixel electrode group is connected to a corresponding source electrode of said thin film transistor. An image display device further comprising a counter electrode provided opposite to the display pixel electrode group, and a liquid crystal filled and sealed in a gap between the display pixel electrode group and the counter electrode.